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THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Fall 2000 Cover Story Synplicity Chief Technology Officer Ken McElvain Talks About the Future of Programmable Logic R Xcell journal Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS PRODUCTS New Virtex Development Board New HDLC and ADPCM Cores APPLICATIONS Using Block-level Incremental Synthesis SOFTWARE New WebPack Integrated Synthesis Environment NEWS IBM and Xilinx Partnership— PowerPC Processors in Virtex-II FPGAs

Xilinx Xcell Journal 37 - complete issue (Q3 2000)...to success are complex and they change constantly. It’s difficult for any one company to master all of the necessary functions

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Page 1: Xilinx Xcell Journal 37 - complete issue (Q3 2000)...to success are complex and they change constantly. It’s difficult for any one company to master all of the necessary functions

T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

Fall 2000

Cover StorySynplicity Chief Technology OfficerKen McElvain Talks About theFuture of Programmable Logic

R

Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

PRODUCTSNew Virtex Development Board

New HDLC and ADPCM Cores

APPLICATIONSUsing Block-levelIncremental Synthesis

SOFTWARENew WebPack IntegratedSynthesis Environment

NEWSIBM and XilinxPartnership— PowerPC Processors in Virtex-II FPGAs

Page 2: Xilinx Xcell Journal 37 - complete issue (Q3 2000)...to success are complex and they change constantly. It’s difficult for any one company to master all of the necessary functions

rogrammable logic technology is advancing at a phenomenal rate; our industry is booming, busi-ness has never been better, and Xilinx is growing faster than we ever imagined. Our devices are

bigger, faster, easier to use, and less expensive than ever before, and there are many new developmenttools, support products, and services being offered by a growing number of companies. In addition, as we add new features, increase performance, and lower prices, many new types of applications areopening for our products-and that fuels even more growth and more innovation.

The phenomenal growth of programmable logic technologies is the result of teamwork; we didn’t do italone. As you can read in the article on page 4 from our CEO, Wim Roelandts, Xilinx is based on apartnership model that includes our technology partners, our stock holders, and you, our customers.Clearly, our sustained success is very dependent on the success of those who work with us. That’s onereason why we work closely with our technology partners and support their development of new prod-ucts and services. It’s also why we work closely with you, to make sure we are creating the right prod-ucts for your current and future needs. It’s also why we publish this journal.

Communication is Key

Communication is necessary to sustain a healthy partnership, and effective communication requires atwo-way process. This journal intends to bring you the latest information about programmable logictechnologies and how to use them. It also brings you the insights of industry insiders about the trendsand developments that will affect you in the future, so you can make informed decisions today. We arealways striving to include articles that make a positive difference for you, and present those articles in aformat that is interesting and easy to read.

Your feedback is important because we want to continue bringing you the types of articles that mattermost to you. After all, this is your journal; it exists only for your benefit. So, let me know what you thinkabout our new Xcell Journal; your suggestions for improvement are always welcome.

Write for Xcell

If you have a novel solution to a common design problem or if you have developed a unique design,why not share it with your peers? Writing technical articles for Xcell is easy, it can gain you a modestamount of fame and fortune, and it’s a great way to promote your company. Send me an e-mail withyour article ideas, and I’ll send you more details.

Thanks for your continued support of this journal. I hope you like the new design.

Carlis CollinsEditor

L E T T E R F R O M T H E E D I T O R

EDITOR Carlis [email protected]

SENIOR DESIGNER Andy Larg

BOARD OF ADVISORS Dave StiegMike SeitherPeter Alfke

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3450Phone: 408-559-7778FAX: 408-879-4780©1999 Xilinx Inc.All rights reserved.

Xcell is published quarterly. XILINX, the Xilinxlogo, and CoolRunner are registered trademarksof Xilinx, Inc. Virtex, LogiCORE, IRL, Spartan,SpartanXL, Alliance Series, Foundation Series,CORE Generator, IP Internet Capture, IP RemoteInterface, MultiLinx, QPRO, Selecti /0, Select1/0+, True Dual-Port, WebFITTER, WebPACK,ChipViewer, Select RAM, Block Ram, XilinxOnline, and all XC-prefix products are trade-marks, and The Programmable Logic Company isa service mark of Xilinx, Inc. Other brand orproduct names are trademarks or registeredtrademarks of their respective owners.

The articles, information, and other materialsincluded in this issue are provided soley for theconvenience of our readers. Xilinx makes nowarranties, express, implied, statutory, or other-wise, and accepts no liability with respect to anysuch articles, information, or other materials ortheir use, and any use thereof is solely at the riskof the user. Any person or entity using suchinformation in any way releases and waives anyclaim it might have against Xilinx for any loss,damage, or expense caused thereby.

The Partnership Model...

P

Xcell journalXcell journal

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The Xilinx Business “Ecosystem” . . . . . . . . . . . . . . . . . . . . .4

Design Technology Advances Unleash Powerful New FPGA Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Maximizing FPGA Design Performance Using Amplify from Synplicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PowerPC Processors in Virtex-II FPGAs . . . . . . . . . . . . . . . . .13

The MathWorks and Xilinx take FPGAs into Mainstream DSP . .14

Xilinx DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

IRL Makes Console Switching Faster and More Reliable . . . . .18

LavaCORE - A Configurable Java Processor . . . . . . . . . . . . .20

Inferring Read Only Memory in FPGA Compiler II and FPGA Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Using Block-Level Incremental Synthesis in FPGA Compiler II and FPGA Express . . . . . . . . . . . . . . . . . .24

Lucent Technologies Gets a Time-to-market Advantage . . . . . .27

New HDLC and ADPCM Cores . . . . . . . . . . . . . . . . . . . . . .28

Moving the M8051Ewarp ASIC Core to a Virtex FPGA . . . . . .30

Xilinx WebPACK Software Now Includes ModelSim . . . . . . . .33

New WebPACK Integrated Synthesis Environment (ISE) . . . . .34

Low Power CoolRunner CPLDs . . . . . . . . . . . . . . . . . . . . . .36

PLDs-Your Competitive Edge for High Volume Production . . . . .38

Design Reuse Strategy for FPGAs . . . . . . . . . . . . . . . . . . . .40

Year 2000 Worldwide Xilinx Event Schedules . . . . . . . . . . . .42

CoolRunner CPLDs - Your Best Choice for Battery Operation . . .43

Choices, Choices, and Opinions . . . . . . . . . . . . . . . . . . . . .44

New Virtex XSV Development Board for Creating Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Strathnuey - The Xilinx Technologies Integrator . . . . . . . . . . .48

Tektronix Logic Analyzers - 800 Mbit/sec Using Virtex FPGAs . . .50

McData Uses Xilinx FPGAs for Fibre-channel Switch . . . . . . . .52

The “Flancter” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Distribution Adds Value: Intel StrongARM Supported with Xilinx Spartan-II FPGAs . . . . . . . . . . . . . . . . . . . . . . .57

Product Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Design Technology Advances UnleashPowerful New FPGA CapabilitiesThe Chief Technology Officer at Synplicity talks about the trends that are shaping the FPGA industry.

Contents Fall 2000Cover Story Page 8

Products

Page 46New Virtex XSV Development Board for Creating Intellectual PropertyThe XSV Board, designed for the SIP developer community, provides a flexible, low-cost platform that supports a large set of interesting applications.

New HDLC and ADPCM CoresA strategic partnership with ISS produces advancedcommunications products.

Applications Page 24

Using Block-Level Incremental Synthesis in FPGA Compiler II and FPGA ExpressBlock-Level Incremental Synthesis allows you to modify a subset of a design and then re-synthesize just the modified subset.

Software Page 34

New WebPack Integrated SynthesisEnvironmentFree, comprehensive design environment for CPLDs available over the Web.

News Page 13

IBM and Xilinx Partnership– PowerPC Processors in Virtex-II FPGAsIBM and Xilinx combine cutting edge technologies to create a revolutionary new product.

Page 28

For a Free Subscription to the Xcell Journal E-mail your request to: [email protected].

Please include: 1. Your full name and mailing address. 2. Your job title. 3. Your e-mail address. 4. Your company name. 5. Is this a new subscription or a renewal?

Xcell journalXcell journal

Page 4: Xilinx Xcell Journal 37 - complete issue (Q3 2000)...to success are complex and they change constantly. It’s difficult for any one company to master all of the necessary functions

by Wim Roelandts,CEO, Xilinx

In today’s fastpaced high tech-nology businessclimate, the keysto success arecomplex and

they change constantly. It’s difficult for anyone company to master all of the necessaryfunctions of business management, prod-uct design, manufacturing, marketing,sales, and customer support. And, as thebreadth of required knowledge and expert-ise expands, people are becoming much

more specialized in their jobs, taking amore narrow focus, because there is somuch to master. That’s why it has becomeimperative that high technology compa-nies, such as Xilinx, focus on the keyaspects of their business, to become excel-lent at their core technology and businessprocesses, while partnering with othercompanies that are also the best in whatthey do.

Well managed companies must also learnto partner with their customers to developthe insight and the processes that ensurethe success of each new generation of tech-nology. And, if the company is successful,

its shareholders will profit and will contin-ue to support the company through stockpurchases—a key factor in the economichealth of the company.

This partnership between companies, spe-cialized partners, customers, and share-holders is like an ecosystem where eachpart depends on the others, and theboundaries between each are blurred asthey work closely together. For each part ofthis ecosystem to survive and to thrive, allparts must work well together, in balance,and this must become the primary objec-tive of the company management—if anypart of the ecosystem fails, all will suffer.

VViieewwfrom the top

The Xilinx Business “Ecosystem”

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The Five Habitats

The Xilinx business “ecosystem,” as I seeit, is composed of five main “habitats,” oroverlapping systems:

• The Company - People who focus on theprimary business goals; the directemployees and managers of thecompany.

• Customers - People who not onlybuy products and services but alsoinfluence the design of new prod-ucts.

• Partners - People who support theecosystem through supplying need-ed services to the company (such asmanufacturing and sales, intellectu-al property and design support).

• Investors - People who own thecompany and support it throughtheir continued investment.

• Government - People who have animpact on the overall business envi-ronment by making laws and regu-lations that can affect the company.

Each of these habitats must be healthyand prosperous for the overall ecosys-tem to be healthy and prosperous.

The Company Habitat

For a company to prosper and grow, itmust create and maintain a balancedecosystem. Therefore the company must:

• Determine the core competenciesrequired for long term success andbecome excellent in those key areas.

• Determine which functions can best behandled by other companies (partners),and manage those relationships well.

• Work closely with customers to developthe right products and to provide spe-cialized services.

• Become a learning organization, adapt-ing to the dynamics of the marketplace.

• Be dynamic, adaptive, and free to inno-vate, with room to make mistakes.

• Take good care of its employees by pro-viding a rewarding, satisfying, andfriendly work environment.

• Advanced information about new prod-ucts and new technologies coming fromthe company so they can be prepared.

• Cooperation from the company forproduct development and marketing.

• Constant communication with thecompany to share informationabout trends, and to maintainoverall balance.

• A working relationship that helpsthem manage their business moreeffectively and be more successful.

• Training.

When partners are prosperous andgrowing, customers receive betterservice and a broader range of sup-port products and services.

The Investor Habitat

For investors to prosper and growthey need:

• The company to be well managedand provide good return on invest-ment.

• To have a good understanding ofthe company’s strategy and busi-ness practices.

• To have timely and unbiased informa-tion about the company’s results.

In many cases, employees, customers, andpartners are also company stockholders,and therefore they are doubly motivated tomaintain a healthy environment that sup-ports the long term growth of the compa-ny. This is important because the compa-ny’s ability to borrow money and thereforeits flexibility and adaptability are directlyaffected by the company’s worth on thestock market.

The Government Habitat

To ensure that government supports thecompany and to ensure that the companyis a good corporate citizen, the companymust:

• Educate the government about the com-pany and its products.

• Give feedback on proposed laws and

• Have a Chief Executive Officer who is acoach, not the “quarterback.” Becausethe business “game” is dynamic, thecoach must have competent managersand trust them to fulfill their specificresponsibilities.

The Customer Habitat

For customers to prosper and grow, theyneed:

• A continuous flow of innovation fromthe company to help them create lead-ing edge products and remain competi-tive in their markets.

• Easy access to all of the company’s intellectual property.

• Open channels of communication withthe company to:

- help it create the right products and services, and become a bettercompany

- receive the latest technical and marketing information

The Partner Habitat

For partners to prosper and grow, theyneed:

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policies that can an impact on the com-pany and its industry.

• Build a partnership with local govern-ment to improve the local communityand to reach common goals.

How the Xilinx Ecosystem Works

Our primary responsibility must be todevelop, manage, and balance our businessecosystem if we are to remain the leader inour industry. So, our first task was todecide what key competencies we neededwithin Xilinx and which we could entrustto outside partners.

We have defined four core competenciesthat we must keep withinXilinx:

• Product design and tech-nology development.

• Marketing.

• Customer support.

• Partner relationshipmanagement.

By focusing on these corefunctions, we can put ourresources to best use.

Product Design

Product design is our pri-mary focus because inno-vation is the lifeblood ofany high technology company; we spendmore money on research and developmentthan any of our competitors. We continu-ously strive to create leading edge devicesand support tools that meet the specificneeds of our customers.

Marketing

It’s not enough to create “dream” productswith more and more features. Excellentproducts must consistently meet the needsof our customers and our customers mustbe fully aware of what we offer. It is thefunction of marketing to make sure thatwe are in full communication with ourmarketplace, in both directions.

ners are manufacturing and sales. So,Xilinx has no fabrication facilities or directsales force. These are two of the mostexpensive functions in any company, andthe costs are not fixed. In a cyclic industry,such as our own, we gain a significant costadvantage by outsourcing these functionsto partners who have made it their busi-ness to be the best; plus we gain addedflexibility that helps us weather theinevitable down turns without having tolay off employees or suffer heavy losses.Therefore, within Xilinx, we have dedicat-ed people to manage these relationshipswith our 3rd party manufacturing andsales partners. In addition, we also havededicated marketing people who manage

our relationshipswith our develop-ment tool partners,helping them defineand market theirproducts to our cus-tomers.

For manufacturing,we have partneredwith UMC inTaiwan and Seiko-Epson in Japan.UMC has createdone of the world’sleading IC fabrica-tion facilities, withthe very latest equip-ment and processtechnologies. And,

because it is their business to manufacturesemiconductors, they are always on thecutting edge of process technology.

We work very closely with UMC to devel-op new manufacturing technologies and toensure that our designs can make best useof the highest performance, and leastexpensive, process technologies. Throughthis partnership, we have moved from 0.5µtechnology to 0.15µ in less than five years;and 0.13µ technology is soon to be in use.This fast-paced process migration hashelped us to quickly reduce costs and sig-nificantly increase density, which meansyou get faster, less expensive devices, soon-er. We could not have progressed this

Customer Support

To create superior technology, and makethe world aware of it, goes a long waytoward the success of any company.However, without effective and consis-tent customer support, it’s not enough.Our technology is complex, and to use iteffectively requires an in-depth and con-stantly evolving expertise. That’s why wecreated our in-house staff of highly-trained support engineers and designservices professionals who can quicklyhelp you meet any challenge.

Sometimes the difference between ourproducts and our services blur. For exam-ple, our in-house development tools and

intellectual property are products, buttheir sole purpose is to assist you in cre-ating the best possible designs with theleast time and effort. So, though most ofour revenue comes from the sale ofFPGAs and CPLDs, we must also makesure the best tools and services are avail-able too.

We also work with many third-party con-sultants to provide training, design serv-ices, IP development, tool development,and so on.

Partner Relationship Management

Two of the most important competenciesthat we decided to entrust to outside part-

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quickly with an in house fabrication facili-ty—the costs would have been far toohigh. This partnership has benefited bothcompanies, as well as our customers.

For sales, we use our distributors and inde-pendent sales representatives. Sales is obvi-ously a critical function in any company,and is very expensive. We chose to partnerwith our distributors because Xilinx prod-ucts are a key source of revenue for them,often providing more revenue than anyother product line. Therefore our distribu-tors have a lot of incentive to focus on ourproducts and to use their extensive salesforce to focus on Xilinx. This is anotherwin-win partnership that helps both com-panies adapt to the inevitable ups anddowns of the business cycles. Our cus-tomers also benefit from the broad rangeof services provided by our distributors.

At Xilinx, average revenue per employee is$600K; many companies with in-housesales teams are fortunate to have$200,000/year/employee. By keeping oursales costs low, we can put more resourcesinto research and development whichkeeps us on the leading edge of technolo-gy, and makes our customers and ourinvestors very happy.

For software support, we partner with theindustry’s leading software and develop-ment tool suppliers to make sure that youhave access to the broadest range of toolsand support. We work very closely withthe leading software suppliers to make surethat our tools work well together. Thoughwe have a massive in-house effort for soft-ware development we also know howimportant it is to provide you with thenew tools and processes that are constant-ly being created in the marketplace.

For research, we partner with universitiesand research centers around the world toaccess the latest developments. Plus, theXilinx University Program is helping trainengineering students in the use of pro-grammable logic devices by providingdonations, discounted products, and serv-ices. Today there are over 1200 universitiesusing Xilinx in class labs; about 15% of allof the engineering universities worldwide.

The Xilinx Value System

Values are what holds any organizationtogether and define the boundaries withinwhich its employees can efficiently func-tion. Too often a company’s values areundefined however and this leads to errat-ic results and confusion.

To help us manage and balance the Xilinxbusiness ecosystem, we developed a clearand consistent set of values that we live by.In part, these values are the boundariesthat allow our managers the room to inno-vate and to take ownership of their func-tions. Our values also help to make Xilinxa great place to work which inevitablyleads to better products, happier cus-tomers, and increased profits.

Our values are contained within theacronym “CREATIVE” which stands for:

Conclusion

Many companies—even successful ones—view themselves as adversaries with theircustomers and with their marketplace,often using military tactics and focusingon winning at all cost. We think there is abetter way.

To become successful, and remain com-petitive, high technology companies mustview themselves as part of a synergisticwhole that includes customers, strategicpartners, employees, investors, and gov-ernment. At Xilinx, our role is to maintainthe dynamic balance of this system, and tokeep it growing and expanding in a waythat makes everyone more whole andprosperous.

When you work with Xilinx, you’ll see whata positive difference our “ecosystem” atti-tude can bring to your long term success.

Customer Focused. We exist only because ourcustomers are satisfied and want to do busi-ness with us... and we never forget it!

Respect. We value all people, treating themwith dignity at all times.

Excellence. We strive for “Best in Class” ineverything we do.

Accountability. We do what we say we will doand expect the same from others.

Teamwork. We believe that cooperative actionproduces superior results.

Integrity. We are honest with ourselves, eachother, our customers, our partners, and ourshareholders.

“Very” Open Communication. We share infor-mation, ask for feedback, acknowledge goodwork, and encourage diverse ideas.

Enjoying Our Work. We work hard, arerewarded for it; and we maintain a good senseof perspective, humor, and enthusiasm.

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by Ken McElvainChief Technology Officer, Synplicity, Inc.

In today’s marketplace there is enormous pressure to create increasingly com-plex systems and get those systems to market as quickly as possible. To chal-

lenge these efforts, there is a lack of qualified engineers, industry stan-dards are constantly changing, ASIC development costs are skyrock-

eting, and new technologies are quickly making yesterday’s meth-ods obsolete. These problems are intensified with the fierce

competition for lucrative emerging markets. The risks aresignificant; one equipment vendor estimates the cost

of missing a market window to be more than $1 million a day.

However, there is also good news. Today’smulti-million gate FPGAs offer great

promise for designers confoundedby the limitations of tradition-

al ASIC implementation.Indeed, the increased

Cover StorySynplicity

The Chief Technology

Officer at Synplicity talks

about the trends that are

shaping the FPGA industry.

Design Technology Advances Unleash Powerful New FPGA Capabilities

The Chief Technology

Officer at Synplicity talks

about the trends that are

shaping the FPGA industry.

Design Technology Advances Unleash Powerful New FPGA Capabilities

8

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time-to-market demands and lower devel-opment cost of FPGAs, combined withtoday’s FPGA capacities well in excess of amillion gates, are yielding a profoundincrease in the number of applicationsbeing realized in programmable form.From networking and telecommunicationsdesigners grappling with narrow marketwindows and evolving standards, to abroad scope of designers seeking low-riskrapid prototyping, the number of peopleturning to FPGA solutions is quicklyexpanding.

Engineers Designing both FPGAs and ASICs

Only six years ago, engineers were dividedinto two distinct groups: those thatdesigned ASICs and those that designedwith FPGAs. The FPGA designers wereprimarily schematic based while the ASICdesigners had adopted RTL technologies.These two groups didn’t work together.

Today, things have changed. Many design-ers developing FPGAs are also designingASICs, often at the same time. In addition,designers are now less concerned about theunderlying device technology because thegap between ASIC and FPGA performanceis narrowing. However, ASICs will remainthe technology of choice for certain typesof applications. If a design must operate atthe low end of power consumption or atthe extreme upper end of performance, orif you are designing a very high-volume,cost-sensitive system, an ASIC is likely themost cost-effective solution. If design flexi-bility or remote design upgradability areneeded or if engineering time and risk mustbe minimized, an FPGA is a logical choice.

The SoC Opportunity for FPGAs

The advent of systems on chips (SoCs) ismore than a simple extension of ASICtechnology to higher density. With SoCs,ASIC designers have become systemdesigners, and the event-driven simulationtechnology traditionally used is no longersufficient for verifying functionality.Instead, what designers urgently need is afaster, higher-level, hardware-oriented veri-fication path that accepts actual systeminputs to yield actual system outputs.

that is possible through the emergence offast, dense FPGAs such as the XilinxVirtex FPGAs and synthesis technologiesthat can translate ASIC RTL into multi-ple FPGAs. By building a version of theirdesign in hardware using multipleFPGAs, designers can use RTL prototyp-ing to leapfrog all of the limitations ofsoftware simulation.

FPGAs Offer Design Flexibility

The Internet’s explosive popularity, andthe resulting surge in demand for band-width, has created immense competitivepressure for communications equipmentmakers. To complicate matters, the com-munications market is a minefield of spec-ifications evolving unpredictably towardstandardization. Schemes for carryingvoice and video over the Internet, or theInternet over cable, or any number of vari-ations on the Internet theme bring withthem a multitude of implementationdetails that often must either be ironedout by committees or decided by the market.

Such last minute unpredictability makesbringing complex communications equip-ment to market quickly even more diffi-cult. Equipment vendors who hope toexploit the high-density and high-volumeeconomics of ASIC technology risk every-thing should a last minute protocolchange force a silicon re-spin. Realizingthis, increasing numbers of equipmentmanufacturers are instead opting for thefast turnaround and flexibility offered by FPGAs.

Fortunately, just such an approach exists inRTL prototyping, a methodology beingadopted widely by both ASIC vendors andsystem houses.

In contrast to conventional ASIC designerswho tend to focus on the functions withintheir chips, SoC designers must give muchmore consideration to the system-levelnature of the device’s inputs and outputs.

Software simulation, which checks circuitfunctionality against a blast of test vectors,falls short of allowing system I/O to betested. Other drawbacks of software simu-lation are well known; it is too slow andcan’t reproduce electromechanical interac-tions such as fetching data from a drive.Simulation can take as much as 60 percentof the design cycle time and require toomany iterations between RTL and gate-level implementation. Also, it does not allow for co-verification of hardwareand software.

These roadblocks stand in the way of whatSoCs require. For example, consumer andcommunication designs (areas of greatpromise for SoCs) compete within tighttime-to-market windows that suffer whendebugging takes many iterations throughlong cycles of simulation and synthesis. Inaddition, many chips for these marketsmust run at high clock rates to verify theircorrect operation. Inadequate verificationof these designs can mean one or more fabre-spins, which can cost over $1 million perre-spin and take up to six months.

To take fuller advantage of the SoC phe-nomenon, designers can instead turn toRTL prototyping, a new methodology

Cover Story Synplicity

9

Today’s multi-million gate FPGAs offergreat promise for designers confoundedby the limitations of traditional ASIC implementation.

-Ken McElvain, Synplicity

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The quick re-configurability of FPGAs car-ries other benefits in addition to accommo-dating shifting specifications. By exploitingthe option for in-system programmability,companies can easily and affordably makefield upgrades, correct bugs and add fea-tures over the Internet, to name just a fewpossibilities.

The Impact of FPGA Technology Advances

FPGA technology usedto be one or two generations behindASICs. However, theincrease in FPGA den-sity and performancehas steadily outpacedthat of ASICs for sometime. Because of theincreasing NRE costsof leading-edge ASICs,the typical ASICdesign is falling fartherbehind the leadingedge of process tech-nology, while FPGAsare becoming processdrivers.

However, taking fulladvantage of state-of-the-art FPGA technolo-gy today presents newand difficult challenges.As FPGA process tech-nology progresses wellinto the deep submicron realm, intercon-nect-dominant delay now poses the samedifficulties for FPGA designers that previ-ously plagued their ASIC counterparts.Traditional schematic or logic synthesis-based programmable design solutions, sim-ilar to the ASIC methodologies of three tofour years ago, lack the ability to adequate-ly account for interconnect effects early inthe design cycle. With today’s highly com-plex circuits and relentless market pressure,it is more important than ever that accurateinterconnect-related performance informa-tion be integral to early design processes.

mented based upon not only traditionaltiming constraints, but also physical con-straints. The nature of FPGA architecturesmakes it possible to perform physical opti-mization techniques during synthesis, forexample, moving registers across regionalboundaries to increase performance.

Physical synthesis offers significant produc-tivity as well as performance advantages toFPGA designers. First, the use of physical

constraints during synthe-sis results in more accuratetiming estimation, elimi-nating time-consumingand tedious design itera-tions common with tradi-tional approaches.Likewise, physical opti-mization during synthesismakes it possible to physi-cally optimize a circuit forthe best possible perform-ance. Combined physicalsynthesis and optimiza-tion techniques can havesignificant cost benefits,enabling designers inmany cases to implementa device in a lower-costspeed grade.

FPGA physical synthesisforms the critical linkbetween state-of-the-artprogrammable technologyand designers seeking toleverage its unique advan-

tages. Such technology opens the door ofopportunity for those faced with today’stough market realities.

Conclusion

Market forces have created a risky environ-ment where the winners and the losers areoften separated by only a small gap of inno-vation. Therefore, it is increasingly impor-tant to produce next-generation designs ontime and within budget, using limitedengineering resources. Today’s programma-ble logic technology and the developmenttools that support them are your keys tosuccess in this dynamic marketplace.

Evolution of Software

Design automation is key to enabling thisnew era of FPGA design. Unfortunately,simply extending interconnect-aware ASICdesign technology to the FPGA domainwon’t work. The interconnect configura-tions and options unique to FPGA archi-tectures cannot be comprehended utilizingASIC physical modeling techniques.Instead, new FPGA-targeted design

automation technology is needed. Suchtechnology must address the difficult taskof bringing accurate information about thephysical interconnection of a programma-ble circuit into the design process withoutextending design cycles.

Fortunately, FPGA design technology isevolving to accommodate the needs ofdesigners in the deep submicron era. Ofparticular significance is FPGA-basedphysical synthesis technology. Physical syn-thesis factors a design’s physical characteris-tics into the synthesis process. During syn-thesis, a design is optimized and imple-

Cover Story Synplicity

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by Philippe GarraultTechnical Marketing Engineer, Xilinx, [email protected]

Amplify is a new product from Synplicity® that allows you to addphysical constraints to your design, using the Synplify® PRO syn-thesis engine. It links your RTL code to a floorplan of the targetdevice. You can assign your RTL code to physical regions by graph-ically dropping the logic into these regions. During the synthesisprocess, Amplify will use a set of rules to optimize the RTL codebased on estimated placement and interconnectdelays (into and between regions).

Amplify generates an optimized netlist (.edf file)and a Xilinx constraint file (.ncf file) based on thespecified physical constraints. These files are thenused by the Xilinx Alliance Series 3.1i softwaretools to implement the design.

Improving Maximum Frequency

With Amplify you can iterate the implementation twice. In thefirst pass, you determine the critical paths after place and route. Inthe second pass, you assign physical constraints on these criticalpaths to optimize the netlist. By iterating the second pass, thephysical constraints can be refined according to the place and routepost-layout timing report, until your timing requirements are met.

Another approach is to set several regions prior to implementa-tion. These regions could be a representation of the RTL hierar-chy of the design and each could contain one block (or module)of the design.

Finally, you could also mix these techniques to get a floorplan thatwould not only be a hierarchy representation but you could alsoadd physical constraints on the critical paths regardless of any hier-archy consideration. This is what we did in the following example.

Design Example

The following example shows how to interface Amplify with theXilinx place and route tools. The design presented is a networkapplication, which is divided into a top module driving nine simi-lar sub-modules. This code is implementing FIFOs and largebusses. We targeted a Virtex-E, XCVE1000-7 device.

On the first pass, the project is synthesized then implemented withglobal timing constraints only (without physical constraints).Figure 1 shows a floorplanned view of the design after the first pass.Note that the logic is spread over the chip because, without place-ment constraints, the place and route algorithm has no informa-tion about what logic is crucial for grouping into a region (or thereare too many possibilities). The timing constraints were not met,and the best frequency obtained was 104.6MHz.

After this first implementation, we analyzed thepost-layout timing report to gather information onthe critical path, such as:

• The number of critical paths.

• The start and end points (single or multiple).

• The type of critical path (link with I/O or purelyinternal, wire or bus).

• The number of logic levels.

• The device resources (flip-flop, combinatorial, block RAM, andso on).

On the second pass, the different critical paths were assigned inseparate regions through the Amplify user interface. Figure 2 showsthe physical constraints entered in the synthesis environment forour example.

The regions are floorplanned according to the required designresources, such as block RAM and high fanout nets. . By re-syn-thesizing the design with these physical constraints, a new netlistfile along with a constraint file were created. The place and routesoftware uses these optimized files to constrain the logic on theseparticular areas by placing the critical logic together, shortening netdelays to meet the timing requirements.

If the constraints are not met, the Xilinx floorplanner can give use-ful information about the final layout and determine the preciselogic utilization within a region, or view the exact placement oflogic on the critical path. This can help to resize regions, removeconstraints on non-critical paths, or re-place regions closer togeth-er to drive or share common logic or busses.

Applications Software

In very large designs, interconnect delays are becoming more and more predominant. AmplifyTM is the firstphysical synthesis tool for FPGAs that helps you optimize signal routing delays and achieve timing closure.

Maximizing FPGA Design Performance Using Amplify from Synplicity

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Figure 3 shows the floorplanned view ofthe constrained design in our example.Note that the logic is gathered according tothe constraint file. The best frequencyobtained was 120.1MHz, which is a 12.9%improvement. Using the post-layout tim-ing report and the floorplanner helped usfocus on the critical parts of the design,thus saving time by applying more accurateconstraints, and reducing the number ofiteration needed to meet the timing con-straints.

Interfacing Amplify with Xilinx Tools

Here are some guidelines to help you getthe best performance from these tools:

• Put different critical paths into differentregions. This usually gives better results.

• If the critical path contains lots of logic,two regions can be overlapped: one smallone containing the most critical logic thatneeds to be placed very close together anda bigger one containing the rest of thecritical path.

• Amplify does not currently write con-straints for block RAM or black boxes,thus if the critical path includes theseobjects, use the Constraints Editor andconstrain black-boxes and block RAM inthe UCF file within or close to the regionconstraining the rest of the critical path.Use the following command:

INST p1.qram1 LOC = RAMB4_R0C1:

RAMB4_R7C1, RAMB4_R*C2;

• Applying physical constraints to criticalpaths is more likely to improve results ifthe ratio between routing and logic is infavor of routing (this ratio is given by thepost-layout timing report).

• Slightly moving a region can affect themaximum frequency of your design.

Conclusion

Synplicity’s Amplify Physical Optimizer inconjunction with the Xilinx Alliance Series3.1i software can significantly improveyour design performance. As a result of thenew features and capabilities, you have amore efficient way to visualize and con-strain critical paths of your designs, savingtime in multiple iterations while gettingbetter speed performance.

Applications Software

Figure 1 - floorplanned view of the design on the first pass.

Figure 2 - Physical constraints entered in the synthesis environment.

Figure 3 - Floorplanned view of the constrained design.

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PowerPC Processors in Virtex-II FPGAsby Ann DuftManager of North American PR, [email protected]

IBM and Xilinx recently announced a part-nership to create a new generation of devicesfor use in communications, storage, andconsumer applications. Under the agree-ment, we are working together to embedIBM PowerPC processor cores in XilinxVirtexTM-II FPGAs. The pairing of a low-cost, high performance PowerPC processorcore with customizable FPGA circuitryallows you to create custom chips for yourparticular application at reduced cost and

with faster time-to-market. Availability datesfor the new chips will be announced laterthis year by Xilinx.

The new devices will initially be fabricatedby IBM for Xilinx using advanced IBM chipmanufacturing technologies, including cop-per interconnects which adds to their per-formance. This will enable Xilinx to broad-en its manufacturing volume and geograph-ic diversity, and leverage common foundrymanufacturing processes.

“This joint effort will bring about a newdesign era combining programmable logictime-to-market advantages with the costbenefits of standard cell technology,” saidAndrew Allison, semiconductor industryanalyst. “This is a potent combination.”

“IBM and Xilinx are committed to meetingeach customer’s unique blend of require-ments for cost, design time, and individual-ized function,” said John Kelly, general man-ager, IBM Microelectronics Division. “Thisrequires a variety of chip design options,from standard, off-the-shelf parts

to FPGAs to ASICs. Thisagreement creates both a new approach in chipdesign, as well as a uniquecollaboration between the world’s leading ASICand programmable logicproviders.”

The complementary mar-keting and technologyagreement will enable cus-tomers who choose FPGAsolutions from Xilinx tomore easily migrate to IBM

ASIC and standard product solutions.Customers will factor performance, cost,time-to-market, and volume requirementsin making a determination as to the bestoption for a given application, while usingthe same industry standard PowerPC andIBM’s system-on-a-chip CoreConnect bustechnology across all solutions.

“The combination of technologies will leadto a new level of performance and flexibilityin the semiconductor market,” said Wim

Roelandts, president and CEO of Xilinx.“IBM’s process technology is the mostadvanced in the industry and thePowerPC architecture has become thestandard in communications, enabling usto deliver the highest performance andhighest density products into the marketat the leading edge of technology.”

Under the multi-year agreement, Xilinxwill license IBM’s high-performancePowerPC processor cores and CoreConnectbus for integration into Xilinx FPGAs.IBM and Xilinx will map the resultingdesigns to IBM’s advanced chip manufac-turing processes, keeping Xilinx FPGAs onthe leading edge of technology. IBM willlicense IP from Xilinx to quickly moveleadership process technology to the mar-ketplace. We also plan to explore otherareas of cooperation that could benefit cus-tomers of both companies.

News Partnerships

IBM and Xilinx combine cuttingedge technologies to create a revolutionary new product.

About IBMIBM Microelectronics is the world’sleading ASIC supplier and a key contributor to IBM’s status as a premier information technologyprovider. IBM Microelectronicsdevelops, manufactures, and marketsstate-of-the-art semiconductor andinterconnect technologies, products,and services. Its superior integrated solutions can be found in many ofthe world’s best-known electronicbrands. More information aboutIBM Microelectronics can be foundat www.chips.ibm.com.

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by Per Holmberg Sr. Product Marketing Manager, Xilinx [email protected]

Anne Mascarin DSP Market Segment Manager, The MathWorks [email protected]

The MathWorks and Xilinx have entered astrategic exclusive alliance and joint develop-ment agreement for the system-level creationof FPGA-based DSP designs. The first prod-uct will be the Xilinx System Generator forSimulink(tm) software. Used with TheMathWorks’ popular Simulink system-leveldesign tools, and the Xilinx COREGenerator and LogiCORE DSP algorithms,this software is the first to bridge the gapbetween system-level DSP design and FPGAimplementation, allowing you to easilydesign high-performance DSP applicationsin Xilinx FPGAs. The overall system flow isillustrated in Figure 1.

System Overview

The Xilinx System Generator automaticallygenerates hardware description language(HDL) code from a system representationmodel in Simulink. The HDL design canthen be synthesized for implementation inXilinx FPGAs using standard hardware syn-thesis software. To maximize predictability,density, and performance, the SystemGenerator automatically maps blocks in thesystem design into optimized LogiCOREalgorithms (cores). With only one represen-tation of the design and no manual interven-tion when translating the system-level designto HDL, a common source of errors isremoved.

You can significantly reduce developmenttime by quickly iterating between the sys-tem-level model in Simulink and the hard-ware implementation. This is especially

important for DSP applications, becausemany system-level design trade-offs are basedupon the results of the hardware implemen-tation. Consequently, your developmenttime is significantly reduced, and moreover,even if you are new to FPGAs, you can usethe familiar tools from The MathWorks,along with the Xilinx FPGA developmenttools, to create FPGA-based DSP applica-tions. This combination not only gives youthe ease-of-use and time-to-market advan-tages of FPGAs but also the highest possibleperformance.

The System Generator

The System Generator consists of two com-ponents to help you proceed from a systemmodel to actual hardware. The Xilinx BlockSet (XBS) allows you to embed bit-true andcycle-true models of FPGA-specific circuitryinto a Simulink design, while the SystemGenerator translation software converts theSimulink model into synthesizable VHDL,with Xilinx FPGA hardware as the target.

The XBS provides these elements:

• Parametric blocks for DSP, arithmetic, andlogic functions.

• Gateway blocks to communicate with theSimulink environment, where you haveaccess to the extensive set of Simulink DSPlibraries.*

• Special tokens to support user-definedblack boxes and to invoke the SystemGenerator interface to the Xilinx FPGAsoftware.

The XBS provides the functionality of:

• Simulink S-functions - the Simulink repre-sentation of the XBS.

• Synthesizable VHDL - the hardware repre-sentation of the XBS, including the use ofXilinx cores where appropriate.

The System Generator software token acti-vates the translation software that converts aSimulink model built from XBS elementsinto synthesizable VHDL. The VHDL gen-erated may include cores for appropriatefunctions, as well as corresponding simula-tion models.

New Technologies DSP

The MathWorks and Xilinx takeFPGAs intoMainstream DSPNow you can develop high-performance programmable DSP systems with Xilinx FPGAsusing system design and verification tools fromThe MathWorks, Inc.

The MathWorks and Xilinx takeFPGAs intoMainstream DSPNow you can develop high-performance programmable DSP systems with Xilinx FPGAsusing system design and verification tools fromThe MathWorks, Inc.

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The System Generator graphical user inter-face (GUI) allows you to customize theSimulink simulation. For example, it canhierarchically override fixed-point valueswith doubles. This is particularly useful dur-ing design and debugging.

Simulink

You can model a VHDL design using anycombination of Simulink blocks. By usingthe XBS black box token, you can theninstantiate the design into a generatedVHDL model. The black box customiza-tion GUI encapsulates the design infor-mation necessary for the compiler tocreate the correct instantiationinterfaces. This black box supportallows the abstraction of com-monly used control signalsand ports, and then infersthem within the generat-ed VHDL.

Working inSimulink, you cre-ate a model of thehardware systemas well as one ormore test envi-ronments in which tosimulate the model. When the model is firstentered, simulation is typically performedusing floating-point data to verify its theoret-ical performance. You then add the appro-priate XBS elements, and then convert datatypes to the bit-true representations used inthe hardware implementation. Then themodel is re-simulated to verify its perform-ance with quantized coefficient values andlimited data bit widths, which can lead tooverflow, saturation, and scaling problems.User-defined black boxes can also be incor-porated in the modeling and elaborationprocess. When the model has been convert-ed to a form realizable in the FPGA and its performance meets specification, you can invoke the netlist and the test bench generator.

The Netlister and Mapper

The netlister extracts a hierarchical represen-tation of the model structure annotated withall the element parameters and signal datatypes. A mapper then analyzes the elements

Multi-rate clocking is supported throughtime step information provided during sim-ulation. Each control logic block is given adefault synthesizable behavior which mayrequire alteration to achieve an efficientimplementation.

The Testbench Generator

The testbench generator is an interactive toolthat runs in the MATLAB environment, in

which you capture the inputstimuli and system outputs ofselected simulation runs for con-version to test vectors. The gen-erator converts the captured sim-ulation data into VHDL codethat will exercise the implementedmodel and test its outputs againstthe expected results.

Logic Synthesis

The Xilinx Foundation Series, orany synthesis compiler supportedthrough the Xilinx Alliance Seriessoftware tools, can be used to syn-thesize the control logic and ele-ments for which no hardware macrosexist, and combine all the pieces intoa fully realized netlist. The outputs ofthis back-end process are a bit stream

and an EDIF structural netlist of the hard-ware, annotated with timing information.This netlist can be simulated with the testvectors produced previously from systemsimulations to verify the performance of thecompleted FPGA hardware realization.

Conclusion

With the introduction of the Xilinx SystemGenerator for Simulink, you now have a toolthat makes the job of incorporating FPGAsinto your DSP designs easier than everbefore. Today, Xilinx FPGAs provide youwith the world’s highest-performance pro-grammable DSP solution, supporting appli-cations equivalent to 160 billion MACs. AsFPGA technology continues to advance, it isexpected that by the year 2002, you will haveaccess to a ten million gate FPGA offering0.6 Tera MACS per second.

See www.xilinx.com for more information.

in the hierarchy and creates a VHDLdescription of the design. Where possible,the mapper uses the Xilinx CORE Generatorto generate optimized LogiCORE imple-mentations for specific design elements.

When an element or its parameter valuesimply functionality unavailable in theCORE Generator, the mapper instantiates areference to a parameterized, synthesizable

entity in a synthesis library or your own sup-plied model.The actual hardware entitiesused have additional inputs and outputs forcontrol signals that are not evident at thelevel of abstraction used in Simulink. Themapper inserts the necessary control portsand connects them to control logic blocks.

New Technologies DSP

Figure 1 - Flow diagram.

About The MathWorksThe MathWorks develops technical

computing software for engineers

and scientists in industry and educa-

tion. An extensive family of products,

based on MATLAB and Simulink,

provides high-productivity tools for

solving challenging

mathematical,

computational,

and simulation

problems. For more information see

www.mathworks.com

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by Rufino OlaySr. DSP Product Marketing Engineer, [email protected]

Xilinx DSP consists of the Virtex andSpartan series FPGAs, a wide range of DSPalgorithms, and a comprehensive set of soft-ware tools and prototyping boards. This is acomplete DSP solution giving you the highperformance and system integration ofASICs and ASSPs plus the reconfigurabilityand quick turnaround of standard proces-sors. This ultimate combination provides acomprehensive and robust platform to helpyou create the highest performing repro-grammable signal processing applicationsimaginable.

We’ve created a completedesign flow that guides youthrough the conceptualarchitectural design, verifi-cation, and implementa-tion. Design techniquessuch as parallel processingand distributed arithmetic,coupled with industry-lead-ing hardware platforms,increases sampling rates byan order of magnitude overthat of traditional approach-es; there is no faster DSP solution, anywhere.Table 1 shows a sample listing of algorithmbenchmarks.

Fast, Flexible, and Easy

With Xilinx DSP you can easily createcustomized architectures that give you the

best speed and area utilization for yourparticular needs.

Parallel Operations

Xilinx DSP helps you create the most robustDSP applications by exploiting the paral-lelism that is inherent in DSP mathematicalmodels. Using the vast logic resources thatare present in the Virtex FPGAs, you can cre-ate fully parallel structures that give you theutmost in computational power.

Customizable Data Structures

Unlike fixed-width processors or ASICs,Xilinx FPGAs give you the freedom to cre-

ate custom word lengths for your particularsituations, including different parameterswithin the same design. For example somechannels in your system might requiremore bits of precision than others; you caneasily change the algorithm and the XilinxDSP software will easily accommodate thenew data configuration.

Multiple Data Paths and Channels

Individual arithmetic logic can be linked toseparate data paths or mutually coupled torun parallel operations during individualcycles. This approach is ideal for applicationsconsisting of multiple subtasks that need lit-tle or no interdependency.

Logical Operations

You can easily implement a variety of bit-and byte-wide operations such as barrel shift-ing, comparison, rotation, and accumulationby instantiating any of our numerous coresor by writing your own HDL code to cus-

tomize a particular process.

The MathWorks SimulinkIntegration

Xilinx and The MathWorks (theleader in DSP algorithm tools)have created a strategic alliancethat allows you to build high per-formance DSP systems in XilinxFPGAs using the system designand verification tools with whichyou are already familiar. Theresult is the Xilinx SystemGeneratorTM tool-set which

bridges the gap between your conceptualarchitectural design and the actual transla-tion and implementation of your FPGA-based DSP system.

With the Xilinx System Generator you caneasily experiment with various DSP func-tions and quickly see the algorithmic trade-offs between performance and silicon area.

Core Solutions Xilinx DSP

The World’s Highest-performance Programmable DSP Solution. A New Paradigm in High Performance Digital Signal Processing...

Algorithm Benchmark Unit of Measure

16-bit 160,000,000,000 MAC/s

256 Tap FIR 160 MSPS

1024 pt FFT 41 usec

Reed Solomon Decoder 87 MHz

JPEG Codec 21 MHz

ADPCM 16 MHz

Table 1 - Performance Matrix

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Then you can easily compare the cost andspeed with off-the-shelf DSP devices.

Key Features include:

• Seamless integration; no manual redesignis required.

• No risk of error introduction.

• Only one source code to maintain.

• Floating-point and fixed-point systemsimulation.

• Automatically generates HDL descriptionfor Xilinx FPGAs.

Comprehensive IP Offering

Our extensive selection of IP, including fil-ters, correlators, transforms, FFTs, FECs,integrators, DDS, and math functions, givesyou the power to build large, complexdesigns quickly and effortlessly. Plus, our IPis optimized and parameterized for imple-mentation in our Virtex and Spartan FPGAsso you get the most efficient and fastestimplementation.

The intuitive GUI in our CORE Generatorguides you through the various options tohelp you customize the IP for your specificdesign requirements. The features include:

• Scalable IP to fit your particular applica-tion.

• Millions of possible permutations.

• Minimal learning curve.

New FIR Filter Generator

Xilinx recently announced the FIR FilterGenerator, a new tool for creating fully opti-mized and parameterized algorithms for

best possible design expertise. In addition,Xilinx DSP FAEs have extensive design expe-rience which gives them particular insightand knowledge to the challenges and intrica-cies of high performance DSP applications.

Third-Party Programs

To help you further reduce your develop-ment time, Xilinx has partnered with variousDSP development companies to provide awide range of services, from algorithm devel-opment to full turnkey operation, givingyou:

• A large and growing selection of system IPfrom our AllianceCORE partners.

• Access to the leading DSP experts in vari-ous application areas.

• Design services and expertise from theXilinx XPERTS partners.

• A wide range of in-house and third-partydesign expertise and application experi-ence.

In addition, numerous third-party vendors

such as GV & Associates, Nallatech, and LyrSignal Processing also offer prototypinghardware.

Conclusion

With the Xilinx DSP solution, you get fasterDSP designs that are customized for yourexact needs. Plus, there are no NRE chargesor limitations to your creativity. There simplyis no better way to create DSP designs.

For more information seewww.xilinx.com/dsp

FPGA-based complex sin-gle-rate, half-band, Hilberttransform, and interpolatedfilter designs. Design tech-niques such as distributedarithmetic are employed tooptimize filter structures forhigh-end DSP applicationssuch as wireless and xDSLmodems, medical imaging,and radar signal processing.The operational perform-ance of the FIR filters, in theVirtex family, exceeds 160billion multiply accumulates(MACs) per second.

The FIR Filter Generator allows you tochoose from millions of parameter combina-tions to match your unique DSP designrequirements, from fast, fully parallel systemsto cost-effective designs optimized for lowersampling rates, as shown in Figure 2. Theavailable parameters include:

• From 2 to 1024 taps.

• From 1 to 32 bit inputdata and coefficient pre-cision.

• Signed or unsigned inputdata.

• Fully serial, parallel, or acombination of serial/par-allel filter implementa-tions with the ability formulti-clocking of outputdata.

• Time multiplexing ofdata for multiple channelstructures.

Smart-IP Technology

By employing the Xilinx Smart-IPTechnology, the CORE Generator main-tains constant performance over the entirerange of FPGA densities; Smart IP gives youpredictable timing and optimal an imple-mentation for area and speed. This pre-dictability, unique to Xilinx, is essential forincorporating entire systems on an FPGA.

In-House Expertise

We’ve gathered together a highly knowledge-able team of DSP experts to create the bestpossible DSP tools and to provide you the

Core Solutions Xilinx DSP

System Design Analysis & Tradeoffs FPGA Design

System Design

System Design

Analysis & Tradeoffs

Cores address the FPGA design phase

Only Xilinx addresses this with The Mathworks!

Traditional design methodology

Using Cores

Using The Xilinx System Generator

Development Time

Shorter Design Cycle

Figure 1 - IP and System Generator provide shorter design cycles.

Xilinx IP Advantage

Worlds fastestprogrammableDSP device

Area/Cost

Lower costthan DSPprocessors

PE

RF

OR

MA

NC

E

Figure 2 - Xilinx FIR Filter Generator only filter algorithmenabling area/performance tradeoffs.

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IRL Makes Console SwitchingFaster and More Reliable.by Robert RoweProduct Manager, Apex [email protected]

One of the most pressing concerns facingInformation Systems Managers today ismanaging the volume and diversity ofservers under their authority. As corpora-tions increase the number of servers theydeploy, the infrastructure needed to supportthis growth requires more efficient manage-ment of physical space, server information,and staff time.

Administrators have recognized the impor-tance of reducing the amount of space occu-pied by computing and peripheral devices,and as a result, are implementing console

switches to manage and operate multipleservers from a single console. This providesmore space for servers, routers, hubs, andprinters by reducing the quantity of key-boards, monitors, and mice.

Apex, the market leader in console switches,chose Xilinx to provide the FPGAs to createtheir next generation switch. By using XilinxFPGAs and the Xilinx InternetReconfigurable Logic (IRL) technologies,Apex could develop a console switch thatcan be upgraded with new services or func-tionality, in the field, without having to sup-ply customers with new boards or EPROMchips. Not only does this provide conven-ience for their installed base of customers, it

also provides flexibility for developing andrapidly deploying new services and forremotely reconfiguring data in the consoleswitch.

Faster Time-to-Market

By populating the console switch withXilinx FPGAs, Apex engineers developed80% of the base solution to get the systemup and running. Then, by the time theswitches were deployed to customers, theremaining 20% of the code was completedand transmitted to the systems in the field.This gave Apex a lead in deploying the prod-uct to the field before the competition-a realtime-to-market advantage and a key benefitfor their customers.

Success Story Xilinx IRL

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Flexibility and High Throughput

In most customer environments, the consoleswitch is located in the same facility as theservers, but with the flexibility offered byXilinx FPGAs, the console can be locatedanywhere in the world. With the ApexEmerge2000, for remote access server con-trol, you can manage the graphical consolesof your server population from any location.

The basic architecture is based on the PCIbus (Figure 1). By using two Xilinx FPGAsin each Emerge2000, one for PCI commu-nications that is loaded at power-up andremains loaded, and the other FPGA loadeddynamically at run time, Apex consoleswitches never have to break the PCIcommunication. TheXilinx PCI core pro-vides up to 33 MHzoperation, is easy touse, and is easy tomigrate to other PCIcores with higher bus widthsif the need arises.

Xilinx also provides an easy migration pathfrom low to high density devices allowingApex to include more robust features intheir console switch products as theirrequirements evolve.

Rapid Prototype Development

By employing Xilinx FPGA technology, theApex engineers could continue developing

Conclusion

Xilinx FPGAs, along with the Xilinx IRLtechnologies, allows companies like Apex tobuild flexible, next-generation equipmentthat can be upgraded over the Internet. Thetime to market advantages are obvious andthe unique design possibilities are limitedonly by your imagination.

the design right up to the time of boarddelivery. Once the boards became available,the engineers could load the FPGA configu-ration at the work bench and verify thedesign. If they had used custom ASICs, it

would have required much more time tocomplete the design. In addition,

due to the ability to remotelyupgrade the design over theInternet, the engineers wereable to ship the product

early, with the assurance thatany new features could easily be

added in the field.

Technical Support from Xilinx

Support from a supplier is a critical pathitem, often overlooked when designersview supplier technology. Obtaining themost up-to-date information, in a preciseformat, can become a critical factor whenmoving at the rapid pace our marketdemands. The Xilinx support organizationis fast and responsive, and delivered the lat-est information to Apex engineering, blur-ring the lines of distinction between sup-plier and customer.

Success Story Xilinx IRL

...due to the ability to remotely upgrade the design overthe Internet, the engineers were able to ship the

product early, with the assurance that any new featurescould easily be added in the field.

About Apex

Apex designs, manufactures and

markets stand-alone electronic

switching systems and integrated

server cabinet solutions for the

client/server computing environ-

ment. Apex supplies stand-alone

switching systems to some of the

largest PC manufacturers in the

industry for integration into their

product offerings, providing

switching systems to OEMs

(Compaq, Dell, IBM, and Hewlett-

Packard) representing 43 percent of

all PC servers and 66 percent of all

“super” servers shipped world-

wide.Go to http://www.apex.com

for more information.Figure 1 - The Emerge2000 board

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by Bhaskar Bose, Ph.D. and M. Esen TunaPresident, Vice President - R&D, Derivation Systems, [email protected], [email protected]

LavaCORETM is a 32-bit configurableJavaTM processor core targeted to the XilinxVirtex FPGA architecture. The processorexecutes Java bytecode directly in hardwareeliminating the need for software-basedinterpreters or code translators. LavaCOREis a clean-room implementation of the JavaVirtual Machine and is provided as a syn-thesizable “soft-core” with a suite of toolsfor parameterized core generation, hard-ware/software co-design, co-verification,and custom Java application development.

LavaCORE is a revolutionary product thatprovides unparalleled flexibility for a widerange of prototyping and embedded appli-cations. Direct Java bytecode executionkeeps the runtime to a minimum makingthe processor ideal for embedded applica-tions that require small memory foot-printsand flexible reconfigurable architectures.Both the application and the operating sys-tem code can be developed in Java andcompiled to native code by standard Javacompilers.

LavaCORE is designed to bring embed-ded Java technology to the reconfigurablemarketplace. The customizable core anddynamic reconfiguration take full advan-tage of the features of programmablehardware.

LavaCORE Features

The processor core features a 32-bit archi-tecture with 32-bit address and data paths.Our reference design is implemented in aVirtex XCV300 BG352-4 FPGA. Figure 1shows a block diagram of the architecture.

A 16x32-bit dual-ported RAM implementsthe register-file. The instruction register iscomposed of three 8-bit registers denotingthe instruction, byte one, and byte two ofthe instruction stream. A 32-bit ALU com-putes arithmetic and logical operations.Additional signals include clock, reset, signalinterrupt, memory interface, and a set ofobservability pins for the state and flags.

Some of the features are highlighted below:

• 32-bit direct execution Java processor.

• Executes Java Virtual Machine bytecode inhardware.

• Stand-alone (system on a chip) or coreconfiguration.

• Built-in hardware encryption module.

• Fully synthesizable FPGA core.

• Parameterized Core Generator automati-cally synthesizes VHDL, Verilog, or EDIFgate-level netlists.

• Software support includes ParameterizedCore Generator, LavaOS RuntimeEnvironment, Co-Simulation/VerificationTools, and Hardware Debugger.

New Products Cores

LavaCORE - A ConfigurableJava Processor Create Java-enabled appliances, mobile devices,secure Internet devices, and embedded networkcomputers that can be dynamically configured forapplication-specific computing.

Figure 1 - LavaCORE architecture.

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New Products Cores

Parameterized Core Generator

The LavaCORE Parameterized CoreGenerator operates via an intuitive graphicalinterface and includes user selectable param-eters for a wide range of configurableoptions. Every implementation ofLavaCORE can be application specific, lead-ing to optimal solutions in terms of power,speed, and area.

Typically, specialized embedded applicationsuse only a subset of the full JVM instructionset. By analyzing the application, you candetermine which Java bytecode instructionscan be omitted or moved from hardware tosoftware, improving various cost criteria.

Additional options allow you to includefunctional components of the synthesizedarchitecture such as the built-in encryptionengine, programmable timers, and interruptcontrollers. For larger systems, floating pointand external memory interfaces are defined(Figure 2).

Once parameterized options are selected, theLavaCore Generator automatically synthe-sizes a gate-level implementation in eitherVHDL, Verilog, or EDIF netlist formats.Along with this softcore, an HDL testbenchand a customized runtime called LavaOSTM

are generated.

The synthesized core can then be directlyinput to Xilinx Foundation Series or AllianceSeries software for place and route. TheHDL testbench is used both to test the hard-core and softcore. Figure 1 depicts thedataflow architecture of a LavaCore instance.

Linker/Application Builder

Standard Java-class files, generated fromthird party commercial Java developmentenvironments, are statically resolved to build

executables. In addition, the linker builds theboot tables, class initialization codes, andassigns the interrupt and trap handlers.

The executable image incorporates the run-time environment. It is designed for embed-ded applications and is small enough to beimplemented in the internal block RAM. Ina standalone configuration, the LavaCOREsystem architecture can incorporate theentire runtime environment and a Java appli-cation within the Virtex block RAM.

Application Debugging Tools

The LavaCore application debugging tool setconsists of a core simulator and a hardwareinterface (Figure 3). The simulator has abuilt-in debugger that features single step-ping, memory and register file monitors, andconditional break points. The simulator andthe debugger share a graphical user interfaceto display and debug the LavaCore executionboth at instruction and micro steps.

The LavaCore simulation environment con-sists of three separate components that vali-date all three aspects of the LavaCore:

• The instruction tester.

• The application simulator.

• The hardware testbench for the synthesizedcore.

The hardware interface provides an imple-mentation debugging bridge for the synthe-sized hardware. The same debugging envi-ronment and user interface are used for thetesting of the target hardware.

Conclusion

The LavaCORE Configurable Java Processorcore enables the deployment of Java technol-ogy for a new generation of embeddedreconfigurable systems. Native execution ofJava bytecode provides reliable hardware exe-cution, denser code, and minimum runtimeenvironment. The LavaCORE parameter-ized core generator allows you to configurethe capabilities of the processor core and syn-thesize an optimal LavaCORE for yourapplication.

LavaCORE provides a fast design solutionfor embedded Java processors targeted toprogrammable hardware. With our config-urable Java processor core and co-design/ver-ification environment this unique IP productwill reduce design time leading to faster timeto market.

For more information about DerivationSystems, or the LavaCORE products, seewww.derivation.com

LavaCORE and LavaOS are trademarks ofDerivation Systems, Inc., JAVA is a registeredtrademark of Sun Microsystems, Inc.

Floating PointUnit

ExternalMemory

GarbageCollector

LavaRock Processor

ALU

LocalMemory

ProgrammableTimers

RegisterFile

InterruptController

EncryptionUnit

Figure 2 - LavaCORE system architecture.

Figure 3 - LavaCORE design environment.

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by Alan MaSenior Corporate Applications Engineer, Synopsys, [email protected]

Prior to the recent advancements in FPGAtechnology, you had to rely on externalRAM or ROM. Now, with the introduc-tion of million-gate FPGAs such as theXilinx Virtex devices, you have access toabundant on-chip memory resources.FPGA Compiler II/FPGA Express(FCII/FE) takes advantage of Virtexresources such as Look-Up Tables (LUTs)MUXF5s, MUXF6s, and on-chip blockSelectRAM to provide the highest qualityof results for ROM functions.

Coding Styles

Version 3.4 of FCII/FE recognizes a ROMdescription using CASE statements in both

Verilog and VHDL, and by using constantarrays in VHDL.

Using CASE Statements

FCII/FE infers ROM when the inputs tothe CASE statement are constant and allthe states are specified. Figure 1 shows anexample of an 8x4 ROM in Verilog. Figure2 illustrates its VHDL equivalent.

Using Constant Arrays

You also have the option of using constantarrays in VHDL. Figure 3 describes thecoding style for the same 8x4 ROM whereCONV_INTEGER is a built-in function thatconverts std_logic_vector to integer.

General Implementations

FCII/FE generally implements ROM usingLUTs, MUXF5s, and MUXF6s when tar-geting Xilinx Virtex devices. The actualresources used are closely related to thewidth of the address port. If the address hasless than or equal to four bits, then theROM will be implemented using LUTs. Ifthe address has five bits, then MUXF5s,(which provide multiplexer functions inone half of a Virtex Configurable LogicBlock), will be used in addition to theLUTs. If the address has between six tonine bits, the ROM will be implementedusing LUTs, MUXF5s, and MUXF6swhich provide multiplexer functions in a

Applications Software

InferringRead OnlyMemory inFPGACompiler IIand FPGAExpress

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full Virtex CLB. When the address has ten or more bits, FCII/FEimplements ROM using on-chip block SelectRAM resources if certainconditions are met.

Using Block SelectRAM

The Virtex series provides dedicated blocks of on-chip, dual port syn-chronous RAM, with 4096 memory cells (bits). These resources canalso be used for ROM if certain conditions are met. Our research indi-cates that when the address of the ROM has ten bits and the data hasmore than or equal to three bits, quality of results can be improved bymapping the ROM to block SelectRAM if the output of the ROM isregistered. However, if the data has less than or equal to two bits (whenthe address has ten bits), using LUTs, MUXF5s, and MUXF6s, asdescribed in the previous section, yields better results. For ROM whoseaddress has more than or equal to eleven bits, block SelectRAM willalways be used if the output is registered. Table 1 summarizes the con-ditions for ROM inference.

To reserve block SelectRAM for user-defined functions, you can usethe scripting command “set_chip_instantiated_blockram”. For exam-ple, the following reserves 4096 bits of block SelectRAM forinferred ROM:

set_chip_instantiated_blockram 4096

While set_chip_instantiated_blockram applies to the current project,you can use the variable proj_user_instantiated_blockram to reserveblock SelectRAM globally for all the subsequent projects. For exam-ple, the following reserves 4096 bits of block SelectRAM for allfuture projects:

proj_user_instantiated_blockram 4096

Conclusion

Inferring ROM is easy with FPGA Compiler II and FPGA Express,which take full advantage of the abundant on-chip memory resourcesof the Xilinx Virtex devices.

Visit the Synopsys FPGA website at www.synopsys.com/fpga for otherinformation on the latest FPGA synthesis technologies.

Applications Software

library ieee; use ieee.std_logic_1164.all;

entity rom_8x4 is port (address: in std_logic_vector(2 downto 0);

output: out std_logic_vector(3 downto 0));

end rom_8x4;

architecture rtl of rom_8x4 is begin

process (address)begin

case address iswhen "000" => output <= "0001";when "001" => output <= "0010";when "010" => output <= "0100";when "011" => output <= "1000";when "100" => output <= "1000";when "101" => output <= "0100";when "110" => output <= "0010";when "111" => output <= "0001";when others => output <= "0000";

end case;end process;

end rtl;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity rom_8x4 is port (address: in std_logic_vector(2 downto 0);

output: out std_logic_vector(3 downto 0));

end rom_8x4;

architecture rtl of rom_8x4 is

constant num_word : integer := 8; constant num_bit : integer := 4; signal int_add : integer range 0 to 7;

type ROMARRAY is array (0 to (num_word-1)) ofstd_logic_vector((num_bit-1) downto 0);

constant ROM: ROMARRAY := ( "0001", "0010", "01 00",

"1000","1000","0100","0010","0001");

beginint_add <= CONV_INTEGER(address);output <= ROM (int_add);

end rtl;

module rom_8x4 (address,

rom_out);

input [2:0] address; output [3:0] rom_out;

reg [3:0] rom_out;

always @(address)case (address)

3’b000 : rom_out <= 4’b0001;3’b001 : rom_out <= 4’b0010;3’b010 : rom_out <= 4’b0100;3’b011 : rom_out <= 4’b1000;3’b100 : rom_out <= 4’b1000;3’b101 : rom_out <= 4’b0100;3’b110 : rom_out <= 4’b0010;3’b111 : rom_out <= 4’b0001;

endcase endmodule

Figure 1 - Using CASE statements for ROM in Verilog.

Figure 2 - Using CASE statements for ROM in VHDL.

Figure 3 - Using constant arrays for ROM in VHDL.

LUT MUXF5 MUXF6 SelectRAM

ADD <= 4 Bits Any Data Width ◆

ADD = 5 Bits Any Data Width ◆ ◆

6 Bits <= ADD <= 9 Bits Any Data Width ◆ ◆ ◆

ADD = 10 Bits 1 Bit <= DATA <= 2 Bits ◆ ◆ ◆

ADD = 10 Bits* DATA >= 3 Bits* ◆

ADD >= 11 Bits* Any Data Width* ◆

Table 1 - LUTs, MUXF5s, MUXF6s, and block SelectRAM utilization.

* Note that LUTs, MUXF5s, and MUXF6s will be used if the output of the ROM is not registered.

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by Alan MaSenior Corporate Applications Engineer, Synopsys, [email protected]

Advancements in the capacity and speed ofFPGAs have made this technology increas-ingly attractive for million-gate designs. Asthe complexity of the designs grows so doesthe need for advanced synthesis and place-and-route tools. One of the highly soughtfeatures is the ability to recompile only themodified portion of a design after modifica-tions have been made. Such a feature is need-ed not only to reduce compilation time, butalso to preserve the timing behavior of cer-tain sections of a design when other sectionsof the design are changed.

To address these requirements, FPGACompiler II and FPGA Express (FCII/FE)version 3.4 introduce Block-LevelIncremental Synthesis (BLIS) to allow you tomodify a subset of your design and then re-synthesize just the modified subset. A designcan be divided into “blocks,” the smallestsubset to which BLIS can be applied.FCII/FE generates an optimized netlist foreach block, which does not change unless thedesign associated with that block has beenmodified. The netlist of each block is thenpresented individually to the place-and-routetool which is capable of recompiling only the

modified netlists. Not only does this increasethe likelihood of preserving post place-and-route timing behavior for the unmodifiedblocks, overall compilation time for bothsynthesis and place-and-route is significantlyreduced.

Identifying Blocks

A block is the smallest subset to which BLIScan be applied. It can be a Verilog module, aVHDL entity, an EDIF netlist, or a combi-nation of these, as long as they form a treewithin the design hierarchy. The top-levelmodule/entity/netlist of this tree is, by defi-nition, the block root. The components of ablock include the block root and all mod-ules/entities/netlists in its tree of the designhierarchy that do not include another blockroot.

For example, the top-level design “TOP” inFigure 1 has two subde-signs A and B. A instanti-ates C and D. B instanti-ates E and F. By defini-tion the top-level designTOP is a block root. Ifyou also decide to desig-nate A and E as blockroots, then the entire

design will have three blocks:

• Block 1: TOP, B, F

• Block 2: A, C, D

• Block 3: E

Any modifications to any module/entity/netlist contained in a block cause theentire block to be re-synthesized. For exam-ple, if F is modified then every member ofBlock 1 (TOP, B, F) will be re-synthesizedeven though TOP and B have not beenchanged.

Blocks can be identified in both theGraphical User Interface (GUI) and the shellof FCII/FE. In the GUI, right-click an elab-orated implementation in the Chips windowand select Edit Constraints. Select the Modules

Applications Software

Block-Level Incremental Synthesis allows you to modify a subset of a design and thenre-synthesize just the modified subset.

Block 1

Block 2

Block 3

= Block Root

C D

A

TOP

E

B

F

Figure 1 - Example of blocks and block roots

Using Block-Level IncrementalSynthesis in FPGA Compiler II and FPGA Express

Using Block-Level IncrementalSynthesis in FPGA Compiler II and FPGA Express

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tab to display the Modules Constraint Table.You can then specify any subdesigns as blockroots in the Block Partition column. Toremove a block root designation, click theparticular cell and select Remove. Note thatthe top-level design is always identified as the

block root by definition and it cannot beremoved. Figure 2 shows the ModulesConstraint Table.

In the shell, use the commandset_module_block followed by the option“true” and the path to themodule/entity/netlist to be specified as theblock root. For example:

fc2_shell/fe_shell> set_module_block true/TOP/A

In the interactive mode, you can remove anyblock root designations by using the “false”option. For example:

fc2_shell/fe_shell> set_module_block false/TOP/A

In the batch mode, the same can be achievedsimply by removing the set_module_blockcommands associated with the block roots tobe removed in the fc2_shell or fe_shell scripts.

Please refer to the man page of set_mod-ule_block for additional usage and syntaxinformation. To access the man page:

fc2_shell/fe_shell> man set_module_block

Block roots can only be designated on user-created modules/entities/netlists. For exam-ple, attempting to modify the setting on aprimitive or the top-level design will result inthe following error message:

for being in the same design source file as A.The newer time stamp of B causes the entireBlock 1 to be re-synthesized. Needless to say,this is not a desired behavior.

It is obvious that BLIS is not useful in the extreme case where all modules/enti-ties/netlists are described in a single designsource file.

Since FCII/FE does not incrementally opti-mize across block boundaries it is importantnot to break combinatorial logic into differ-ent blocks. For best QoR, it is recommend-ed to observe conventional Register TransferLevel (RTL) coding style when partitioningdesigns. This involves grouping related com-binatorial logic within a module/entity andregistering all outputs of such a module/enti-ty.

Note that BLIS is most effective when mod-ifications are done within a module/entity.Changing the partition or the pins of themodules/entities of the design causes theentire design to be re-synthesized. This iswhy thorough planning in the early stage ofthe design process is vital to success.

Implementation Update

This section describes what needs to be donein the GUI and the shell to update an imple-mentation after a design has been modified.It is assumed that blocks have been definedas described previously, an optimized imple-

mentation has been created, and place-and-route netlists have also been generated. Forthose who are not familiar with the synthesisprocess of FCII/FE, please refer to the FPGACompiler II/FPGA Express Getting Startedmanual for step-by-step instructions.

In the GUI, a red question mark next to adesign source file in the Design Sources

Error: Cannot set block option on module ‘AND’

Furthermore, the concept of block and blockroot only applies when the target architecturesupports BLIS. Attempting to apply this fea-ture on an architecture which is not support-

ed by BLIS will result in the fol-lowing error message:

Error: block assignments are notsupported for the target technologyof this chip

BLIS is currently available forthe Xilinx Virtex architecture.

Design Planning

The advancement in synthesisand place-and-route technolo-gies certainly plays an importantrole in Quality of Results (QoR)but thorough design planningcan never be replaced. In order to

take full advantage of BLIS it is important tounderstand that:

• FCII/FE uses a time stamp to determine ifan implementation is out-of-date. If thetime stamp of any of the analyzed designsource files is newer than the elaboratedimplementation then the elaborated imple-mentation needs to be updated.

• A block is the smallest subset to whichBLIS can be applied and any changes inany member of a block cause the entireblock to be re-synthesized.

• A block represents “hard” boundaries whichFCII/FE does not opti-mize across.

Therefore it is recommend-ed that each module/enti-ty/netlist in a design bedescribed in its own designsource file. Doing so ensures that modifying amodule/entity/netlist will not affect the timestamp of other modules/entities/netlistswhich could potentially be members of other blocks.

In Figure 3, A and B are described in thesame design source file. Modifying A notonly causes the entire Block 2 to be re-syn-thesized, it also affects the time stamp of B

Applications Software

Figure 2 - Modules Constraint Table

Block 1

Block 2

Block 3

= Block Root

C D

A

TOP

E

B

F

Figure 3 - Example of design planning

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window indicates that the file has beenmodified. Right-clicking the modified fileand selecting Update File reanalyzes the filefor syntax errors.

Similarly, a red question mark next to anelaborated implementation in the Chips win-dow indicates that the implementation isout-of-date with respect to its design sourcefiles. Right-clicking the elaborated imple-mentation and selecting Update Chip re-elab-orates the implementation.

Once the design has been re-elaborated,right-clicking the optimized implementationand selecting Update Chip re-optimizes thedesign. If blocks are properly defined asdescribed previously, BLIS will be automati-cally enabled. In this situation only theblocks that are associated with modified filesare re-optimized. Note that there has to be atleast two blocks defined to enable BLIS.

Instead of individually updating the designsource files, the elaborated implementa-tions, and the optimized implementations,you can update the entire project in onestep by right-clicking the project icon in theDesign Sources window and selectingUpdate Project. It is important to under-stand that FCII/FE generates one netlist inEDIF format for each block defined. Thenames of the netlists are the same as themodule/entity/netlist name of the respec-tive block roots. Performing an UpdateProject ensures that only the netlists associ-ated with modified blocks are regenerated.Note that explicitly choosing Export Netlistforces all netlists to be regenerated. Thisstep is therefore only recommended whenthe design is synthesized for the first time.

If Export Timing Specifications is selected inthe Export Netlist dialog box, FCII/FE gen-erates a Synopsys Constraint File (.scf ) topass timing constraints entered in FCII/FEto the place-and-route tools. Since theXilinx place-and-route tool does not read.scf directly, the information in this filemust be transferred to a User ConstraintFile (.ucf ) for timing constraints to be con-sidered during place-and-route.

Figure 4 shows a sequence of equivalentfc2_shell/fe_shell commands to be used in

the interactive mode. Please refer to theman pages for complete usage and syntaxinformation.

Limitations

As mentioned previously, time-stamping isused to determine if an implementation isout-of-date. FCII/FE processes timestamps in whole seconds. If both analysisand elaboration finish within one second,then the analyzed design source files andthe elaborated implementation will havethe same time stamp. When the timestamp of the elaborated implementation isolder than or equal to the analyzed designsource files, the existing elaborated imple-mentation is discarded and re-elaboratedupon Update Chip or Update Project. Thenew elaborated implementation will thenhave a newer time stamp than the existingoptimized implementation. This causesthe existing optimized implementation tobe discarded and re-optimized when actu-ally none of the design source files havebeen modified. Because designs in generaltake longer than one second to be analyzedand elaborated, this limitation should notpresent any problems.

Note that BLIS is driven only by the dif-ference in time stamps, the existence of at

least two defined blocks, and any changeof block roots. Other operations, such asmodifying timing constraints, do notcause block-level incremental re-synthesisof the implementation.

Conclusion

FPGA Compiler II and FPGA Express ver-sion 3.4 introduce Block-Level IncrementalSynthesis allowing you to modify a subset ofa design and then re-synthesize just the mod-ified subset. They generate an optimizednetlist for each block and the netlist of ablock does not change unless the design asso-ciated with that block has been modified.

The place-and-route tools that supportblock-level incremental place-and-route areable to recognize and recompile only thenetlists that have been changed. Not onlydoes this increase the likelihood of preservingpost place-and-route timing behavior for theunmodified blocks, overall compilation timefor both synthesis and place-and-route canbe significantly reduced.

Please visit http://www.synopsys.com/products/fpga/ for the latest in FPGA synthesis technology.

Applications Software

create_project TOP

add_file -library WORK -format VHDL c:/designs/top/TOP.vhd add_file -library WORK -format VHDL c:/designs/top/A.vhd add_file -library WORK -format VHDL c:/designs/top/B.vhd add_file -library WORK -format VHDL c:/designs/top/C.vhd add_file -library WORK -format VHDL c:/designs/top/D.vhd add_file -library WORK -format VHDL c:/designs/top/E.vhd add_file -library WORK -format VHDL c:/designs/top/F.vhd

analyze_file

create_chip -name TOP -target VIRTEX -device V800FG680 -speed -6 -frequency 50 TOP

current_chip TOP

set_module_block true /TOP/A set_module_block true /TOP/B/E

optimize_chip -name TOP-Optimized

export_chip -dir .

# design has been modified

update_project

list_message

Figure 4 - fc2_shell/fe_shell commands

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by Tamara SnowdenCorporate PR Manager, [email protected]

The Cajun P880 Routing Switch is thenewest member of Lucent’s next-genera-tion, enterprise data networking solutionsthat provide network managers with aneasy and flexible way to optimize their net-work designs; it had anextremely aggressive devel-opment schedule.

“We originally designed theP880 with an ASIC at theheart of the switching fab-ric,” said Brian Ramelson,design manager at Lucent.“We soon realized that if westuck with an ASIC design,the product would be lateto market.” Ramelson had recently attendeda Xilinx Virtex series presentation and decid-ed to contact Xilinx personnel to find outmore.

As a result, a close working relationshipdeveloped between Ramelson and JohnDePapp, Xilinx field applications engineer,over the next several weeks. The two spentover 100 hours working together on theproject. “The design process went verysmoothly,” said Ramelson “the support pro-vided by DePapp was second-to-none.”

Virtex FPGAs - a Test Case

Ramelson’s team selected the VirtexXCV150 and XCV800 FPGAs to supply thefunctions they needed. “At the time we wereskeptical that any FPGA could implementthese functions,” said Ramelson. “We decid-ed to try Xilinx FPGAs for this project as atest case for future designs.” The Virtex seriesdevices range from 50,000 to 1,000,000 sys-

tem gates at clock speeds up to 200 Mhz andinclude many new features that address sys-tem-level design challenges. Fully supportedby the Alliance Series software, the Virtexfamily offered a complete solution forLucent, ready to meet the design challenges

for their groundbreakingproduct.

The Software Solution

Lucent’s design team choseSynopsys FPGA Express forsynthesis, VCS for a Verilogsimulator, and Xilinx AllianceSeries tools for place androute. Ramelson especiallyappreciated the ability of theAlliance Series software to per-

form multi-pass timing-driven place-and-route. “If a layout initially failed to meet tim-ing requirements, we let the system work onthe problem,” said Ramelson. “In one casewe let the software perform about twentysuccessive iterations over a weekend resultingin two or three workable layouts.”

The Alliance Series provides the flexibility toselect the best EDA design environment fora specific application. Combining theadvanced implementation technology ofXilinx with the strengths of its partners pro-vides a powerful overall design solution, thehighest clock performance and the highestdensities in the industry.

The Cajun P880 Switch

The 17-slot Cajun P880 is a major step upfrom Lucent’s P550 7-slot switch, althoughthe two share a common architecture. TheP880 can use any of the company’s existing50-series boards for Ethernet, Fast Ethernet,

or Gigabit Ethernet. This provides net man-agers an obvious migration path. By mid-2000 even more capable 80-series boardswill become available and can be deployedbeside the 50-series boards in the sameP880 chassis.

The P880’s backplane scales upward from56 Gigabits per second to 139 Gigabits persecond providing the P880 with the capabil-ity of switching or routing from 41 to 106million packets per send. Designed with nosingle point of failure, the highly reliableCajun P880 supports up to 768 10/100megabits per second Ethernet ports, up to384 fiber Fast Ethernet ports, and up to 128Gigabit Ethernet ports in a fault-tolerant,modular chassis.

The P880’s switching fabric consists of sixswitch elements, each using two XCV150devices for a total of 12 per chassis. The con-troller used a single XCV800 device. Thedesign allows for high redundancy to maxi-mize reliability. A second backup controller isoptional with the P880, while a seventhswitch element can be added for redundancy.Ramelson estimates a typical place and routefor the controller took just about two hours.

Conclusion

Ramelson notes this was a far different expe-rience from the last time he worked with anFPGA. “The element that best representsthe success of this program was how fast wewere able to complete the design. End toend the design process was completed with-in six weeks—we had a working model inabout a month.”

Because of the breadth of its capabilities, theP880 spans both the “internetwork” and“wiring-closet” market sectors. This makesthe Lucent switch a potent competitor. Butspecs mean little unless you can deliver prod-uct on time and that was where XilinxFPGAs entered the picture. “By going withXilinx we were able to ship the P880 monthsearlier than we would have with a tradition-al ASIC design,” concluded Ramelson.

More information on the Cajun P880 can be found at

http://www.lucent.com/ins/products/p880/

Success Story Virtex FPGAs

When Lucent Technologies set out to design the Cajun P880 Routing Switch, designers quicklydetermined that a traditional ASIC design would require too much time.

Lucent Technologies Gets a Time-to-market Advantage

“By going with Xilinx we were able to ship

the P880 months earlierthan we would have with a traditional ASIC design”

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by Katie DaCostaIP Product Marketing, [email protected]

To help our customers reduce design cyclesand get products to market quickly, Xilinxand ISS (Integrated Silicon Systems, Ltd.)have entered into a strategic developmentand OEM agreement to provide versions ofISS multimedia and communications coresoptimized for Xilinx FPGAs. The IPcores will be available for purchasefrom Xilinx as LogiCORE products,downloadable from the Xilinx IPCenter, and optimized for Xilinxarchitectures and design tools. Thecores in this program includeSingle-channel HDLC, 32-channelHDLC, and 32-channel ADPCM, and areavailable now.

A Strategic Alliance

The deliverables of this agreement are opti-mized and supported cores from ISS’s

extensive IP portfolio for the latest Xilinxdevices including Virtex, Virtex-E, andSpartan-II FPGAs, as well as future FPGAfamilies. Xilinx will deliver theseLogiCORE products using the Xilinx

CORE Generator tool to smoothly inte-grate the cores into the Xilinx design flow.

“This agreement broadens our long-termand successful relationship with Xilinx,”said James G. Doherty, CEO of ISS. “Thestrength of the Xilinx Virtex architecturecoupled with their commitment to partner-

ships provides a perfect environment toexpand the usage of ISS cores in wirelessand wired communications, and digitalvideo and imaging applications. With thisagreement, Xilinx can now fully utilize ourexpertise in multimedia communications to

provide the highest-performance,off-the-shelf design solutions

available in the market.”

“ISS has achieved industry-widerecognition for solving the needs of

the communications and multimediauser community,” said Mark Aaldering,senior director for the IP Solutions Divisionat Xilinx. “By partnering with ISS, Xilinx isable to address the demand for a one-stopsource of high-quality, cost-effective, opti-mized FPGA cores. This agreementexpands the successful long-term relation-ship between ISS and Xilinx, which startedwith membership in the Xilinx

New Products Cores

A strategic partnership with ISS producesadvanced communications products.

New HDLC andADPCM CoresNew HDLC andADPCM Cores

28

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New Products Cores

AllianceCORE third party IP develop-ment program and the co-developmentpartnership for Reed-Solomon ForwardError Correction cores. The agreementreinforces the Xilinx commitment to pro-viding leading-edge IP for multi-milliongate FPGA designs.”

The New Cores

The first three cores to result from theXilinx-ISS agreement are focused on accel-erating the design cycle of high-densityFPGAs in communications applications.

The HDLC (High-level Data LinkControl) protocol controller cores and theADPCM (Adaptive Differential Pulse CodeModulation) codec core are used in a num-ber of telecom applications ranging frominternet routers and switches to VoIP (Voiceover Internet Protocol) gateways.

“The Xilinx HDLC and ADPCMLogiCORE products address the explodingdemand from telecom and network devel-opers for complex Virtex-based IP for dataand voice processing,” said Babak Hedayati,Director of Marketing and BusinessDevelopment at Xilinx IP SolutionsDivision. “The HDLC protocol is proven asone of the most popular methods of trans-mitting data over WAN systems. The avail-ability of these cores on the Xilinx IP Centerprovides a one stop source to integrate tele-com IP solutions into Xilinx FPGAs.”

Conclusion

The strategic partnership between Xilinxand ISS is already producing optimizedcores for the communications market, and many more are on the way. Xilinx con-tinues to provide the most advanced FPGAand IP technologies to help you create thenext generation of high performance equip-ment and get your products to market assoon as possible.

HDLC Cores

The HDLC cores conform to the ITUQ.921 and X.25 recommendations for fullduplex, point-to-point and multi-pointoperation. The cores function at data ratesover 40 Mbps and include a direct connec-tion to pulse code modulation (PCM) net-works. The HDLC cores are ideal for pub-lic and private packet switched data net-works such as Frame Relay switches, cablemodems, Broadband ISDN, T1/E1,T3/E3, Packet-based DSL AccessMultiplexers (DSLAMs), Remote/multi-service access concentrators, and Sonet net-works.

ADPCM Cores

The 32 Channel ADPCM speech codecperforms the ITU G.726 conversion of 64kbit/s A-law or µ-law PCM channels to andfrom 40-, 32-, 24- or 16-Kbit channelsusing the Adaptive Differential Pulse CodeModulation transcoding technique. Thecore supports up to 32 duplexencoding/decoding channels or up to 64encoding and/or decoding channels, andcan operate in burst or continuous modes.It is on-line configurable for A-law or µ-lawPCM encoding as well as various ADPCMcompression rates including G.721 orG.723 mode operation. The ADPCMcodec will be used in applications such asCO DSLAMs, satellite communications,digital audio storage, H.323 VoIP gateways,access servers, and computer telephony andcellular networks where high quality voicecompression is important.

Availability

The HDLC and ADPCM cores are avail-able now. Suggested resale pricing is $7,200for the 32 Channel HDLC controller core,$3,900 for the Single Channel HDLC con-troller core, and $14,400 for the 32 ChannelADPCM codec core. Licensing informationand instructions for downloading the cores,and information on all Xilinx LogiCOREproducts can be found at the Xilinx IP Center at: www.xilinx.com/ipcenter.Information on other Xilinx LogiCOREand third-party AllianceCORE products isalso available from the IP Center.

About ISS

Integrated Silicon Systems Ltd. (ISS) is

the leading supplier of application-spe-

cific virtual components (ASVCs) for

multimedia and communications

FPGA, ASIC, and System-on-a-Chip

(SoC) integrated circuits. ISS delivers

video/image compression, audio com-

pression, and channel coding solutions

for consumer and communications

applications. Using proprietary tech-

niques for direct-mapped implementa-

tions of digital signal processing func-

tions and algorithms in hardware, ISS

delivers solutions that realize 10X to

1000X improvements in performance

compared to conventional implementa-

tions using software-programmable

DSP microprocessors. ISS is a private-

ly held company with European head-

quarters in Belfast, Northern Ireland,

UK and worldwide sales and marketing

operations in San Jose, California.

More information about ISS and its

products may be obtained at

http://www.iss-dsp.com

”The strength of the Xilinx Virtexarchitecture, coupled with their

commitment to partnerships,provides a perfect environmentto expand the usage of ISS coresin wireless and wired communi-cations, and digital video and

imaging applications.“

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by Kevin RowleyDesign Engineer, Mentor Graphics - IP [email protected]

There is an ever increasing demand fordigital IP cores that have been proven inFPGAs as well as ASIC test silicon. This isdue to the obvious prototyping advantagesand increasing market share of FPGAs. In this article I explain the strategy we used and the results we obtained whenimplementing the Mentor GraphicsM8051EwarpTM core, which was originallycreated for ASIC development, in XilinxVirtexTM technology.

Test Strategy

The usual method we use to prove thefunctionality of the M8051Ewarp core in

ASIC gates is to envelope the synthesizedcore in a wrapper which has instantiated allthe necessary components for simulation ofthe core. These components typically areprogram memory, data memory, and extraperipherals. However, after FPGA place androute the core will have I/O pads on itsinterface.

The delays inherent in these pads precludethe usual ASIC test method and a new syn-thesizable wrapper is required which, afterplace and route, will have the M8051Ewarpcore, memories, and required peripherals ina single netlist which can then be simulated.The synthesizable wrapper we used is illus-trated in Figure 1.

The most important point about Figure 1is that all memories are on-chip, whichmeans there are no I/O pads between theM8051Ewarp core and its memory mod-ules, and thus delays on inputs and outputsto and from memory are avoided. The testcode for the core is contained in theProgram ROM. Also shown are the datamemory RAM block and the internal datamemory (IRAM). The peripherals are thewait-state generator necessary for the testsuite and the External Special FunctionRegisters (ESFRS) also needed by the testsuite.

Data captured from the wrapper is writtento a simulation-listing file for comparison

New Products Cores

Moving the M8051EwarpASIC Core to a Virtex FPGA

Mentor Graphics implements their M8051EwarpTM core in a Virtex FPGA.

Moving the M8051EwarpASIC Core to a Virtex FPGA

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to reference listings. The test bench is aself-checking type which will setup and ini-tialize the M8051Ewarp core and thencheck the program execution (using thetest program stored in ROM).

Memory Requirements

Successful simulation of the system testsuite required the following memory :

• 4k bytes of synchronous ROM.

• 1k bytes of synchronous single-portRAM.

• 256 bytes of dual-port synchronousRAM.

The CORE Generator tool from the Xilinx2.1i Alliance Series software suite was usedto design and generate the memory mod-ules.

Specifying Memory Contents

The RAM cores had all their contents ini-tialized to zero by the CORE Generator,however the ROM module had to have testopcodes stored in it for simuation. Thereare two ways of specifying ROM contentswith the CORE Generator:

The CORE Generator then generated anEDIF netlist with this .COE file for theROM; it also generated EDIF netlists forthe RAM modules. The EDIF netlistswould be dragged-in later at the place androute stage for the wrapper.

Synthesis Strategy

We used Mentor Graphics LeonardoTM forsynthesis. The target operating speed of theM8051Ewarp core in the Virtex FPGA was30 Mhz. Therefore, the synthesis con-straints were setup accordingly. The part wetargeted was the XCV200BG352. To syn-thesize the wrapper we first synthesized theM8051Ewarp core separately and then readit in, during the synthesis of the wrapper, asa separate file.

Wrapper Synthesis

For synthesis, all the memory modules aretreated as “black boxes.” In addition toproducing an EDIF file of the synthesizedwrapper for place and route, synthesis alsoproduced an .NCF file which Xilinx placeand route uses to determine the timingconstraints of the circuit. The timinganalysis by Leonardo produced the follow-ing results:

Clock Frequency Report

Clock : Frequency--------------------------------------------------------------

SCLK : 33.8 MHzCCLK : 33.4 MHzPCLK : 33.4 MHz

Critical Path Report

There are no paths that violate user specifiedoptions or constraintsAnd the expected area utilization report:

******************************************Device Utilization for v200bg352******************************************Resource Used Avail Utilization--------------------------------------------------------------IOs 97 260 37.31%Function Generators 3653 4704 77.66%CLB Slices 1827 2352 77.68%Dffs or Latches 653 4704 13.88%

--------------------------------------------------------------

• .MIF file - Requires a line for each ROMlocation but also each byte has to be inbinary format.

• .COE file - Allows the ROM locations tobe specified in hex format.

Because the .COE format is closer to Intelhex format we decided to use a .COE fileto specify the ROM. First however it wasnecessary to write a special program whichwould take the Intel hex format file for thetest opcodes and convert it into a .COE filefor the CORE Generator.

The final COE file looked like the follow-ing (abridged) :

Component_Name=crom;

Data_Width=8;

Depth=4096;

Radix=16;

Default_Data=0;

Memory_Initialization_Vector =

01,

80,

00,

c2,

a8,

...

New Products Cores

Figure 1 - Test setup for the core.

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This shows that the wrapper fitted into theXCV200 device and, according toLeonardo, was expected to run correctly at30 Mhz.

Place and Route of the Wrapper

Because several runs were required to passstatic timing during synthesis and placeand route, it was necessary to automate theplace and route stage using the followingscript :

ngdbuild -p v200bg352-6 ewarp_f.edf

ewarp_f.ngd

map ewarp_f

par -d 1 -ol 5 -pl 5 -rl 5 -w ewarp_f

ewarp_f_out.ncd ewarp_f.pcf

trce ewarp_f_out ewarp_f.pcf -v 3 -o

ewarp_f_out

ngdanno ewarp_f_out ewarp_f.ngm

ngd2ver ewarp_f_out -w

The file ewarp_f.edf is the EDIF file forthe wrapper after synthesis. Note “ngdan-no” produces the SDF file which must beback-annotated with the FPGA netlist forgate-level simulation. The “ngd2ver” pro-gram produces a verilog netlist of theSimPrims primitives for verilog gate-levelsimulation. The FPGA device utilizationfigures we achieved are detailed in the out-put file from the “par” program:

Device utilization summary:

Number of External GCLKIOBs 3 out of 4 75%

Number of External IOBs 94 out of 260 36%

Number of BLOCKRAMs 11 out of 14 78%

Number of SLICEs 2073 out of 2352 88%

Number of GCLKs 3 out of 4 75%

Number of TBUFs 16 out of 2464 1%

The “trce” program listed static timinginformation and constraints applied forplace and route. This produced a lot of vio-lations on paths which upon closer inspec-tion turned out to be multi-cycle pathexceptions. This was because multi-cyclepath exceptions setup for theM8051Ewarp synthesis were not included

We found that the maximum speed withthe netlist was 31.25 Mhz. Above thisspeed the setup time required for PROGAfeeding into the ROM was being violated;

PROGA was becoming valid too latebefore the next clock cycle.

Conclusion

We successfully placed and routed a com-plete M8051Ewarp core plus memory andperipherals on a Xilinx Virtex device andgot it to work at speeds up to 31.25 Mhz.The key to our success was using the on-chip memory of the Xilinx part, and usingthe Xilinx CORE Generator software todesign the memories. Synthesis was per-formed by Leonardo and the post-synthe-sis EDIF netlist of the M8051Ewarpwrapper was placed and routed by Xilinx2.1i Alliance Series software. The resultingverilog netlist and SDF file, after placeand route, ran through the test suite suc-cessfully at the required speed.

References

[1] ASIC/FPGA market share ,www.xilinx.com, June 2000

in the .NCF file generated from wrappersynthesis. Some effort was needed toexamine all violating paths from “trce”and make sure they were path exceptions.

Verification

Illustrated in Figure 2 is a waveform viewof the M8051Ewarp core cycling throughthe test code stored on ROM at 30 Mhz.Program opcode can be seen coming into M8051Ewarp core on the PROGDIinput. The program address is shown insignal PROGA. The test code was setup bythe COE file at ROM generation.

Running the complete simulation through4k bytes of test code results in 12100 vec-tors. If the core has simulated correctly, itwill finish at PROGA equal to FFF hex. Ifthere has been a problem then the simula-tion will not reach program address FFFhand it will be stuck in a loop at an earlierprogram address and will terminate after acertain time-out period.

The output delays on some of theM8051Ewarp core output ports exceededthe strobe period at 30 Mhz. Usually coreoutputs are strobed out to a listing filetwice per clock cycle, the strobe periodbeing just less that half a clock cycle.Therefore, since some output delaysexceeded the strobe period it was not possi-ble to do a straight unix “diff ” between theVirtex netlist simulation listing and the ref-erence listing for this test. However inspec-tion of the listing file from simulation andcomparison with the assember code listingfor the test showed the circuit to be func-tioning correctly.

For more information on the

M8051Ewarp core see the

Mentor Graphics website at:

www.mentor.com/inventra/

8051e_warp.html

New Products Cores

32

Figure 2 - Waveform view.

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by Anita SchreiberStaff Applications Engineer, [email protected]

Simulation is one of the keys to creatingfast compact designs, with the least timeand effort. Now you can simulate yourfunctional and post-route VHDL andVerilog CPLD designs using the XilinxWebPACK software, which includes theModelSim software from ModelTechnology, Inc. (MTI).

Using the MTI ModelSim simulator givesyou the ability to use HDL testbencheswhich allow you to behaviorally describethe stimulus for your design. Describingstimulus behaviorally allows the simulationto more accurately represent the systemconditions and to vary based on theresponse received by the device. HDL test-benches also enable concurrent stimulationof different functions within the design andcan be defined to compare the results fromthe device with expected results, eliminat-ing the need to inspect waveforms to insurethat the device is functioning properly.

MTI ModelSim Xilinx Edition (MXE)

The inclusion of ModelSim in WebPACKis through an exclusive OEM arrangementbetween MTI and Xilinx. MTI licenses toXilinx a special edition of ModelSim calledthe ModelSim Xilinx Edition (MXE).MXE Starter is a free trial version availableto Xilinx WebPACK customers that allowsyou to run up to 500 debuggable lines ofcode before performance reductions occur.Upgrades to the ModelSim PersonalEdition (PE) and the Elite Edition (EE) areavailable from MTI and both upgrades arecompatible with WebPACK.

Downloading MXE

MXE is included in the latest backPACKmodule of WebPACK as shown in Figure1. Downloading the required design entry

and CPLD fitter modules of WebPACKand the MXE backPACK module results ina tight integration between WebPACK’sProject Navigator design environment andMTI’s simulation tools. WebPACK is avail-able at: www.xilinx.com/products/soft-ware/webpowered.htm.

MXE Licensing

Licenses are required for MXE and can beobtained at the end of the installationprocess or after the product has beeninstalled. With either method, your Webbrowser will be directed to an online licenserequest form. Upon completion of thisform, the MXE license and instructions forinstalling the license will be quickly e-mailed to you.

Using MXE with the WebPACK Project Navigator

Once you have installed MXE, you canimport HDL testbenches into design proj-ects in the same manner as other sourcefiles. When an HDL testbench is selectedin Project Navigator, the ModelSimFunctional and Post-route simulationprocesses are available as shown in Figure 2.You can create simulation command files(ModelSim “.do” files) as Project Navigatorinvokes the MXE simulator, or you canspecify existing .do files.

Execution of either of the simulatorprocesses results in ModelSim simulatingthe design and displaying the specifiedwindows as shown in Figure 3.

Conclusion

With ModelSim and WebPACK you canquickly and easily create CPLD designsthat work perfectly, the first time.

A detailed application note (XAPP338)instructing you on the operation of MXEwithin WebPACK for both CoolRunner

and XC9500 CPLDs, leads you through asimple and complex design example usingMXE for both functional and post-routesimulations. XAPP338 is available on theXilinx website at:

www.xilinx.com/xapp/xapp338.pdf.

Product Focus Software

Xilinx WebPACK Software Now Includes ModelSim

A complete design environment,including simulation, for XilinxCoolRunner and XC9500 CPLDs...

Figure 1 - MXE backPACK Module.

Figure 2 - ModelSim Simulator processes.

Figure 3 - Resulting ModelSim windows.

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by Larry McKeoghCPLD Software Sr. Technical Marketing Engineer, [email protected]

Xilinx WebPACKTM, the popular Internet-enabled Project Navigator-based CPLDdesign environment just got better. The newWebPACK ISE release extends your produc-tivity and performance capabilities even fur-ther with an easier to use design interfaceand greater design control.

The free WebPACK tool modules include:

• Design Entry Module - Provides VHDL,Verilog, and ABEL HDL support as wellas schematic capture design entry which isnew to WebPACK with ISE.

• Fitter - Fitters for either the XC9500 orCoolRunner families.

• Programming - For device programmingcontrol.

In addition, the recently introducedBackPACK modules have been augmentedfor the WebPACK ISE release.

New BackPACK Capabilities

Xilinx introduced the concept of aWebPACK “BackPACK,” or productivityenhancement module in April 2000.BackPACK modules are not required forCPLD design completion, but are useful in

extending design flow functionality. Thefirst BackPACK modules introduced wereChipViewer and Model Technology’sModelSim XE Starter Edition. WebPACKISE includes updates to these two tools aswell as offering schematic design libraries foruse with schematic capture.

WebPACK ISE also introduces two newtools developed by Visual SoftwareSolutions (VSS) for inclusion in Xilinx soft-ware: StateCad (www.statecad.com) andHDL Bencher (www.testbench.com).

StateCad

StateCad automates the state machinedesign process. It automatically looks forcommon design problems such as stuck-at-state, conflicting state assignment, and inde-

Innovations Software

Free, comprehensive design environment for CPLDs available over the Web.

New WebPACKIntegrated SynthesisEnvironment (ISE)

34

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terminate conditions. Its automated erroranalysis insures that designs are logicallyconsistent which reduces the simulationrequirements and improves product reliabil-ity. StateCAD automatically produces HDLcode for synthesis and simulation that elim-inates manual translation efforts and codingerrors. It simplifies complex state machinedesign allowing you to achieve peak hard-ware performance with less effort thanbefore.

HDL Bencher

HDL Bencher is an automatic test benchgenerator allowing test benches to be creat-ed in minutes. A VHDL or Verilog design

file can be imported to HDL Bencher eithermanually or through the Project Navigatordesign environment. HDL Bencher analyzesthe design I/O and creates a default stimuluswaveform for each. The waveform may be

into four basic areas allowing as much oras little interaction with the design flowas you want.

Greater Control

In addition to the improved design environ-ment and new tool integration the CPLDtools are augmented with the following newfeatures and improvements:

• XC9500XV output banking support auto-matically assigns device outputs based onthe desired output voltage standard.

• Improved design analysis included in thefitter and timing reports.

• Operating code cleanup and efficiencyimprovements.

• The ABEL language was upgraded to ver-sion 7.3 with the following changes:

- ABEL-XST synthesis. ABEL designerscan now choose ABEL-XST synthesisfor similar synthesis results withimproved software stability

- WYSIWYG Support. New option forABEL designers who want to assign theexact design implementation and nothave the synthesis or fitting tools re-optimize the design

- True bus notation for ABEL designs

• Improved design analysis included in fitterand timing reports.

• Operating code cleanup and efficiencyimprovements.

Conclusion

WebPACK ISE builds on the success of theoriginal WebPACK with improvements tothe Project Navigator design environmentfor improved ease of use. The Xilinx CPLDdesign implementation tool update includedin WebPACK ISE provides design control,while the tight integration of new tools suchas ECS, HDL Bencher, and StateCadextend the WebPACK functionality makingWebPACK ISE the industry leader in designenvironments available over the Internet.

WebPACK ISE is a modular design toolavailable for free from the Internet athttp://www.xilinx.com/products/software/webpowered.htm.

easily modified to simulate the expecteddesign performance. Final waveforms maybe exported as a VHDL or Verilog file foruse in many popular EDA simulators. Theautomatic nature of HDL Bencher allowstest benches to be automatically updated asyour design changes, thus eliminating staletest cases. Use of HDL Bencher ensures thatyour complex hardware designs are morerobust and up-to-date than if coded manu-ally all in a fraction of the time.

Easier to Use Design Interface

The upgraded Project Navigator designenvironment, shown in Figure 1, has a newlook and feel. The basic Project Navigator

structure is maintained andincludes significant new flexi-bility enhancements, allowingyou to fully customize thedesign environment.

Other ease of use improve-ments (as shown in Figure 1)include:

1 - HDL editor integration.

2 - Synthesis flow switching.

3 - Double-click design process propertyand options access.

4 - Augmented design processes grouped

Innovations Software

Time (ns)

A[3:0]

B[3:0]

ADD_SUB

S[3:0] 1 0 2

1

1

0

1

2

0

0

1

0 200100

1

Figure 1 - Project Navigator design environment.

21

34

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Smart Cards are becoming a common part ofour every day lives, and new ways to use thistechnology are being developed at a rapidpace. Because they hold more than 100 timesthe information contained on a standardmagnetic strip card, Smart Cards can store

small denominations of cash, accumulatemedical records, be used as security cards,and can greatly ease on-line buying. Theirapplications and acceptance are increasingdaily; the American Express® Blue Card nowcomes with a free Smart Card reader thatconnects to your PC so you can interrogateyour account securely on-line, and you don’thave to enter your account details every timeyou purchase from a website.

The Smart Card Reader

One of the fastest growing uses for SmartCards is to replace the standard credit card;this has lead to a dramatic increase inportable battery powered Smart Card read-ers. These readers can be used in restau-rants for payment at your table, in taxis andbuses for payment on the move, and in on-line Web-based or main street stores.

Figure 1 shows the basic components of aSmart Card reader. These functions mayalso be integrated into cash registers, vend-ing machines, public pay phones, set-topboxes, mobile phones, utility meters, andmany other devices that require an authen-tication or secure payment system.

The functional blocks that make up thesystem are:

• Main data processing - typically a 16- or32-bit microprocessor (MCU) for com-putational functions.

• Memory - to store data (operating sys-tem, variables, data storage) and micro-processor boot code.

• Security logic - to aid data encryption.

• Card reader interface - for both the SmartCard reader (contact and contactless) andthe magnetic card reader.

• Keypad and keypad decoder - for enter-ing Personal Identification Numbers(PINs) and other data, and the associatedlogic to decode the input.

• LCD Display driver - for user feedback.

• Modem and modem interface - for inter-facing to wireless, cellular, and radiomodems (usually PCMCIA type).

How it Works

In a typical consumer transaction:

• The merchant inserts the Smart Cardinto the card reader and power is appliedto the card.

• The reader communicates with the SmartCard MCU to perform the card authen-tication cycle.

Product Focus CoolRunner

Coolrunner CPLDs can be used to implement various functions within Smart Card Readers, and are especially beneficial in handheld,lightweight, battery-powered applications.

Low PowerCoolRunnerCPLDsAn Ideal Fit for Smart Card Readers

by Karen ParnellEuropean Marketing Manager, High Volume Products, [email protected]

Low PowerCoolRunnerCPLDs

36

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• During the initial read function the SmartCard interface logic passes the data to thecard reader microprocessor via the securitylogic. (The CoolRunner device is a non-volatile EEPROM CPLD so it is secureand reliable and thus ideal for implement-ing security logic and MCU decoding.)

• The card reader instructs the user to entera PIN via a message on the LCD. The userenters their PIN via the keypad; this isauthenticated by the reader MCU. ThePIN is verified by the MCU in the cardwhich compares the PIN stored in it’sRAM with the one presented. If the com-parison is negative the CPU will refuse towork. The Smart Card keeps track of howmany wrong PINs are entered and if it isover a predetermined number, typicallythree attempts, the card blocks itself againstany future use.

• When the PIN is verified, the purchaseamount is entered by the merchant andthe Smart Card is interrogated to see if ithas enough stored value. If so, theamount entered is deducted from thestored value on the card.

• If it is not an SVC (Stored Value Card)transaction then the amount to be debited from the bank account will beverified using the modem (wireless, cellular, or radio).

Card reader to be updated in the field, thusincreasing the effective system life. By inte-grating all of the logic into a small form fac-tor, ultra-low-power CoolRunner CPLD,you can dramatically reduce the total PCBarea and number of layers required.

Conclusion

The Smart Card market is on the brink ofrealising its full world-wide potential forcashless transactions, store loyalty schemes,access control systems, medical record cards,identity cards, drivers licenses, and manyother applications. This year we will see per-sonal computers shipped with Smart Cardreaders as standard equipment which willunlock widespread world-wide acceptance ofmulti-application Smart Cards, and hand-held battery powered Smart Card readers intaxis and buses will become common place.

Xilinx high-volume CoolRunner CPLDdevices provide you with cost effective solu-tions that retain the traditional PLD time tomarket advantage but with the added benefitof ultra low power operation, very smallform factor packages, and a secure, reliable,non-volatile process technology.

• When the transaction is complete thecard is ejected and removed. The SmartCard reader is then ready for the nexttransaction.

CoolRunner Technology is Key

The Coolrunner family of ultra low power,low cost CPLDs is ideal for this application.Not only do the CoolRunner devices con-sume less power than any other CPLD butthey come in very small form factor pack-ages, such as the 56 pin, 0.5mm pitch ChipScale Package device shown in Figure 2.CoolRunner devices are available in both3.3V and 5V versions, enabling Smart Cardreaders to easily accommodate both the new3.3V Smart Cards and the older 5V types.

CoolRunner CPLDs are perfect forperforming the interfacing anddecoding functions in the SmartCard reader. The main CoolRunnertasks are the memory interfacing,input/output expansion, keypaddecoder logic, LCD interfacing,modem interfacing, and interfacingto the physical card reader itself.Because they are reprogrammable,CoolRunner devices allow the Smart

32

1000

5

200

44VQ (32)48CS (32)

64

2000

6

166

44VQ (32)*48CS (32)56CP (44)

100VQ (64)

128

4000

6

166

100VQ (80)144TQ (104)

256

8000

7.5

133

144TQ (104)208PQ (160)280CS (160)

384

XCR3032XL

Macrocells

Usable Gates

tPD (ns)

fSYS (MHz)

Packages(Max. User

I/Os)

XCR3064XL XCR3128XL XCR3256XL XCR3384XL

12000

7.5

133

280CS (216)

Product Focus CoolRunner

Figure 1 - Smart Card reader internal functions.

Table 1 - The CoolRunner family of CPLDs.

Figure 2 - CoolRunner XPLA3 64-macrocell 56-pin,

0.5mm pin pitch Chip Scale package.

6mm

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by Rebecca BurrDirector, Market Analysis, Xilinx, [email protected]

According to the Semiconductor IndustryAssociation (SIA), the programmable logicmarket is forecasted to grow by 42.9% in2000 to $4.1 billion. To place this in per-spective, in 1990, PLD shipments of $416million represented roughly 5% of all logicdevices sold. In the year 2000, PLDs willaccount for more than 14% of all logicdevices sold. This tremendous marketexpansion only further reinforces thegrowing acceptance and viability of PLDsas a system design standard. Fueling thisexplosive growth are several industrieswhose success was in part enabled by thePLD industry.

Time-to-Market Advantages

Winning companies have succeeded bygetting their products to market beforetheir competition. They meet their cus-tomers’ needs quickly and therefore estab-lish a market position that is very difficultto challenge; this position also gives thema market advantage for subsequent genera-tions of products. This so-called “time-to-market” paradigm is the watchword formany entrepreneurial companies.

Reducing their time to market remains akey focus for competitive companies. Thisfocus is growing in complexity because ofvirtual manufacturing and because systemdesigners are increasing their collaborationwith suppliers and customers–the stepsrequired for prototyping, design change,quality testing, and change execution arebeing further compressed. Programmablelogic has proven itself a very effective solu-tion for dealing with these challenges byhelping companies deliver products tomarket as fast as possible.

Time-to-Volume Advantages

Winning companies must not only devel-op new products quickly (time to market),they must also be able to manufacture theproduct, and quickly ramp production tomeet customers’ demands. This is called“time-to-volume.” Component supplythrough electronics distributors, and flexi-ble contract manufacturing, are factorsthat have enabled companies to respond tosoaring customer demand. Furthermore,PLDs have been a major factor in provid-ing an off-the-shelf platform for not onlyprototyping and early production, but alsomanufacturing through the entire productlife cycle.

As standard, off-the-shelf products, PLDscan be produced inexpensively, in high vol-umes; there is no delay for production rampup as is often the case with ASICs whichoften require a long lead time and addedrisk. We maintain that time to volume is amore critical concern than time to marketfor electronic equipment designers andmanufacturers today.

Designing with standard, off-the-shelf pro-grammable logic devices gives you the keyadvantage of flexibility, allowing you toimmediately address market demands forhigh volume production; programmablelogic has been proven effective for all appli-cations, not just low volume systems andprototyping.

Affordability Meets Desirability

Many factors affect whether a product isviewed by the marketplace as being bothdesirable and affordable. Figure 1 illustratesmarket potential, which is the junction rep-resenting those consumers who desire andcan afford a given product.

Consumers must balance the purchasingpower of their income with the cost of agiven product. Purchasing power is affectedby a broad spectrum of factors. For example,consumers’ income levels, other expenses,and inflation play a large part in determin-ing purchasing power. At the same time,they must rationalize the cost of ownershipof a product (maintenance, and so on) andany ongoing usage costs. Therefore, a prod-uct must offer a high level of utility throughfeatures and performance. The combinationof product appeal and practicality equates tomarket size.

A Tale of Two Products

Let’s illustrate how the manufacturingmodel, and consequently the drive for timeto volume, has changed over the years bycontrasting TVs with DVDs (digital videodisk players). Television entered the US mar-ket in 1936 with very little market impact,because there was little content and also lit-tle disposable income with which to buy theTV sets. By 1945 there were probably lessthan ten thousand TV sets in use, yet thatnumber was destined to grow enormously as

Column Market Analyst

With a compound annual growth rate of over 29% from 1990 to 2000 the PLD industry is one of the fastest growing segments of the IC industry.

PLDs-Your CompetitiveEdge for High VolumeProduction

PLDs-Your CompetitiveEdge for High VolumeProduction

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post-war incomes rose and broadcast net-works were able to supply the content thatdrove demand. By 1950, the number of TVsets in consumer’s hands had grown signifi-cantly to six million sets, and then to sixtymillion by 1960. In 1998, according to theConsumer Electronics ManufacturingAssociation (CEMA), penetration of colortelevisions reached 98% of U.S. households.Figure 2 presents television penetration overtime.

Contrasting the acceptance and penetrationof television to that of DVD player marketillustrates why time to volume has become afundamental market force for designers andsystem manufacturers. The DVD marketwas in an ideal market position at its incep-tion. The content (movies) was already avail-

able and the market requirement for high-quality movies to be played on big-screenTVs and home theater systems had alreadydeveloped. Moreover, the cost to purchase aDVD player and the DVD disks was lowcompared to when TVs were initially intro-duced to the market. The result was explo-sive growth in product demand. Industryprognosticators forecast that the US con-sumers will purchase ten million DVD play-ers in 2000. This will represent an increasein market penetration from 4% to 12% intwelve months.

Customer demand has driven this growth ofadvanced products. TVs were interestingand unique, yet with the lack of disposableincome there was not a significant demandfor televisions until the 1950s. For con-

sumer products, theaffordability threshold isattained when the endequipment price fallsbetween 1.1 and 1.8weeks of householdincome. Table 1 presentsUS median householdincome and correspon-ding price points for con-sumer goods acceptance.

Industrial Markets

The concepts of marketpotential apply to non-consumer, industrialequipment as well. For example, Internet-based corporations of all sizes must respond

to their customers’ needs for morebandwidth. Both internal cus-tomers for Intranet support, andexternal customers demandingfaster, more seamless Internetinterfaces, are demanding greaterperformance. The result is thatcompanies are demanding ever-increasing performance and morefeatures from their network sys-tem suppliers. Those network sup-pliers, in turn, have to respondwith faster, better, cheaper prod-ucts in much shorter time thanever before. The stakes are colos-sal, because if a network companycannot service its customers, then

some other supplier will step in and take its placeas the market leader.

Conclusion

Programmable logic will continue to outpaceother electronic component market segmentsbecause there is no faster or better way to devel-op and manufacture your products; this appliesto cellular phones, base stations, electronic testequipment, medical devices, telephone switch-ing systems, and a vast array of consumer andindustrial products. In the year 2000, PLDswill account for more than 14% of all logicdevices sold.

Programmable logic has proven itself a veryeffective solution for dealing with the chal-lenges of delivering product to market on atimely basis.

IncomeExpensesInflation

Purchasing Power

Ownership CostUsage Cost

Cost

UsesUsability

Affordability

Desirability

Market Potential

Figure 1 - Market potential is the overlap of affordability

and desirability.

250,000,000

200,000,000

150,000,000

100,000,000

50,000,000

0

1940

1945

1950

1960

1970

1980

1990

Population

Population

Television Ownership

Source: U.S. Census Department, CEMA Consumer Research

Year Total Income Product Affordability Range

1969 $33,072 $728 to $1,191

1979 $34,666 $763 to $1,248

1983 $32,941 $725 to $1,186

1989 $36,598 $805 to $1,318

1993 $33,660 $741 to $1,212

1996 $35,172 $774 to $1,266

Table 1 - Product affordability based on consumer income (in 1996 dollars).

Column Market Analyst

Figure 2 - Television penetration time to volume

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Perspective Design Reuse

The design productivity gapcreates an opportunity for

competitive advantage.

Design Reuse Strategy

for FPGAs

by Carol FieldsMethodology Manager, Design Solutions Group, [email protected]

40

With today’s technology, you are faced withmore usable gates then ever before; that’sboth a blessing and a curse. Moore’s law,stating that “the number of transistors persquare inch on an integrated circuit doublesevery two years”, has been holding true since1965, allowing a higher level of integrationto occur on one piece of silicon. However,you can only take advantage of this expo-nential growth in densities if it is matched bya similar growth in design productivity.

Why worry about this gap in productivity?History has shown that on average, for agiven product market, the first entrant takes70% of all sales over the lifetime of the prod-uct, the second takes 15%, and the later onesshare the remaining 15%, as illustrated inFigure 1. It pays to be first.

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Design Reuse Fills the Productivity Gap

The most promising way to fill this produc-tivity gap, and be the first to the market withyour new product, is to reuse existing designsor Virtual Components (VCs). Design reuseis not a new idea; designers have alwaysreused code, scripts, testbenches, and so on.What is new (from two years ago) is thegrowth in intellectual property (IP) infra-structure and the formalization of DesignReuse methodologies.

Design Reuse exists in several levels from “adhoc” reuse of a previous proj-ect to purchasing a designfrom a third-party vendor. Ifan in-house VC has thepotential of being reusedmore than twice, it is wise toput some effort into develop-ing a Design Reuse method-ology. This methodologyaddresses all aspects of theprocess including legal andbusiness practices, VC specifi-cation, designing and coding,testing strategies, design stor-age and retrieval, and designmetrics.

The amount of effort or lack of effort has adirect effect on the VC’s reusability, especial-ly if the person reusing the module is not theoriginal designer. If a third-party VC is to bepurchased, it is important to understand thetotal cost and actual usability of the VC.

The key to Design Reuse is trust. For aninternally generated VC you need to build-intrust, and when purchasing a third party VCyou need to define what makes the VC trust-worthy.

Design Reuse Strategy Today

The most popular design reuse methods arefor ASIC designs. This makes sense becausethe abundance of gates provided by Moore’sLaw is allowing such a high level of integra-tion as to place an entire System-on-a-Chip(SoC). In 1995 the Dataquest definition ofSoC included a compute engine (micro-processor, microcontroller, or digital signalprocessor), at least 100K of user gates, andsignificant on-chip memory. Five years laterwe still do not find an abundance of systemson an ASIC chip. However, what we are

operate at internal speeds far surpassing 200MHz. Many designs that once could only beimplemented in an ASIC due to speed, den-sity, or pricing are converting to a muchmore flexible and productive FPGA solution.

It is a safe bet that more systems will beimplemented in FPGAs in the future, espe-cially given Moore’s law and the ingenuity ofFPGA R&D engineers. The industry ana-lysts predict that in 2003 FPGAs will beginto replace standard cell ASICs in all but veryhigh volume applications. However, there aremany cases where the volume is not high

enough for Standard Cell technology,such as the adoption of gigabitEthernet, and areas where there is ademand for higher performance prod-ucts to meet increasing traffic flowfrom the Internet.

Because Design Reuse is about plan-ning for the future, the term Systems-on-a-Reprogrammable-Chip (SoRC)is used for SoC implemented in anFPGA. This term is used to defineboth full and partial system-leveldesigns since the challenges facingthese FPGA designers are almostidentical. Although it is rare to find

entire systems on an FPGA today, there isan increasing amount of SLI designs occur-ring due to the newer FPGA architectures(such as the Virtex family containing sys-tem-level features).

Planning for the Future

Today most major digital design companiesare in the process of defining (or redefin-ing) their Design Reuse strategy. This gen-erally includes the creation of an internalDesign Reuse Department, similar instructure to the existing EDA Departmentused to manage CAD tools. In the late1980’s many major companies had alreadyformed their EDA Department to supportthe multitude of ASIC EDA tools. At thispoint FPGA technology was just emergingwith designers using either a proprietaryEDA tool or a simple schematic capturetool; these tools hardly required a depart-ment to manage them. By the mid-1990sFPGAs were being widely used by thesesame companies for higher density gluelogic and SLI, and FPGA support wasretrofitted into the EDA Departments.

seeing is an increased use of System LevelIntegration (SLI). What we are also findingis more SLI occurring on FPGA deviceswith many of the same design issues as SoC.

The predictions are that by 2003 the bulkof the industry revenue growth will bebecause of SLI. The existing Design Reusemethodologies today are closely linked toSoC. In reality it makes more sense to tieDesign Reuse methodology to both SoCand SLI since a formalized Design Reusemethodology would benefit both SoC andSLI designers.

Systems-On-a-Reprogrammable-Chip

FPGAs have changed dramatically since theywere first introduced and used as glue logicjust 15 years ago. In the late 1980 and early1990s, FPGAs were primarily used for pro-totyping and lower volume applicationswhile custom ASICs were used for high vol-ume, cost sensitive designs. FPGAs had beentoo expensive and too slow for many appli-cations, let alone for Systems-on-a-Chip.Plus, the development tools were often diffi-cult to learn and lagged the features found inASIC development systems.

Silicon technology now allows us to buildFPGAs consisting of tens of millions of tran-sistors allowing for more features and capa-bilities in programmable technology. Withtoday’s deep sub-micron technology, it ispossible to deliver over three million usablesystem gates in a FPGA. Today’s averageASIC design operating at 30 to 50MHz canbe implemented in an FPGA using the sameRTL synthesis design methodology. By theyear 2003, a state-of-the-art FPGA willexceed 10 million system gates, and will

Perspective Design Reuse

Product Life Cycle

SalesVolume

Growth Maturity Decline

1st Entrant

2nd Entrant

3rd EntrantOthers

ProfitMargin

TotalRevenues

Figure 1 - Time-to-market product life cycle.

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Today, we have the opportunity to define areuse strategy that can not only co-exist forFPGAs and ASICs but can also work seam-lessly between the two technologies. Thedecision to include FPGAs in a DesignReuse strategy must be made up-frontbecause it affects almost all phases of theDesign Reuse process, from design specifica-tion to verification planning.

Sharing RTL Design Methods

One of the most exciting outcomes of thedramatic improvements in FPGA architec-tures, pricing, and design tools is that thistechnology advancement has made it possi-ble for ASIC and FPGA designers to share acommon RTL design methodology. A com-mon RTL design methodology is the basisfor a common design reuse methodology.

Though ASICs will continue to providehigher levels of design integration, higherspeeds, and new EDA environments,FPGAs are never far behind. The majorFPGA and EDA companies have made aconscious decision to keep their design envi-ronments the same, from the end userspoint of view, to make it easy for users tomove from one technology to the another.This was illustrated by the wide adoption ofRTL synthesis tools and verification tools inthe mid-1990s. In the case of RTL synthesis,existing ASIC methodology was kept thesame and the synthesis algorithms wherechanged to target specific FPGA devices.Today we are seeing higher-level EDA toolssuch as Floorplanners and team-baseddesign tools using the Internet.

Conclusion

In 1999, the number of ASIC design startspeaked at only 1000 designs, and despite allthe publicity over the multimillion gatesdesigns, most of these design starts wereunder 200K transistors. The average FPGAdesign start in 1999 was between 10K and50K gates, with the fastest growing size rangebetween 50K and 100K gates. Consideringthat FPGAs are more widely used than ASICsin digital designs today, it makes sense toinclude FPGAs in a design reuse strategy.

There are many benefits of sharing a commondesign reuse strategy; one of the most com-pelling is the flexibility it gives the designer tochoose the IC technology late in the designcycle. It provides the flexibility to choose thebest method to implement an SLI designwithout the overhead of retraining the designteams. In this fast pace market it is difficult topredict what features your product will needand what technology you should use.

A Design Reuse strategy is more than RTL codeand synthesis. Many companies reusing designshave found more value in the design and testspecifications than the actual RTL design. Ifyou are currently an ASIC user, the good newsis that many of the elements of a good designreuse methodology can easily incorporateFPGAs with minimal modifications.

Xilinx has joined efforts with Qualis DesignCorporation to create the first Reuse DesignGuide for FPGA users. This new FPGA ReuseField Guide will walk you through the elementsof building a design reuse strategy and is avail-able, free of charge, from the Xilinx website at:www.xiliinx.com/ipcenter.

100

10

10

20101990 20001980

SchematicCapture

LogicSynthesis

DesignReuse

ProductivityGap

Moore’sLaw

EngineeringProductivity

SystemVerification

BehavioralCompilers

Gates / designer / day

Figure 2 - The productivity gap

Perspective Design Reuse

42

Year 2000 WorldwideXilinx Event SchedulesYear 2000 North American Event Schedule

Sept 6-7 Embedded Internet Conference 2000San Jose, CA

Sept 20 SNUG 2000 BostonBoston, MA

Sept 24-28 Embedded Systems Conference 2000San Jose, CA

Sept 26-28 MAPLD 2000Laurel, MD

Oct 16-19 ICSPAT 2000Dallas, TX

Oct 16-18 NCF / InfoVision 2000Chicago, IL

Oct 18-21 Frontiers in Education 2000Kansas City, MI

Year 2000 European Event Schedule

Sept 4-15 Xilinx RoadshowThroughout Germany

Sept 5-8 EUSIPCO 2000Tampere, Finland

Oct 12-13 Nokia ExpoEspoo, Finland

Oct 23-24 IP2000 EuropeEdinburgh, Scotland

Nov 21-24 Electronica 2000Munich, Germany

Year 2000 South East Asian Event Schedule

Sept 27-28 IIC 2000Seoul, Korea

Oct 3-4 EDA&THsinchu,Taiwan

Nov 2000 Xilinx Technical SeminarSydney, Singapore, Seoul, and Shanghai

Year 2000 Japanese Event Schedule

Nov 2000 Micon System Tool Fair 2000Tokyo, Japan

Nov 2000 Xilinx Technical SeminarTokyo, Osaka, Yokohama, and Tachikawa, Japan

For more information about Xilinx Worldwide Events, please contactone of the following Xilinx team members or see our website at:http://www.xilinx.com/company/tradeshows.htm

• US Shows: Darby Mason-Merchant at: [email protected] orJennifer Makin at: [email protected]

• European Shows: Andrea Fionda at: [email protected].

• Japanese Shows: Renji Mikami at: [email protected]

• SouthEast Asian Shows: Mary Leung at: [email protected]

Year 2000 WorldwideXilinx Event Schedules

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by John HubbardCPLD Applications Engineer, [email protected]

The hand-held consumer electronics market is currently experiencingunprecedented growth, and it has become imperative for manufactur-ers to maximize battery longevity to enhance their competitive edge.With the CoolRunner CPLD family you get high performance,extremely low power, and field upgradeability, in a very small package—clearly the best solution for the next generation of low costportable equipment.

CPLD Comparison

Your battery-operated design will run much longer with CoolRunnerCPLDs. To illustrate the dramatic difference, Figure 1 compares theimpact on battery life using CPLDs from Altera®, Cypress®, Lattice®,Vantis® and Xilinx. This comparison was implemented with the fol-lowing conditions:

• Two Energizer® No. E91 AA 1.5V alkaline batteries were used as thepower source.

• The CPLD was the only device loading the batteries.

• Each CPLD was fully populated with 16 bit binary counters.

• All counters were clocked at 20 MHz.

• All outputs were unloaded.

Dynamic Power Consumption

As you can see from Figure 1, CoolRunner CPLDs extend battery lifefar beyond the competition. In fact, the competition was given apower advantage by measuring their CPLDs in low power mode.However, the competition’s CPLDs run much slower in low powermode. CoolRunner CPLDs do not need a low power mode and theyalways operate at full speed.

Static Power Consumption

Since the CoolRunner CPLD draws 1/1000th the power that thecompetition requires at standby, your power management require-ments will be dramatically reduced or eliminated. As shown in Figure2, in standby mode, the CoolRunner CPLD can extend battery life upto 390 times that of the competition.

Total Power Consumption

By modulating the dynamic operation (full power) with static opera-tion (standby mode), you will considerably extend the battery life ofyour design using CoolRunner CPLDs. Figure 3 illustrates batterylongevity in the form of duty cycle where, for example, a 75% dutycycle represents 75% dynamic and 25% static operation.

Conclusion

CoolRunner CPLDs are clearly the low power leader—for your com-pany to remain competitive in the rapidly growing portable market,your best choice is Xilinx.

See the articles on page ___ and ___ for more information. You canfind the full story on CoolRunner CPLDs at:http://support.xilinx.com/products/xpla3.htm and http://support.xil-inx.com/products/coolpld.htm

Comparisons CoolRunner CPLDs

CoolRunner CPLDs - Your Best Choice for Battery OperationRecent studies prove that the Xilinx CoolRunner” family gives you far longer battery life than any other CPLD on the market.

0

1000

2000

3000

4000

5000

6000

Hours of operation

*Low power mode for all competitors.

Xilinx XCR3128XL

Altera 3000A

Altera 7000A

Cypress CY37128

Lattice ISPLSI2128VE

Vantis M4A3

Vantis M4LV

Figure 2 - Static CPLD battery life comparison.

0

100

200

300

400

500

600

700

800

900

1000

Hours

5 25 50 75 100

Power Duty Cycle

Figure 3 - CoolRunner duty cycle effect on battery life.

0

20

40

60

80

100

120

140

160

180

200

Hours of operation

Xilinx XCR3128XL

Altera 3000A

Altera 7000A

Cypress CY37128

Lattice ISPLSI2128VE

Vantis M4A3

Vantis M4LV

*Low power mode for all competitors.

Figure 1 - Dynamic CPLD battery life comparison.

You can extend your battery life up to 200times just by using CoolRunner CPLDs.

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by Peter AlfkeApplications Engineering, [email protected]

Xilinx offers a wide variety of programmablelogic devices, using different architecturesand technologies. Here is a high-leveloverview of the different families and somesuggestions for the prospective user.

5V or 3.3V / 2.5V?

The standard logic supply for 30 years hasbeen 5 volts, but modern processes withsmaller geometries demand lower voltages,such as 3.3V, 2.5V, 1.8V, and even lower inthe future. While Xilinx strives to makeinputs tolerant to voltages higher than Vcc,we discourage you from starting any newproject with 5V devices.

Xilinx will continue offering 5V devices foryears to come, but these devices will not ben-efit from the traditional performanceenhancing and cost-reducing redesigns, andprocess enhancements. To benefit from thelatest technology, do not use 5V devices fornew designs unless there is a special reason.

CPLDs or FPGAs?

CPLDs with their PAL-derived, easy-to-understand, AND-OR structure offer a sin-gle-chip solution with fast pin-to-pin delays,

even for wide input functions. And, onceprogrammed, the design can be locked andthus made secure. Most CPLD architecturesare very similar, so it is important to evaluatethe subtle nuances.

In-system-programmability (ISP) is a mustfor today’s designs, and the ability to main-tain pin-outs during design modifications(“pin-locking”) is crucial. The limited com-plexity (<300 flip-flops) means that mostCPLDs are used for “glue logic” functions.For most CPLDs, the relatively high static(idle) power consumption prohibits their usein battery-operated equipment. XilinxCoolRunner devices are the notable excep-tion, offering the lowest static power con-sumption (<50 microamps) of any program-mable device.

FPGAs offer much higher complexity, up to70,000 flip-flops, and their idle power con-sumption is reasonably low. Because the con-figuration bitstream must be reloaded everytime power is re-applied, design security is anissue, but the advantages and opportunitiesof dynamic reconfiguration, even in the end-user system, are an important advantage.FPGAs offer more logic flexibility thanCPLDs, and more sophisticated system-levelfeatures (clock management, on-chip RAM,programmable I/O levels).

Recommendations

Use CPLDs, such as the XC9500XL family,for small designs where “instant-on”, fast andwide decoding, in-system programmability,and design security are important. UseCoolRunner CPLDs when idle-power con-sumption is important, as in battery-operat-ed equipment.

Use FPGAs for larger and more complexdesigns.

FPGA Families

Xilinx has a wide range of FPGAs to choosefrom. Here’s an overview of our completeproduct line, from the beginning.

XC2000 and XC6200

The Xilinx XC2000 family was introducedin 1985, and has outlived its useful life. TheXC6200 family embodied an innovativearchitecture that was popular in academicresearch, but found no commercial use.These families are no longer available.

XC3000, XC3100, and XC5200

These families are not recommended for newdesigns, because several newer families offerbetter functionality and performance at alower price. The XC3000L is still the FPGAfamily with the lowest static (idle) powerconsumption of <100 microamps, and itoffers an on-chip crystal-oscillator driver, notavailable in any other FPGA family. Thesefamilies stay in production, but are not rec-ommended for new designs.

XC4000 - E, EX, XL, XLA, and EV

Today, this is the industry’s most popularseries of FPGA families. The XC4000E is asuperset of the XC4000 family, with higherspeed, more routing, and edge-triggered syn-chronous write into the LUT-based RAM.The XC4000EX extends the XC4000E fam-ily to 3000 flip-flops, and adds a generousamount of routing resources. The XC4000,

Column Getting Started

How to choose the best Xilinx programmable logic technology for your application.

Choices, Choices, and Opinions

44

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Column Getting Started

XC4000E, and XC4000EX are 5V fami-lies, and as such are not generally recom-mended for new designs, because newerfamilies offer better performance and lowercost.

The 3.3V XC4000XLA is an upgrade ofthe very popular 3.3V XC4000XL family,and the 2.5V XC4000XV extends the fam-ily to 18,000 flip-flop capacity. TheXC4000XLA devices should be used wherethe more advanced features of the Virtexseries (BlockRAM, clock management, andversatile I/O) are not needed. Use Virtex-Einstead of XC4000XV for new designs.

Spartan

Spartan devices are functionally a subset ofthe XC4000E family, offering up to 2000flip-flops at a significantly lower price.They are mainly used in cost-sensitive,high-volume (consumer) applications.Spartan FPGAs achieve lower manufactur-ing cost in several ways:

• The die are smaller.

• The manufacturing flow is streamlined.

• Speed, temperature, and package optionsare more limited.

• Configuration modes are bit-serial only.

• The pricing structure favors high-volume sales.

Spartan is a 5V family, and as such is not

The 2.5V Virtex family covers the rangefrom 1,800 to more than 27,000 flip-flops.The 2.5V Virtex pins are 5V tolerant, andthe devices can implement 5V PCI.

The 1.8V Virtex-E family is an enhancedsuperset of the original Virtex family withtwo or three times the amount ofBlockRAM, as well as support for differen-tial I/O standards such as LVDS, BusLVDS,and LVPECL. At the high end, Virtex-Eoffers 73,000 flip-flops (>3 million systemgates). The enhanced 0.18 micron processprovides higher performance, but requires1.8V for the core. The I/O uses up to 3.3 V,and is not 5V tolerant.

The 1.8V Virtex-EM family includes twodevices that are electrically and architec-turally identical with Virtex-E, but havesignificantly more BlockRAM (over 1 mil-lion bits in the XCV812E). Virtex-EM isalso the first FPGA family using copperinterconnect technology for lower inter-connect resistance, higher speed, and betterresistance to metal-migration problems.

The Virtex-E and -EM families are highlyrecommended for new designs, where theyoffer not only high speed and high capaci-ty, but also valuable system-level featuressuch as clock management, a versatile I/Ostructure, and substantial amounts of dual-ported BlockRAM. Virtex-EM is ideal formemory-intensive applications.

Spartan-II

Spartan-II extends the advanced featuresof the Virtex family, with 400 to 4,700flip-flops. Spartan-II uses streamlinedmanufacturing methods and limitedspeed, temperature, and package optionsto address the cost-sensitive high-volume(consumer) market.

Conclusion

Xilinx offers many different programma-ble logic families to meet the needs of awide range of applications. Make sure youare using the right technology today, soyour designs will continue to be competi-tive tomorrow.

generally recommended for new designs.

Spartan-XL and XC4000XLA

The Spartan-XL and XC4000XLA familiesoffer similar features and performance,where Spartan-XL covers the range of 360to 2000 flip-flops, while XC4000XLAoffers 1,500 to 7,000 flip-flop capacity.These 3.3V families should be used wherethe more advanced features of the Virtexseries and Spartan-II are not needed (suchas BlockRAM, clock management, and ver-satile I/O).

Virtex, Virtex-E, and Virtex-EM

The Virtex family is the biggest designproject in Xilinx history and, judging bythe number of early design-wins, is also themost successful. The Virtex architecture isrooted in XC4000 concepts (4-input look-up tables, usable as synchronous RAM),but the design started with a clean slate:

• The interconnect structure is generous,and is optimized for short and predictabledelays.

• DLL-based fully digital clock-manage-ment eliminates on-chip and on-boardclock delays.

• The device pins are compatible withmany board-level I/O standards.

• Up to several hundred dual-portedBlockRAMs of 4Kb each.

XC4000EX

Spartan-XL

XC4000XL

XC4000XLA

Spartan-II

XC4000XV

Virtex

Virtex-E

Virtex-EM

XC4000E

Spartan

XC4000

XC3000(A)

Logic:

I/O:

XC3000(A) XC3000(L)

Vcc=5.0V

Vcc=5.0V

Vcc=3.3V

Vcc=3.3V

Vcc=2.5V

Vcc=1.5...3.3VXC4000XV: 3.3V only

Vcc=1.8V

Vcc=1.5...3.3V

Figure 1 - Xilinx FPGA Genealogy

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by Dave Vanden BoutProduct Manager, XESS Corp. [email protected]

With the advent of large FPGAs such as theXilinx Virtex series, the semiconductorintellectual property (SIP) market is poisedfor rapid expansion. Developers of openSIP serve a large segment of this market.With open SIP, the HDL source code andschematics for a functional core are madefreely available and the developers generaterevenue through service and support. Butopen SIP developers need an affordable,widely available platform for their cores torun on, just as the PC provided the plat-form for the growth of the open Linux OS.That’s why we created the XSVDevelopment Board

XSV Features

The XSV Development Board from XESSCorp., shown in Figure 1, is a general-pur-pose Virtex FPGA development platformwith extensions for multimedia I/O andnetwork connectivity. The XSV houses asingle Virtex chip in a 240-pin PQFP pack-age, ranging from the XCV50 (50 K gates)up to the XCV800 (800 K gates). The widerange of device sizes in the same low-costpackage lets XESS tailor the price of theboard to meet the price requirements of

Innovations IP Development Tools

The XSV Board, designed for the SIP developer community, provides a flexible, low-costplatform that supports a large set of interesting applications.

New Virtex XSVDevelopment Boardfor Creating Intellectual Property

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open SIP developers and users. Thereforeyou can move from smaller to largerFPGAs on the XSV Board without theneed to rearrange your pin assignments.

Video and Audio Capabilities

The XSV Board surrounds the Virtex chipwith circuitry that supports many oftoday’s important applications. A videodecoder chip digitizes NTSC, PAL, andSECAM formats with up to nine bits ofresolution. The FPGA can process the dig-itized video and store it in one of two inde-

pendent banks of 512K x 16 SRAM, or itcan send the video to a 24-bit RAMDACfor output on a VGA monitor. Video needssound to go with it, so a 20-bit stereo codeclets the FPGA input and output two chan-nels of audio.

Connectivity

To provide connectivity, the XSV Boardhas interfaces for the parallel, serial, andPS/2 keyboard/mouse ports common onPCs. There is also a USB port that connectsa wide variety of devices to the XSV Boardat up to 12 Mbps through a USB core in

which are loaded into the XSV Board withthe GXSLOAD utility from XESS. XESSalso provides utilities to run self-test diag-nostics and to set the frequency of the pro-grammable oscillator on the XSV Board.

XSV Board users can get example designsand application notes at www.xess.com andcan subscribe to an email list of users whoprovide assistance to one another.

Conclusion

Using the XSV Board, you can easily devel-op Intellectual Property for Xilinx FPGAs.This flexible, low-cost platform supports avariety of applications and helps you toquickly realize your designs. For developingIP, there is no faster or easier method.

For more information contact XESS on-line at: www.xess.com, or send e-mail to:[email protected]

the FPGA. For even higher speeds, anEthernet physical-level interface links theFPGA to a network at up to 100 Mbps.The FPGA can also communicate withexternal systems through two 50-pin I/Oheaders (38 general-purpose I/O, 12power/ground).

Configuration

A Xilinx XC95108 CPLD manages theconfiguration of the XSV Board. TheCPLD accepts bitstreams via the parallelport and loads them into the FPGA. Or it

can program the bitstream informationinto a 16 Mb Flash RAM on the XSVBoard. The Flash RAM stores multiple bit-streams that are selectable with a DIPswitch. The CPLD configures the FPGAwith the selected bitstream upon power-up.

Using XSV

The XSV Board is attached to a PC with acommonly available 25-wire parallel portcable, and is powered with a standard PC-ATX power supply. The Xilinx FoundationSeries or Alliance Series development soft-ware is used to generate Virtex bitstreams

About XESS

XESS Corporation is the

leading provider of hybrid

programmable logic/microcontroller

development boards. Targeted at the

educational market, XESS boards

allow universities and students

to build systems which combine

elements of hardware and software

and then quickly explore tradeoffs

between the two. XESS sells its

products directly to customers world-

wide. Founded in 1990, XESS is

privately held and is headquartered

in Apex, NC.

Innovations IP Development Tools

Figure 1 - XSV Development Board block diagram.

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by Derek McAulayDesign Engineer, Nallatech [email protected]

The low profile PCI/USB card,Strathnuey, is the latest carrier card to beadded to Nallatech’s award winning DIMEmodule product line. The Strathnuey pullstogether, in a compact form factor, manyof the exciting new technologies beingproduced by Xilinx for FPGAs. Support isincluded for the high speed SelectMAPinterface (which forms the basis for partialreconfiguration), Chipscope ILA (givingbuilt-in logic analyzer capability), XilinxPCI LogiCORE development (for customapplication development), and DSP IPcore verification.

Using two of the latest Spartan-II devicesthe Strathnuey provides a versatile plat-form for application development. TheSpartan-II family is used in diverse appli-cations such as wireless digital communi-cation systems, digital TV, high-speedDSL, cable modems, and medical imagingsystems.

DIME - DSP and Image processing Modules forEnhanced FPGAs

The DIME module slot, illustrated inFigure 1, gives access to the wide range of DIME modules, which you can use to customize the card to your selectedapplication.

DIME Select

To complement the Strathnuey, a newrange of low profile modules, called DIMESelect, are now available from Nallatech.These new modules enable you to cus-

tomize the Strathnuey for your applicationwhile maintaining the low cost and fea-tures of the DIME standard. DIME Selectmodules will include AD/DA conversion,Bluetooth, SDRAM, QDR ZBT, andEthernet.

DIME Professional

If you require a higher level of perform-ance and more processing power, theVirtex-based DIME Professional modulescan also be mounted onto the Strathnuey.These DIME modules are all populatedwith the Virtex family and include a widerange of functions, such as video captureand display, high speed communications,data capture/generation, and complexDSP algorithms.

Whether you are using DIME Professionalor DIME Select modules, the Strathnueyenables you to construct full customFPGA-based systems using standard offthe shelf products, guaranteeing riskreduction and a significant reduction indevelopment costs and time to market.

Configuration Software

The Strathnuey kit comes complete withcompiled designs for the PCI/USB inter-

face, along with Spartan-II drivers andapplication software, removing the needfor required expertise in PCI or USB inter-facing. The advanced system-level toolssupplied are those from the establishedDIME range, which include plug and playcapability and a standard interface whichprovides transparent migration to themore powerful and scalable DIME plat-forms such as the Ballynuey.

A key component of the tools is the integrated high speed configuration mechanism which allows the on boardSpartan-II, or other attached FPGAs, to beconfigured directly over the PCI or USBbuses, thus eliminating the need for dedi-cated download cabling and PROM pro-gramming. The configuration of theSpartan-II or Virtex-E FPGA (using theDIME slot) can be performed via theXilinx SelectMap protocol, or alternativelyvia the JTAG chain, which allows access tothe data and control registers, enablingpartial reconfiguration. This feature natu-rally provides the mechanism to developdynamically reconfigurable systems givingthis card the capability of having multiplepersonalities.

The software tools run on all Windowsplatforms (95/98/NT/2000) and is one ofthe first FPGA-based system platforms tobe supported under Linux.

New Products Development Tools

An entry level PCI card with DIME slot capability using Spartan-II FPGAs.

Strathnuey - The Xilinx Technologies IntegratorStrathnuey - The Xilinx Technologies Integrator

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New Products Development Tools

Communication Interface

Communication and control of theStrathnuey is provided by two separatemechanisms. Using the universal PCIinterface enables the card to be used insidestandard PC systems for embedded appli-cations. Alternatively, for standalone orremote applications, the card can use theUSB interface allowing it to be connecteddirectly to a laptop, for example.

IP Core Demonstration Platform

The flexibility and scalability of theStrathnuey make its range of applicationswide and varied. In particular, theStrathnuey is an ideal demonstration envi-ronment for IP core suppliers to showtheir cores’ capabilities working “live” withreal hardware and data.

As an example, IP developers can easilysend data to and from their cores via thestraightforward infrastructure interfacessuch that demonstration GUIs could beconstructed to elegantly demonstrate anyspecial features of their particular cores.Additionally, if required, a DIME modulecan provide the appropriate physical frontend or back end interface to hook up thecore with other systems for a completedemonstration system.

Integrated Silicon Systems (ISS), the lead-ing multimedia IP core provider, selectedDIME to demonstrate the capabilities ofits applications-specific virtual compo-nents (ASVCs). “Performance and flexibil-ity were key selection criteria when ISSwent looking for a suitable hardware plat-form to demonstrate its multimedia andcommunications IP cores working inXilinx Virtex technology.” commentedStephen Farson, Engineering Manager,ISS. “Nallatech’s DIME solution excelledin these areas.”

Educational Lab Experiments

The Strathnuey provides an excellent edu-cational platform for ElectronicEngineering courses, with the ability to gofar beyond education in FPGA technologyto complete system design. The simplicityof the software interface to the uncommit-ted secondary Spartan-II FPGA allows

PCI Development Platform

The Strathnuey can also be used to proveyour own PCI interface designs when youare using the Xilinx 32-bit PCILogiCORE or an in house PCI core.Support for 3.3V and 5V PCI is incorpo-rated with auto detection circuitry toselect the appropriate bit streams fromthe flash-based XCV1800 PROMs. ThesePROMs can easily be reconfigured withthe user-specific bit stream.

Conclusion

The Strathnuey gives you a complete plat-form that links the exciting new technolo-gies from Xilinx. In addition, theStrathnuey provides an ideal entry-levelDIME-based system development plat-form, which can also be used as a steppingstone to the high performance BallynueyDIME Professional products.

For more information on the Strathnueyor other DIME products, contactNallatech at www.nallatech.com.

very elaborate Computer Based Training(CBT) courses to be based around theStrathnuey. These can be developed toeducate the student in many areas and theintegration of technologies such as theXilinx Chipscope ILA allows the studentto have a full debug workbench on his PCwithout the expense of additional testequipment.

The addition of DIME Select Moduleswill ensure that lecturers can educate theirstudents in many areas including:

• FPGA technology.

• DSP theory.

• Communications theory.

• ADC/DAC principles including aliasing.

• Control theory.

• Hardware and software partitioning.

The new development system is the resultof a close collaboration between Nallatechand the reconfigurable logic group led byPatrick Lysaght at the University ofStrathclyde. The group has a 70-seat labo-ratory for teaching undergraduates digitaldesign and has been using Xilinx FPGAssince 1989.

Figure 1 - Strathnuey block diagram

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by Tamara SnowdenCorporate PR Manager, [email protected]

Technology leader Tektronix, headquar-tered in Wilsonville, Oregon, recentlyannounced its new suite of instrumentsdesigned for the most challenging leading-edge digital design applications. The inte-grated tool set is composed of new per-formance-leading instruments: the TLA714/720 portable and benchtop logic ana-lyzers, the TDS694C digital storage oscillo-scope (DSO), and complementary connec-tion devices. The instruments weredesigned to work together to provide spe-cialized features and optimized perform-ance.

An Integrated Solution

“A digital design engineer operates in anenvironment of accelerating technologicalchange under extreme time-to-market con-ditions,” said Steve Jennings, director ofmarketing of the Tektronix’ MeasurementBusiness Division. “This new integratedsolution provides superior measurementand analysis capabilities for even the mostchallenging design areas like Rambus mem-ory systems and next-generation micro-processors.”

Choosing an Upgradable FPGA Solution

“The Virtex FPGA provides the flexibilitynecessary to implement protocol detectionand reorganize the data for a delightful pres-entation to the Logic Analyzer and in sodoing, delighting the customer,” saidBrainard Brauer, a Tektronix design engineer.“An ASIC was not an option in this design.The Virtex FPGA provides field upgradeabli-

Success Story Virtex FPGAs

Tektronix Logic Analyzers 800 Mbit/sec Using Virtex FPGAs

Tektronix chose the Virtex XCV300device specifically for it’s TLA 700Rambus adapter, based upon its flexibility and overall performance.

Tektronix chose the Virtex XCV300device specifically for it’s TLA 700Rambus adapter, based upon its flexibility and overall performance.

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ty of the code, which is critical in this fastmoving, cutting-edge application.”

“Virtex FPGAs have allowed Tektronix tode-serialize the Rambus data bus,” saidBrauer. Virtex devices accept Rambus dataafter presampling logic has converted theserial channel from 26 bits on both edges at800Mbit/sec to 56 single edge signals to400Mbits/sec. “Tektronix has been suc-cessful at using the Virtex FPGA to acceptthis 400MBits/sec data directly into theVirtex device.” This was achieved by pro-viding multi-phase clocks to the device(four phases). Each clock was connected toa different global clock input, routed overits own internal globalroute with separate DLL’s(Delay Locked Loops).

“The device achieves asetup/hold specificationbetter than 1.2ns worstcase across temperatureand at any pin of thedevice,” said Brauer. “It iscritical to verify that thetools have routed eachdata input to an IOB(Input/Output Block). Inthe Tektronix implemen-tation, four input pinswere consumed for eachdata line. As a result, fourIOBs were required (one for each clockphase). The package loading must be care-fully understood and compensated for toavoid signal slew rate issues.

Choosing a Software Solution

Brauer used the Xilinx Alliance Series soft-ware to design the TMS810 Rambus inter-face adapter, which provides the crucial frontend interface between Rambus and theTLA700 logic analyzer. The Alliance Seriesis the industry’s leading open systems soft-ware that provides the flexibility to select thebest EDA design environment for a specificapplication. Combining the advancedimplementation technology of Xilinx withthe strengths of its partners provides a pow-erful overall design solution, the highestclock performance and the highest densitiesin the industry.

At the heart of all of the TLA 700 Serieslogic analyzer modules is a breakthroughcalled MagniVuTM acquisition technology,a super-high-speed sampling architecturethat dramatically changes the way logicanalyzers work and what functionality theyoffer. All incoming data is oversampled ata 2GHz rate, regardless of how the logicanalyzer is being used. The oversampleddata is then processed in real time to per-form timing acquisition, state acquisition,and triggering without missing the slight-est piece of crucial timing information onany channel.

A New Family of Logic Analyzers

The new family of logic analyzers, theTLA 714 and the TLA 720, are replacingthe original TLA 704/711. They offer anindustry-leading combination of acquisi-tion speed, channel width and memorydepth, all of which are essential for sup-porting next-generation microprocessordesigns. Now offering up to 16M, theTLA 714/720 have the deepest memoryconfiguration in the industry plus aninnovative hardware-assisted display sys-tem to simplify the management of such alarge memory.

“High register count isa key to our busdecoding implementa-tion, once deserializedinto a wide parallelpipe line architecture.The Virtex device pro-vided the lower powerconsumption weneeded with muchhigher useable registerdensities than previ-ous devices,” saidBrauer.

The new TLA 700features an easy-to-useWindows 98 user

interface and a PC platform with expand-ed openness in response to customers’strong acceptance of the original TLA700’s open platform. Tektronix built inan industry-standard computer and oper-ating system to provide the user with afamiliar interface. Because it works justlike any other PC-based software, the usercan focus on the problem, rather than thetool. Tektronix has also created theEmbedded Systems Tools PartnersProgram to deliver developmentand debug solutions for theTLA 700 Series. The solu-tions range from providingsoftware, analysis toolsand physical processorconnections, to disassem-bly software that runs onthe logic analyzer.

Success Story Virtex FPGAs

About Tektronix

Tektronix is a portfolio of measure-

ment, color printing, and video and

networking businesses dedicated to

applying technology excellence to

customer challenges. Headquartered

in Wilsonville, Oregon, Tektronix

has operations in 26 countries out-

side the United States. Founded in

1946, the company had revenues

of $2.1 billion in fiscal 1998.

For more information, visit the

website at www.tek.com.

“An ASIC was not anoption in this design. TheVirtex FPGA provides fieldupgradeablity of the code,which is critical in thisfast moving, cutting-edge

application.”

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by Tamara SnowdenCorporate PR Manager, [email protected]

McDATA Corporation, headquartered inBroomfield, CO, is the architect of thefirst enterprise-wide SAN (Storage AreaNetwork) solution. McDATA specializesin highly available, scalable and centrallymanaged enterprise SANs, providing cus-tomers with hardware and software thatallow dynamic connection between the

data center and edge servers in large enter-prise data centers. McDATA also offersdesign, implementation planning, integra-tion testing, and training services for com-panies building enterprise SANs.

Designing a Bridge Card

In the late 1990s McDATA designed a128-port 9032 Model 5 Director for IBM-a super switch for interconnecting main-frame computers and high speed peripher-

als like disk and tape arrays. IBM came toMcDATA again when the company need-ed an internal bridge card to manage theoptoelectronic, framing, and format con-version from newer, IEEE One GigabitFibre-Channel connections (or FICON)for the 9032 (Shown in Figure 1).Originally designed with the 200-MegabitESCON protocol in mind, to the Model 5would be the first of IBM’s switches tosupport FICON.

Success Story McData

When IBM needs state of the art Fibre-Channel hardware, it thinks McDATA. When McDATA needs FPGAs, it thinks Xilinx.

McData Uses Xilinx FPGAs for Fibre-channel Switch

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Each new bridge card would perform thework of up to eight ESCON channels. Upto 16 FICON Bridge cards (equivalent to128 ESCON ports or one half of theModel 5’s capacity) would be supported ina single 9032 Model 5 Director.

Retrofitting the FICON bridge card wouldallow data centers to usethe much higher speedof FICON withoutreplacing the 9032Directors. It would alsogive IBM’s customersthe ability to optimizefor either raw speed or-through multiplexing-larger arrays of storagedevices. Except for thecosts associated of thebridge card itself,upgrading the Directorwould be nearly pain-less, and conserve thecustomer’s investmentin a costly piece of high-performance hardware-the 9032 Model 5 has abackplane with full-duplex, 1-Gigabitcapacity.

Choosing FPGAs Over ASICs

Roughing out the block diagram for thenew FICON card was straightforward.The bridge card would handle multiplex-ing and format conversion; IBM wouldperform protocol conversion in the main-frame. The 1-Gigabit optical input issteered to an optoelectronic converter, andfrom there to a 32-bit, 26-Mhz parallelbus. Next is a framer, then a Fibre-Channel high-level protocol converter, fol-lowed by eight IBM-supplied ESCONengines the output of which connect to the9032 Director’s backplane.

Xilinx FPGAs form the heart of the bridgecard’s framer and protocol conversion sec-tions. Originally, an ASIC had been tar-geted for these roles. But ASIC develop-ment is risky and time consuming andproject engineer Paul Hwang needed tominimize risk and get the product to mar-ket as quickly as possible. Hwang decided

not have been possible with an ASIC—another time saver and another advantageof the FPGA approach.

McDATA used several different Xilinxproducts to implement the bridge card,among them the XC4013XL, XC4028XL,and XC4044XL FPGAs, and an XC9500CPLD. The CPLD was used to interfaceto an Intel i960 processor which down-loaded the bitmaps into the FPGAs. Asthe design evolved, McDATA started withrelatively large FPGAs, but as they alteredand optimized the design, they moved tosmaller die sizes especially with respect tothe XC4013s. McDATA is also moving toXilinx XLA technology FPGAs to “greatlyhelp with cost reduction, while continu-ing to minimize program risks,” accordingto Hwang.

The process went so well that McDATAis sticking with its original FPGA imple-mentation, especially since this allows forthe design to be further refined. As isusually the case, McDATA originallyanticipated going to an ASIC to mini-mize costs. But now, production of theFICON Bridge Card is well underwayusing Xilinx FPGAs. The cost reductionsmade using Xilinx XLA-class FPGAshave been significant, and consequently,there are no immediate plans to switch toa custom chip.

Conclusion

Looking back on the development Hwangsays, “The risk was too high with the ASICapproach. In hindsight, we made exactlythe right decision to go with XilinxFPGAs.”

to use Xilinx FPGAs and design toolsrather than develop an ASIC. The teamwould take advantage of FPGA repro-grammability to design, develop, anddebug as they went along.

Using multiple FPGAs sped up the effortfurther. McDATA found that by parti-

tioning the design intomodules, each with itsown FPGA, they couldassign each part to a dif-ferent designer or teamfor easy to manage andfaster parallel develop-ment.

Xilinx FPGAs were alsovaluable because therewere so many unknownsin the project. In fact,once the decision hadbeen made to useFPGAs, McDATA decid-ed to optimize the bridgecard architecture aroundthem, to get the most outof the programmability.This helped minimize

the impact of specification changes, bugs,and implementation changes. Use of theFPGAs drastically cut development risk,and development moved along far fasterthan the ASIC approach.

“We knew Xilinx’ product philosophy,having been a Xilinx customer for fiveyears, and were very comfortable with itand with the company’s product,” saysHwang . “It was McDATA’s positive expe-rience that made Xilinx the choice of theengineering team. They also knew thatthey didn’t need to push Xilinx technolo-gy; there was capability in reserve.”

The Design Process

The design process went smoothly usingstandard Xilinx Alliance Series( softwaretools. “We used the scripting capabilitiesto the fullest so that we could automate asmuch of the process as possible,” saysHwang. In addition, McDATA used theXilinx EPIC FPGA editor to help debugthe design by bringing out internal signalsto unused I/O pins, something that would

Success Story McData

“It was McDATA’s posi-tive experience that

made Xilinx the choiceof the engineering

team. They also knewthat they didn’t need topush Xilinx technology;

there was capability in reserve.”

“The risk was too high with theASIC approach. In hindsight, wemade exactly the right decision

to go with Xilinx FPGAs.”

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by Rob WeinsteinSenior Member of Technical Staff, Memec Design Services

There are times when it’s important to gen-erate a status flag that is set by an event inone clock domain and reset by an event in adifferent clock domain. Using a D-type flip-flop, where a “1” is clocked in from oneclock domain and its asynchronous reset ispulsed by logic in the second clock domain,is the time-honored method to achieve thisfunction. While there is nothing logicallywrong with this, it introduces other prob-lems such as combinational logic driving anasynchronous reset pin, uncertainty in tim-ing constraint boundaries, and muddyingthe global reset function.

Here, I present an alternative method forgenerating a multiple clock domain flag reg-

ister that mitigates these problems. It’s calledthe “Flancter” (named by my colleague,Mark Long), and is shown in Figure 1.

As you can see, it’s made up of two D-typeflip-flops, an inverter, and an exclusive OR(XOR) gate. Notice that the asynchronousreset inputs to the flip-flops are shownunconnected for clarity only. Normally,these would be tied to the global set/resetnet in the system.

Operation of the Flancter is simple; whenFF1 is clocked (rising edge of SET_CLKwhile SET_CE is asserted), OUT goes high.When FF2 is clocked (rising edge ofRESET_CLK while RESET_CE is asserted),OUT goes low. Note that this circuit mustbe used in an interlocked system where theflip-flops won’t be continuously clocked by

the two clock domains. Also, the outputmust be synchronized with additional flip-flops to mitigate metastability when cross-ing clock domains (more about this later).

How It Works

To explain its operation, I like to rearrangethe circuit as shown in Figure 2.

This is the same circuit as shown in Figure1, but untwisted so that the two inputs tothe XOR gate are clearly visible. You cansee that the XOR gate’s upper input islabeled Q1, while its lower input is labeledQ2. Also, Q1 and Q2 are the Q outputs ofFF1 and FF2, respectively. Now for thetrick part of this magic trick: the D inputto FF1 comes from an inverter, so whenev-er FF1 is clocked, Q1 assumes the oppositestate of Q2 and the output of the XOR

Applications Circuit Design

The “Flancter”How to set a status flag in one clock domain,clear it in another, and never have to use anasynchronous clear for anything but reset.

The “Flancter”

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gate will go high. When FF2 is clocked, Q2becomes the same as Q1, and the outputwill go low. In summary, clocking FF1causes OUT to go high and clocking FF2causes OUT to go low.

A timing diagram will help describe theFlancter’s operation. Figure 3 shows thebasic timing diagram.

The basic points of interest in the timingdiagram are:

• SET_CLK and RESET_CLK are asynchro-nous to each other.

• At point A, the rising edge of SET_CLKwhile SET_CE is high causes Q1 to gohigh because it gets the inverted value ofQ2. Also, OUT goes high because it is theXOR of Q1 and Q2.

• At point B, the rising edge ofRESET_CLK while RESET_CE is highcauses Q2 to go high because it gets the

There are a few things wrong with theFlancter from the start. One problem isthat it uses two flip-flops to create a singleflag bit. This is a minor fault when youconsider that most FPGAs have an abun-dant supply of flip-flops. A more seriousissue is how to use the output. Rememberthat the output can change synchronouslyto either clock domain. You need to resyn-chronize the output to whichever clockdomain needs to see it; often both clockdomains. It is common to use two flip-flops in series as a metastability-resistantsynchronizer.

However, the most serious drawback to theFlancter is that operating the set and resetflip-flops must be mutually exclusive intime. This means that when logic in clockdomain 1 sets the Flancter, it doesn’tattempt to set the Flancter again until itsees that it has been reset. Likewise, thelogic in clock domain 2 never attempts toreset the Flancter unless it sees that it hasbeen set. Establishing this kind of inter-locked protocol guarantees that both of theFlancter’s flip-flops won’t be clocked simul-taneously (or within each other’s setup andhold time windows).

Applications of the Flancter

There are many applications of theFlancter, but a very common application isinterfacing a microprocessor to an FPGA.Typically, the microprocessor and FPGAlogic run on separate clocks. When themicroprocessor writes a control registerwithin the FPGA, the Flancter can be usedas a status flag to tell an internal statemachine that new data is available.

value of Q1. Also, OUT goes low becauseit is the XOR of Q1 and Q2.

• At point C, Q1 again gets the invertedvalue of Q2, causing OUT to go high.

• At point D, Q2 goes low because it getsthe value of Q1, causing OUT to go low.

So What’s Wrong With It?

Applications Circuit Design

B

SET_CLK

SET_CE

Q1

Q2

OUT

A C

D

RESET_CLK

RESET_CE

Figure 3 - Basic Flancter timing

Figure 2 - Rearranged Flancter

Figure 1 - Basic Flancter.

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Likewise, a state machine within theFPGA can use the Flancter to generate aninterrupt to the microprocessor that is sub-sequently cleared by a read or interrupt-acknowledge cycle from the microproces-sor, as shown in Figure 4.

Things to notice in Figure 4:

• The Flancter is made up of FF1, FF2, theinverter, and the XOR gate.

• The state machine, FF1, FF3, and FF4are all synchronous to SYSCLK.

• The microprocessor (µP) runs off its ownclock, PCLK.

• The state machine pulses SET_CE forone SYSCLK cycle when it needs torequest an interrupt.

• The microprocessor performs a readcycle from a predefined address to resetthe interrupt. Although not shown, read-ing from this address may also cause astatus register to be driven onto themicroprocessor’s data bus allowingsimultaneous reading of status and reset-ting of interrupt.

• FF3 and FF4 are resynchronizing flip-

flops used to filter any metastable logicconditions from propagating into thestate machine.

• The particular microprocessor used inthis example employs metastable resistant

techniques on its INT input.

• The interrupt sequence is defined suchthat setting and resetting the interruptflag cannot occur simultaneously.

The following timing diagram helps illus-trate the operation:

Things to notice in Figure 5:

• The FPGA’s state machine sets the inter-rupt request (INT) at point A.

• Sometime later, the microprocessorresponds to the interrupt by reading astatus register, thus resetting the inter-rupt request at point B.

Variations on a Flancter

While the basic Flancter is very simple, manyuseful variations are possible. I describe someof the more interesting variations in theFlancter app-note available on our website,h t t p : / / w w w. m e m e c d e s i g n . c o m /resources/guides/. Some of the variationsyou’ll find there include the 3-way Flancter,the n-way Flancter, the async-reset emulatingFlancter, and the default-to-active-highFlancter. The app-note also has VHDL andVerilog listings for the basic Flancter.

Conclusion

I turned 37 this year and I got to thinkingthat all the “greats” did their best work longbefore they reached my age. As I look backon my design career, I realize that I haven’tdesigned any circuits or developed any the-orems that will bear my name like thePierce Oscillator or Shannon’s SamplingTheorem. The best I can do is to offer theFlancter as my legacy. Perhaps someday, theWeinstein-Flancter will be found in theindexes of engineering tomes right betweenWatt-Hour and Wien-Bridge.

SYSCLK

SET_CE

Q1

Q2

INT

A

RD_L

RESET_CE

ADDRESS

B

Status Address

Product Focus Circuit Design

Figure 5 - Flancter interrupt timing diagram

Figure 4 - Flancter used for microprocessor interrupt

56

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by Russ SinagraMarketing Manager GPD, [email protected]

A number of Avnet customers, in variouslocations across North America, were look-ing for a simple and flexible way to developa PCI interface to an Intel StrongARMprocessor, and several Avnet FAEs (FieldApplications Engineers) across the countryhelped their customers develop uniquesolutions for their individual designs. Then,during an Avnet FAE design review wherethe PCI requirements of different cus-tomers were discussed, it became apparentthat there were a number of commonrequirements for a PCI interface—and theyrealized there was a common solution tomany different problems.

By using Spartan-II FPGAs from Xilinx, theAvnet FAEs knew they had a great opportu-nity to provide an aggressively priced yet flex-ible PCI connection that would meet theneeds of many customers. The FAEs knewthat this would be a great way to highlight anumber of Avnet Design Services (ADS)strengths as well.

The CatapultTM StrongARM PCI Development Kit

Avnet combined their ADS board-levelsolution services, their FPGA services, andtheir ability to create Intellectual Property,to create the Catapult StrongArm PCIDevelopment Kit, a solution that coversmany needs (Fig.1). This kit gives you atime-to-market boost by integrating all thekey product technologies into a singledevelopment environment.

A StrongArm SA1110 Processor providesthe processing power and a Xilinx Spartan-II XC2S100 implements a glueless inter-face between the SA1110 processor busand the industry standard PCI bus. Alongwith these hardware resources, AvnetDesign Services provides IP cores for PCI,

SDRAM control, and theStrongArm interface as a startingpoint for your specific applica-tion. In addition to the IP core,software is provided to helpdevelop your embedded appli-cation. Applications develop-

ment software is also available from AvnetDesign Services or third parties. AvnetDesign Services can also provide engineer-ing consulting services, helping you toquickly customize your design to furtherspeed your time to market.

The kit sells for $8,995.00 and is availablenow from your local Avnet distributor. Formore information, visit the Avnet site at:http://www.ads.avnet.com

Column Distribution

Avnet is a key member of the Xilinx sales force, helping our customers create solid designs using innovative development tools

Distribution Adds Value:Intel StrongARM Supported with Xilinx Spartan-II FPGAs

Figure 1 - Catapult block diagram

57

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Reference Virtex

Each Virtex family has its own unique fea-tures to meet different application require-ments. All devices have both distributedRAM and block RAM, and between fourand eight DLLs for efficient clock manage-ment.

• The Virtex family, consisting of devicesthat range from 50K up to 1 million logicgates, supports 17 I/O standards, and offers5V PCI compliance.

• The Virtex-E familyoffers the highest logicgate count available forany FPGA, rangingfrom 50K up to 3.2million system gates,and supports 20 I/Ostandards includingLVPECL, LVDS, andBus LVDS differentialsignaling.

• The Virtex-EMExtended Memoryfamily consists of twodevices that have ahigh RAM-to-logicgate ratio that is target-ed for specific applica-tions such as gigabitper second networkswitches and high defi-nition graphics.

Virtex and XC4000X Series FPGAs

Designed in an advanced 0.25 micronprocess, the XC4000X series delivers indus-try-leading performance while significantlyreducing power consumption.

See www.xilinx.com for more information.

The XC4000X Series is part of the broadspectrum of Xilinx “XL” products unveiledSeptember, 1998. As a result, Xilinx offersthe broadest choice of 3.3 volt and 2.5 voltdevices available from a single supplier, withdensities ranging from 800 to 500,000 sys-tem gates. With 12 family members rangingfrom 30,000 to 500,000 system gates, thedevices feature patented SelectRAM memo-ry, with a highly flexible arrangement oflogic, single-port, or dual-port memory.

FPGA Product Selection Matrix

DEVICES KEY FEATURES

XC4013XLA 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y

XC4020XLA 1862 20K 13K-40K 25K 28x28 784 2016 205 12/24 Y

XC4028XLA 2432 28K 18K-50K 33K 32x32 1024 2560 256 12/24 Y

XC4036XLA 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y

XC4044XLA 3800 44K 27K-80K 51K 40x40 1600 3840 320 12/24 Y

XC4052XLA 4598 52K 33K-100K 62K 44x44 1936 4576 352 12/24 Y

XC4062XLA 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y

XC4085XLA 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y

XCV50 1728 21K 34K-58K 56K 16x24 384 1536 180 2/24 Y

XCV100 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y

XCV150 3888 47K 93K-165K 102K 24x36 864 3456 260 2/24 Y

XCV200 5292 64K 146K-237K 130K 28x42 1176 4704 284 2/24 Y

XCV300 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y

XCV400 10800 130K 282K-468K 230K 40x60 2400 9600 404 2/24 Y

XCV600 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y

XCV800 21168 254K 511K-888K 406K 56x84 4704 18816 512 2/24 Y

XCV1000 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y

XCV50E 1728 21K 47K-72K 88K 16x24 384 1536 176 2/24 Y

XCV100E 2700 32K 105K-128K 118K 20x30 600 2400 176 2/24 Y

XCV200E 5292 64K 215K-306K 186K 28x42 1176 4704 284 2/24 Y

XCV300E 6912 83K 254K-412K 224K 32x48 1536 6144 316 2/24 Y

XCV400E 10800 130K 413K-570K 310K 40x60 2400 9600 404 2/24 Y

XCV600E 15552 187K 679K-986K 504K 48x72 3456 13824 512 2/24 Y

XCV1000E 27648 332K 1,146K-1,569K 768K 64x96 6144 24576 660 2/24 Y

XCV1600E 34992 420K 1,628K-2,189K 1062K 72x108 7776 31104 724 2/24 Y

XCV2000E 43200 518K 1,857K-2,542K 1240K 80x120 9600 38400 804 2/24 Y

XCV2600E 57132 686K 2,221K-3,264K 1530K 92x138 12696 50784 804 2/24 Y

XCV3200E 73008 876K 2,608K-4,074K 1846K 104x156 16224 64896 804 2/24 Y

XCV405E 10800 130K 1,068K-1,307K 710K 40x60 2400 9600 404 2/24 Y

XCV812E 21168 254K 2,569K-3,062K 1414K 56x84 4704 18816 556 2/24 Y

* I/Os are 5V tolerant** 5 Volt tolerant I/Os with external resistorX = Core and I/O voltageI/Os = I/O voltage supported

– – – X– – – X– – – X– – – X– – – X– – X *– – X *– – X *– – X *– – X *– X I/O *– X I/O *– X I/O *– X I/O *– X I/O *– – X *– – X *X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **

XC4000 Series:Density

Leadership/High Performance/

SelectRAMMemory

Virtex Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O

4 DLLs

Virtex-E Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O+

8 DLLsLVDS, BLVDS,

LVPECL

Virtex ExtendedMemory Capabilities

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3 Vo

lt

5 Vo

lt

FPGA Product Selection Matrix

58

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Reference Spartan

DEVICES KEY FEATURES

XCS05 238 3K 2K-5K 3K 10x10 100 360 77 12 Y – – – X

XCS10 466 5K 3K-10K 6K 14x14 196 616 112 12 Y – – – X

XCS20 950 10K 7K-20K 13K 20x20 400 1120 160 12 Y – – – X

XCS30 1368 13K 10K-30K 18K 24x24 576 1536 192 12 Y – – – X

XCS40 1862 20K 13K-40K 25K 28x28 784 2016 205 12 Y – – – X

XCS05XL 238 3K 2K-5K 3K 10x10 100 360 77 12/24 Y – – X *

XCS10XL 466 5K 3K-10K 6K 14x14 196 616 112 12/24 Y – – X *

XCS20XL 950 10K 7K-20K 13K 20x20 400 1120 160 12/24 Y – – X *

XCS30XL 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y – – X *

XCS40XL 1862 20K 13K-40K 25K 28x28 784 2016 224 12/24 Y – – X *

XC2S15 432 8K 6K-15K 22K 8x12 96 384 86 2/24 Y – X I/0 *

XC2S30 972 17K 13K-30K 36K 12x18 216 864 132 2/24 Y – X I/0 *

XC2S50 1728 30K 23K-50K 56K 16x24 384 1536 176 2/24 Y – X I/0 *

XC2S100 2700 53K 37K-100K 78K 20x30 600 2400 196 2/24 Y – X I/0 *

XC2S150 3888 77K 52K-150K 102K 24x36 864 3456 260 2/24 Y – X I/0 *

XC2S200 5292 103K 71K-200K 130K 28x42 1,176 4704 284 2/24 Y – X I/0 *

* I/Os are tolerantX = Core and I/O voltageI/Os = I/O voltage supported

FPGA Product Selection Matrix

Spartan Family:High Volume

ASICReplacement/

High Performance/SelectRAM Memory

Spartan-XL Family:High Volume

ASICReplacement/

High Performance/SelectRAM Memory

Spartan-II Family:High VolumeBlockRAM

Distributed RAMSelectI/O

4 DLLs

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3.3

Volt

5.0

Volt

FPGA Product Selection Matrix

Say hello to a new level of performance; theSpartan-II family now includes deviceswith over 200,000 system gates, and youget 100,000 system gates for under $10, atspeeds of 200Mhz and beyond, giving youdesign flexibility that’s hard to beat. Theselow-powered, 2.5-V devices feature I/Osthat operate at up to 3.3V with full 5-Vtolerance. Spartan-II devices also featuremultiple Delay Locked Loops, on-chipRAM (block and distributed), and versatileI/O technology that supports over 16 high-performance interface standards. You getall this in an FPGA that offers unlimitedprogrammability, and can even be upgrad-ed in the field, remotely, over any network.

Robust Feature Set

• Flexible on-chip distributed andblock memory.

• Four digital Delay Locked Loops forefficient chip-level/board-level clockmanagement.

• Select I/O Technology for interfacingwith all major bus standards such asHSTL, GTL, SSTL, and so on.

• Full PCI compliance.

• System speeds over 200 MHz.

• Power management.

Extensive Design Support

• Complete suite of design tools.

• Extensive core support.

• Compile designs in minutes.

Advantages Over ASICs

• No costly NRE charges.

• No time consuming vector generationneeded.

• All devices are 100% tested by Xilinx.

• Field upgradeable (remotely upgrade-able, using Xilinx Online technology).

• No lengthy prototype or productionlead times.

• Priced aggressively against comparableASICs.

For more information see www.xil-inx.com/products/spartan2

59

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Reference CPLDs

Whether performinghigh speed network-ing-based or power-conscious portabledesigns, XilinxCPLDs provide youwith a completerange of value ori-ented products.

XC9500 - Offers industry-leading speeds, while giv-ing you the flexibility of anenhanced customer-provenpin-locking architecturealong with extensive IEEEStd. 1149.1 JTAGBoundary-Scan support.

CoolRunner - Offers thepatented Fast Zero Power(FZP() design technology,combining low power andhigh speed. These devicesoffer standby currents ofless than 100 microamps,operating currents 50-67%lower than traditionalCPLDs, and pin-to-pinspeeds of 5.0ns.

Core

Vol

tage

CPLD

Fam

ily

Devi

ces

Key

Feat

ures

Mac

roce

lls

Max

. I/O

Pin-

to-P

inDe

lay

(ns)

Syst

emFr

eque

ncy

Indi

vidu

alOE

Ctrl

JTAG

Ultra

Low

-Pow

er

Phili

psPa

rt N

umbe

r

XC9500XL

XPLA3

XPLA-Enhanced

XPLA2

XC9500

XPLA-Enhanced

XC9536XL 36 36 4 200 √ √XC9572XL 72 72 5 178.6 √ √XC95144XL 144 117 5 178.6 √ √XC95288XL 288 192 6 151 √ √XCR3032XL 32 32 5 200 √ √XCR3064XL 64 64 6 166 √ √XCR3128XL 128 104 6 166 √ √XCR3256XL 256 160 7.5 133 √ √XCR3384XL 384 216 7.5 133 √ √XCR3032A 32 32 6 111 √ √ PZ3032A

XCR3064A 64 64 7.5 95 √ √ PZ3064A

XCR3128A 128 96 7.5 95 √ √ PZ3128A

XCR3320 320 192 7.5 100 √ √ PZ3320C

XCR3960 960 384 7.5 100 √ √ PZ3960C

XC9536 36 34 5 100 √ √

XC9572 72 72 7.5 83.3 √ √

XC95108 108 108 7.5 83.3 √ √

XC95144 144 133 7.5 83.3 √ √

XC95216 216 166 10 66.7 √ √

XC95288 288 192 10 66.7 √ √XCR5032C 32 32 6 111 √ √ PZ5032C

XCR5064C 64 64 7.5 105 √ √ PZ5064C

XCR5128C 128 96 7.5 100 √ √ PZ5128C

Best Pin-LockingJTAG w/ClampHigh PerformanceHigh Endurance

Ultra Low PowerJTAGIncreased LogicFlexibility

Ultra Low PowerJTAG

Ultra Low PowerHigh Density

Best Pin-LockingJTAGHigh Endurance

Ultra Low PowerJTAG

3.3 VoltISP

5 VoltISP

CPLD Product Selection Matrix Density Features

WebPOWERED Software Solutions - Offeryou the flexibility to target the XC9500and CoolRunner Series CPLDs on-line oron the desktop, including:

• WebFITTER - an on-line device fittingand evaluation tool that accepts HDL,ABEL, or netlist files and provides allreports, simulation models, and pro-gramming files, along with price quotes.

• WebPACK - downloadable desktop solu-tions that offer free CPLD software

modules for ABEL/HDL synthesis andsimulation, device fitting, and JTAGprogramming.

Through leading performance, free inter-net-based WebPOWERED software andthe industry’s lowest power consumption,Xilinx has the right CPLD for everydesigner’s need.

See www.xilinx.com/products/cpldsolu-tions/index.htm for more information

XC9500 and CoolRunner CPLDs

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Reference PROMs

Configuration XC17xx/XC18VxxFPGA Bits Solution PD8 PC20 SO20 PC44 VQ44

XCV50 558,048 01 X* X X X**XCV100 780,064 01 X* X X X**XCV150 1,038,944 01 X* X X X**XCV200 1,334,688 02 X XXCV300 1,750,656 02 X XXCV400 2,544,896 04 X XXCV600 3,606,816 04 X XXCV800 4,714,400 04 + 512 X XXCV1000 6,126,528 04 + 02 X X* Available on XC17xx only

** Available on XC18Vxx only

Configuration PROMs for Virtex

Configuration XC17xx/XC18VxxFPGA Bits Solution PD8 PC20 SO20 PC44 VQ44

XCV50E 630,048 01 X** X X X***XCV100E 863,840 01 X** X X X***XCV200E 1,442,106 02 X XXCV300E 1,875,648 02 X XXCV400E 2,693,440 04 X XXCV405E 3,430,400 04 X XXCV600E 3,961,632 04 X XXCV812E 6,519,648 04+04 or 08* X XXCV1000E 6,587,520 04+04 or 08* X XXCV1600E 8,308,992 04+04 or 08* X XXCV2000E 10,159,648 04+08* or 16* X XXCV2600E 12,922,336 16* X XXCV3200E 16,283,712 16* X X* In development** Available on XC17xx only*** Available in XC18Vxx only

Configuration PROMs for Virtex-E

Xilinx offers a full range of configuration memo-ries optimized for use with Xilinx FPGAs. OurPROM product lines are designed to meet thesame stringent demands as our high-performanceFPGAs and CPLDs, taking full advantage of thesame advanced processing technologies. In addi-tion, they were developed in close cooperationwith Xilinx FPGA designers for optimal perform-ance and reliability.

XC18V: Our in-system re-programmable familyprovides a feature-rich, fast configuration solutionunmatched by any other configuration PROMavailable today, and provides a cost-effectivemethod for re-programming and storing largeXilinx FPGA bitstreams. This family is JTAGready and Boundary-Scan enabled for exceptionalease-of-use, system integration, and flexibility.

XC17V/XC17S: Our low-cost XC17V and XC17Sfamilies are an ideal configuration solution forcost-sensitive applications. XC17V00 PROMs arepin-compatible with our 18V family to allow for acost-reduction migration path as your productionvolumes increase. The XC17S family is speciallydesigned to provide a low-cost, integrated solutionfor our Spartan families of FPGAs.

XC18V

XC17V

XC17S

F P G A C o n f i g u r a t i o n s

PROM Density PD8 SO20 PC20 PC44 VQ44 JTAGISP

XC1765EL(X) 64Kb X X X XXC17128EL(X) 128Kb X X XXC17256EL(X) 256Kb X X XXC17512L 512Kb X X XXC1701L 1Mb X X X XXC1702L 2Mb X XXC1704L 4Mb X XXC18V128 128Kb X X XXC18V512 512Kb X X X XXC18V01 1Mb X X X XXC18V02 2Mb X X XXC18V04 4Mb X X XNote: XC1700EL parts are marked with an “X” instead of “EL”

3.3V Configuration PROMs

FPGA Configuration Bits Family PROM Solution PD8 VO8 SO20XCS05XL 54,544 Spartan XL XC17S05XL X X XCS10XL 95,752 Spartan XL XC17S10XL X XXC2S15 197,696 Spartan II XC17S15XL X XXCS20XL 179,160 Spartan XL XC17S20XL X XXCS30XL 249,168 Spartan XL XC17S30XL X XXC2S30 336,768 Spartan II XC17S30XL X XXCS40XL 330,696 Spartan XL XC17S40XL X X* XXC2S50 559,232 Spartan II XC17S50XL X XXC2S100 781,248 Spartan II XC17S100XL X XXC2S150 1,041,128 Spartan II XC17S150XL X XXC2S200 1,335,872 Spartan II XC17S200XL* X X* In development

3.3V Configuration PROMs for Spartan-XL/Spartan-II

61

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The Xilinx QPRO family of RadiationHardened FPGAs and PROMs are findinghomes in many new satellite and spaceapplications. Both the XQR4000XL andXQVR Virtex products are being designedinto space systems that will utilize reconfig-urable technology. Numerous communica-tions and GPS satellites, space probe, andshuttle missions are included on the grow-ing list of programs that will be flying thesedevices.

because their systems can retain consistentform, fit, and function through the use ofVirtex QPRO FPGAs. This cannot beachieved with costly and inflexible ASICsor custom logic.

Please visit http://www.xilinx.com/prod-ucts/hirel_qml.htm for all the latest infor-mation about these products, includingsome new applications notes.

The Virtex QPRO family of HighReliability products is experiencing a highdegree of success in the defense market. Asdesigners find it more and more difficult tofind components suitable for the harshenvironments seen by defense systems, theyare discovering that they can incorporatethe functions of obsolete parts into VirtexQPRO products. This has the added longterm advantage of significantly reducingthe costs of future re-qualifications,

Reference QPRO

DEVICES KEY FEATURES

XQR/XQ4013XL 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y

XQR/XQ4036XL 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y

XQR/XQ4062XL 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y

XQ4085XL 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y

XQV100 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y

**XQVR/XQV300 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y

**XQVR/XQV600 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y

**XQVR/XQV1000 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y

* I/Os are tolerant** XQR and XQVR devices are Radiation HardenedX = Core and I/O voltageI/Os = I/O voltage supported

(1) All devices specified from -55°C to +125°C(2) Selected XQ4000E/EX devices also available

– – X *– – X *– – X *– – X *– X I/O *– X I/O *– X I/O *– X I/O *

XC4000 Series:Density

Leadership/High Performance/

SelectRAMMemory

Virtex Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O 4 DLLs

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3 Vo

lt

5 Vo

lt

FPGA Product Selection Matrix

XC1736D 36Kb XXC1765D 64Kb XXC17128D 128Kb XXC17256D 256Kb XXQR/XQ 1701L* 1Mb X XXQR/XQ 1704L* 4Mb X X*** XQR devices are Radiation Hardened.** XQ devices only.

QPRO QML-certified PROMsPackage

Device Density DD8 SO20 CC44 PC44

QPRO QML-Certified FPGAs and PROMs

62

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Lead Product Feature Comparison

Alliance Series Foundation Series ISE Series

ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX

Design Entry

Schematic Entry √ √ √ √ √ √ √

HDL Entry √ √ √ √ √ √ √

ABEL Entry √ √ √ √ √ √ √

HDL Editor √ √ √ √ √ √ √

State Diagram Editor √ √ √ √ VSS* VSS* VSS*

Environment

Operating System PC/UNIX PC/UNIX PC PC PC PC PC PC PC

Simulation

Gate Level Timing Simulation √ √ √ √

HDL Simulation MTI** MTI** MTI** MTI** MTI** MTI** MTI** MTI** MTI**

HDL Test Bench Generator VSS* VSS* VSS*

Synthesis

Xilinx Synthesis Technology (XST) √ √ √

FPGA Express √ √ √ √ √ √ √

Incremental Synthesis √ √ √ √ √ √ √

System Features ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX

Constraints editor √ √ √ √ √ √ √ √ √

Floorplanner √ √ √ √ √ √ √ √ √

CPLD ChipViewer √ √ √ √ √ √ √ √ √

Pin Editor √ √ √ √ √ √ √ √ √

FPGA Editor √ √ √ √ √ √ √ √ √

Core Generator included √ √ √ √ √ √ √ √ √

Configuration by cable √ √ √ √ √ √ √ √ √

Error navigation to Xilinx Web √ √ √

Command line operation √ √ √

HTML timing reports √ √ √ √ √ √ √ √ √

Data Book I/O timing √ √ √ √ √ √ √ √ √

Project archiving √ √ √ √ √ √ √ √ √

System Interfaces

EDIF in √ √ √ √ √ √

PROM file generation √ √ √ √ √ √ √ √ √

JTAG download software √ √ √ √ √ √ √ √ √

IBIS √ √ √ √ √ √ √ √ √

STAMP √ √ √ √ √ √ √ √ √

VHDL, Verilog √ √ √ √ √ √ √ √ √

HDL Simulation libraries √ √ √ √ √ √ √ √ √

*VSS - Delivered as part of the ALLSTAR program or as a backPACK module in WebPACK

Lead Product Device Support Comparison

Alliance Series Foundation Series ISE Series

Family Part Number ALI-STD ALI-ELI FND-EXP FND-ELI FND-BAS FND-BSX ISE-ELI ISE-EXP ISE-BSX

Virtex XCV50 only √ √ √All devices up to

√ √ √ √ √ √XCV1000

Virtex-E XCV50E only √ √ √

All devices up to√ √ √ √ √ √XCV1000E

All devices up to√ √ √XCV3200E

Virtex-EM XCV405EM √ √ √ √ √ √

XCV812EM √ √ √ √ √ √

Spartan XCSxx√ √ √ √ √ √ √ √ √(All devices)

Spartan XL XCSxxXL√ √ √ √ √ √ √ √ √(All devices)

Spartan-II XC2SxxXL(Includes √ √ √ √ √ √ √ √ √XC2S200)

XC9500 XC9500 XV/XL√ √ √ √ √ √ √ √

√Series (All devices)

XC400 XC4000E/L/EX√ √ √ √ √ √ √ √

√Series (All devices)

XC4000XL/XLA(All devices up to √ √ √XC4020)

XC4000XL/XLA√ √ √ √ √ √(All devices)

XC4000XV√ √ √ √ √ √(All devices)

XC3000 XC3x00A/L√ √ √ √ √ √Series (All devices)

XC5200 XC5200√ √ √ √ √ √Series (All devices)

*Note: CoolRunner Series is only available in WebFITTER and WebPACK at this time.

Xilinx development systems give you thespeed you need. With version 3.1i solu-tions, Xilinx place and route times are asfast as 2 minutes for our 200,000 gate,XC2S200 Spartan(r)-II device, and 30minutes for our 1 million gate, system-levelXCV1000E Virtex(tm)-E device. Thatmakes Xilinx development systems thefastest in the industry.

And with the push of a button, our timing-driven tools are creating designs that sup-port I/O speeds in excess of 800 Mbps, andinternal clock frequencies in excess of 300MHz.

These development solutions combinepowerful technology with a flexible, easy touse graphical interface to help you achievethe best possible designs within your proj-ect schedule, regardless of your experiencelevel.

Reference Software

63

Page 64: Xilinx Xcell Journal 37 - complete issue (Q3 2000)...to success are complex and they change constantly. It’s difficult for any one company to master all of the necessary functions

You can betyour ASIC on it.

The Programmable Logic CompanySM

The Spartan®-II family offers a

winning combination of perfor-

mance and price. In fact with

over 200,000 system gates, clock

speeds beyond 200MHz, and lightning fast

compile times, Spartan-II FPGAs give you the

best dollar value in the industry.

Get rid of the risk

Now you’ve got the design flexibility you’ve

been waiting for, without any annoying NRE

costs, strung-out production times, or the design

risks associated with a typical ASIC. To save system

costs, there’s also multiple Delay Locked Loops, on-chip

RAM (block and distributed), and our unique SelectI/O™

interface technology.

Xilinx IP Center completes the total solution

The Xilinx IP Center brings you all the

FPGA cores, reference designs, design

services and third party support you could

wish for, all easily available via the web.

Find out more today by visiting us at

www.xilinx.com/sp1.htm. You’ll soon see

why you can bet your ASIC on us.

© 2000 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia +852-2-424-5200; Xilinx and Spartan are registered trademarks,

and SelectI/O are trademarks and The Programmable Logic Company is a service mark of Xilinx, Inc.

www.xilinx.com