Download pdf - 32bit multiplier

Transcript
  • 7/25/2019 32bit multiplier

    1/23

    SYSTEM EVALUATION OF 32BIT UNNSIGNED MULTIPLERUSING CLAA AND CSLA

    Presente

    Sivasank

    M.Tech ,

    Priyada

    Techno

    Under the guidance of

    Mr. SOMASEKHAR .A

    Assistant Professor

    Dept. of ECE

    Priyadarshini Institute of Technology & Management

  • 7/25/2019 32bit multiplier

    2/23

    C!TE!TS

    A"ST#ACT$!T#DUCT$!

    E%$ST$!& S'STEM

    P#"(EMS $! E%$ST$!& S'STEM

    P#PSED S'STEM

    S(UT$! ) T*E P#"(EM

    S$MU(AT$! #ESU(TS ) #E&U(A# CS(A

    AD+A!TA&ES APP($CAT$!S

    C!C(US$!

  • 7/25/2019 32bit multiplier

    3/23

    A"ST#ACT

    Carry Se-ect Adder CS(A/ is one of the fastest adders used in 0

    processing processors to perfor0 fast arith0etic functions.

    "y gate -eve- 0odification of CS(A architecture 2e can reduce area and

    "ased on this 0odification341bit 0u-tip-ication CS(A architecture

    deve-oped.

    The proposed design has reduced area and po2er as co0pared 2ith

    0u-tip-er,CS(A . This 2ork eva-uates the perfor0ance of the proposed designs in ter0

    po2er by hand 2ith -ogica- effort and through %i-in5 $SE 67.6+eri-og

    this 2i-- be i0p-e0ented in )P&A Sparton 8/.

  • 7/25/2019 32bit multiplier

    4/23

    $!T#DUCT$!

    $n e-ectronics, an adder or su00er is a digita- circuit that perforof nu0bers.

    Adders can be constructed for 0any nu0erica- representations, sucE5cess13, the 0ost co00on adders operate on binary nu0bers.

    Adders p-ays Ma9or ro-e in Mu-tip-ications and other advanced

    designs

  • 7/25/2019 32bit multiplier

    5/23

    E%$ST$!& S'STEM

    The carry1se-ect adder genera--y consists of t2o #ipp-e CarryAdders #CA/ and a Mu-tip-e5er .

    Adding t2o n1bit nu0bers 2ith a carry1se-ect adder is done 2ith therefore t2o #CA/.

    $n order to perfor0 the ca-cu-ation t2ice, one ti0e 2ith the assu0carry being :ero and the other assu0ing one.

  • 7/25/2019 32bit multiplier

    6/23

    #E&U(A# 34 bit 0u-tip-ier CS(A

  • 7/25/2019 32bit multiplier

    7/23

    AREA EVALUATION METHODOLOGY OF REGULAR 16-bitmuti!i"# CSLA

    G$t" %&u't(

    )*+HA,FA,MU.

    FA(3/+3013.

    HA(6+106.

    MU(12+30.

  • 7/25/2019 32bit multiplier

    8/23

    P#"(EMS $! E%$ST$!& S'STEM

    The prob-e0 in CS(A design is the nu0ber of fu-- adders are incrthe circuit co0p-e5ity a-so increases.

    The nu0ber of fu-- adder ce--s are 0ore thereby po2er consu0ptdesign a-so increases

    !u0ber of fu-- adder ce--s doub-es the area of the design a-so increa

  • 7/25/2019 32bit multiplier

    9/23

    S(UT$! ) T*E P#"(EM

    The para--e- #CA 2ith Cin;6 is rep-aced 2ith "inary1E5cess 6 converte

    &u#-bit BEC

  • 7/25/2019 32bit multiplier

    10/23

    M&i4" CLSA

    "asic function of C(SA is obtained by using the

  • 7/25/2019 32bit multiplier

    11/23

    P#PSED S'STEM681b C(SA/

  • 7/25/2019 32bit multiplier

    12/23

    $n this syste0 2e use the "EC to reduce the #CA circuits*ere based on the carry input the MU% 2i-- be se-ect corresponding

    $n this design 2e give the MU% inputs are #CA output and "EC ou

    Co0pare to regu-ar design the area of the design is -ess

    Contd=

  • 7/25/2019 32bit multiplier

    13/23

    AREA EVALUATION METHODOLOGY OF MODIFIEmu!ti!i"# CSLA

    &ATE CU!T;

    )A>MU%>"EC/

    63>8>64>6>6>67)

  • 7/25/2019 32bit multiplier

    14/23

    COMPARISION

    GROUP REGULAR MODIFIED

    UP 4 ?@

  • 7/25/2019 32bit multiplier

    15/23

    RTL SCHEMATIC

  • 7/25/2019 32bit multiplier

    16/23

  • 7/25/2019 32bit multiplier

    17/23

    Simu$ti&' R"ut

  • 7/25/2019 32bit multiplier

    18/23

    Eva-uation #esu-ts

    Po2er Uti-i:ed ; 34 0B

    De-ay; 68.47< ns

  • 7/25/2019 32bit multiplier

    19/23

    T( USEDProgra00ing -anguage +E#$(& *D(

    Too- %i-in5 $SE 67.6/

  • 7/25/2019 32bit multiplier

    20/23

    AD+A!TA&ES

    (o2 po2er consu0ption(ess area -ess co0p-e5ity/

    More speed co0pare regu-ar CS(A

  • 7/25/2019 32bit multiplier

    21/23

    APP($CAT$!S

    Arith0etic -ogic units*igh Speed 0u-tip-ications

    Advanced 0icroprocessor design

    Digita- signa- process

  • 7/25/2019 32bit multiplier

    22/23

    CONCLUSION

    A si0p-e approach is proposed in this paper to reduce the area

    of MU(T$P($E# CS(A architecture. The reduced nu0ber of gates o

    offers the great advantage in the reduction of area and a-so the p

    0odified CS(A architecture is therefore, -o2 area, -o2 po2er,

    efficient for +(S$ hard2are i0p-e0entation.

  • 7/25/2019 32bit multiplier

    23/23

    #E)E#E!CES

    6 ". #a0ku0ar, *arish M Fittur G(o2 po2er and Area efficient carry se-ect adTrans,+o-.47,)eb 4764.

    4 T. '. Ceiang and M. I. *siao, GCarry1se-ect adder using sing-e ripp-e carry addeLett., vol. 34, no. 22, pp. 21012103, Oct. 1998.

    3 '. Fi0 and (.1S. Fi0, G8