Download ppt - ARM Cortex-M0 August 22, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. CORTEX-M0 Structure Discussion

ARM Cortex-M0

August 22, 2012Paul Nickelsberg

Orchid Technologies Engineering and Consulting, Inc.

www.orchid-tech.com

CORTEX-M0 StructureDiscussion 2 – Core

Peripherals

Cortex-M0 StructureDiscussion 2 – Core

PeripheralsTopics Today

• CORTEX-M0 SYSTICK Core Peripheral• CORTEX-M0 NVIC Core Peripheral• CORTEX-M0 SCB Core Peripheral

Cortex-M0 Core Peripherals

Cortex-M0 32 Bit CPU

SYSTICK NVIC SCB

Core Peripherals are Common to All Cortex Devices

Core Peripheral Memory Map

MemoryRegion Usage

Memory Attribute

XN Memory Region Start

Memory Region Stop

Device Access Device XN 0xE0100000 0xFFFFFFFF

Private Peripheral Strongly Ordered XN 0xE0000000 0xE00FFFFF

External Device Device XN 0xA0000000 0xDFFFFFFF

External Memory Normal -- 0x60000000 0x9FFFFFFF

Internal Peripheral Device XN 0x40000000 0x5FFFFFFF

Internal SRAM Normal -- 0x20000000 0x3FFFFFFF

Internal Code Execute Normal -- 0x00000000 0x1FFFFFFF

Core Peripheral Memory Map

Core Peripheral Memory Region Start

Memory Region Stop

Nested Vector Controller (NVIC) 0xE000EF00 0xE000EF03

System Control Block (SCB) 0xE000ED00 0xE000ED3F

Nested Vector Controller (NVIC) 0xE000E100 0xE000E4EF

SysTick Timer (STK) 0xE000E010 0xE000E01F

System Control Block (SCB) 0xE000E008 0xE000E00F

SYSTICK Core Peripheral

24-Bit Reload Register

24-Bit Down Counter

IRQ Control Register

Cortex-M0 CPU

SysTick Interrupt

System Clock


time

Time interval = Reload Count / Clock Frequency

P e r i o d i c I n t e r r u p t s


• Simple Periodic Interval Timer• Identical Structure in Cortex-M0, M3, M4• Settable Interrupt Priority• 24-Bit Counter Width• Count Enable Control• Interrupt Enable Control

Nested-Vectored Interrupt ControllerNVIC Core Peripheral

What is an Interrupt Controller?

INSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTION

Normal Program FlowInstruction Proceed in Sequence




INSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTION

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Interrupt Event

Interrupt Return


• An Interrupt Controller manages the process of interrupting normal program flow upon receipt of an interrupt event

• Interrupt Entry: • Push Stack Frame• Fetch Interrupt Vector

• Interrupt Exit: • Pop Stack Frame• Resume normal program execution



What is a ‘Vectored’ Interrupt Controller?

VECTOR 0VECTOR 1VECTOR 2VECTOR 3VECTOR 4VECTOR 5VECTOR 6VECTOR 7VECTOR 8VECTOR N

Interrupt Service Routine 2



Interrupt Service Routine 8 Interrupt

Controller

Ind

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Vector Table


• An Interrupt Vector is a unique 32-Bit value which is set to the Start Address of an Interrupt Service Routine

• Interrupt Vectors are Stored in a Sequential Table of Vectors

• Vectored Interrupts have low latency




Exception Number

IRQ Number Vector Offset

Initial Stack Value 0x001 Reset Vector 0x042 -14 NMI Vector 0x083 -13 Hard Fault Vector 0x0C4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED

10 RESERVED11 -5 SVCall Vector 0x2C12 RESERVED13 RESERVED14 -2 PendSV Vector 0x3815 -1 SYSTICK Vector 0x3C16 0 IRQ0 Vector 0x4017 1 IRQ1 Vector 0x4418 2 IRQ2 Vector 0x48• • • • 47 31 IRQ31 Vector 0xBC



Receive Interrupt

Branch to Global Service Routine

Determine Unique Interrupt

Service Unique Interrupt

Normal Program Flow

Return to Normal Program Flow

Receive Interrupt

Normal Program Flow

Service Unique Interrupt

Return to Normal Program Flow

VECTOREDNOT VECTORED

Has extra stepslonger latency

Older ARM7 Style New CORTEX Style

Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a ‘Nested’ Vectored Interrupt Controller?



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Low Priority High Priority


Nested Interrupt Support• Individual Interrupts have Priority• Higher Priority Interrupt will Preempt

Lower• Lower or Equal Priority Interrupt will Wait• Interrupt Tail Chaining to Reduce

Latency• Interrupt Late Arriving to Reduce

Latency


Interrupt Types Interrupt Priority

Reset Highest Priority -3

Non Maskable Interrupt (NMI) Priority -2

Hard Fault Priority -1

SVCall Configurable Priority

PendSV Configurable Priority

SysTick Configurable Priority

Interrupt (IRQ0 - 31) Configurable Priority


Interrupt Preemption Higher Priority Interrupt preempts lower priority interrupt

Interrupt Tail Chaining At completion of interrupt, it another interrupt event has occurred, then stack pop is skipped and new interrupt service starts

Interrupt Late Arriving If low priority interrupt begins and while saving the stack frame a higher priority interrupt occurs, then higher priority interrupt will execute first.


Normal program flow Normal program flowPush

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Int 2

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Interrupt Preemption – Int 2 Higher Priority Than Int 1



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Interrupt Tail Chaining – Int 1 Higher or Equal Priority Than Int 2



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Int 1

Int 2

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Interrupt Late Arriving – Int 2 Higher Priority Than Int 1

SCB Core PeripheralRegister Set which provides system implementation and system control functions

• CPU ID Register• Interrupt Control and State Register• Application Interrupt and Reset Control Register• System Control Register• Configuration Control Register• System Handler Priority Registers

Cortex-M0+ PeripheralMPC Core Peripheral

Memory Protection Unit• CORTEX-M0+ Eight Separate Regions• CORTEX-M0+ Overlapping Regions• CORTEX-M0+ Background Regions

Meaning and Implications

Processor Architecture – 8 Bit World to 32 Bit World

Pro

cess

ing

Cap

abili

ty

8 Bit Architecture

32 Bit CORTEX-M0

Sophisticated NVIC Interrupt ControlLow Latency Interrupt FeaturesVectoring, Preemption, Chaining, Late ArrivalCore Control FeaturesMemory Protection Unit