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ASE Confidential / Security-C ASE Confidential / Security-C

Co-Design for High Density SiP Module

Miniaturized Products Corp. R&D ASE Nov 11th, 2015

© ASE Group. All rights reserved.

ASE Confidential / Security-C

Outline

Market Opportunities and Trend

High Density Heterogeneous Integration Examples

Co-Design Capabilities

Conclusion



5G

SiP Module Growing Opportunities

2

Wearable SiP/Module Smartphone SiP/Module

WWAN/WLAN SiP/Module IOT SiP/Module

Processor:

AP, MCP,

BB, …

Data Center

http://www.google.com.tw/url?url=http://www.kpcb.com/blog/how-kleiner-perkins-invests-in-the-internet-of-things-picking-the-winners&rct=j&frm=1&q=&esrc=s&sa=U&ei=MCPkVJ6dKI3Z8gX0tYDoDA&ved=0CBsQ9QEwAw&sig2=RY5aDo-zAWpfG-hvjBH_XA&usg=AFQjCNH0J3gk-oU5qhY0utPjeqsoiUKvMw

http://www.google.com.tw/url?url=http://www.fandroides.com/devuelve-el-lte-a-tu-nexus-4-con-android-5-0-lollipop/&rct=j&frm=1&q=&esrc=s&sa=U&ei=bCPkVPeSNoKi8AWj7YDgDA&ved=0CCEQ9QEwBg&sig2=O7LYWnqyWeR0XSJMsfL15A&usg=AFQjCNEaPbHWlsx4VjW_YAVIW1Om7XeFuQ

http://www.google.com.tw/url?url=http://www.padgadget.com/2014/07/08/ipads-could-face-downturn-as-attention-shifts-to-wearable-devices/&rct=j&frm=1&q=&esrc=s&sa=U&ei=5CPkVKi_N4nz8gWRgIHgDA&ved=0CCEQ9QEwBjgo&sig2=pvCdYCwUhDlhzz0Ig5peXg&usg=AFQjCNHGDce0o0WAQ1JzHa2rUpSTCzEhUQ



Complexity of Heterogeneous SiP Module

Package

System/

Sub-system

Component

Optical

Sensor

RF/FEM

Connectivity

WWAN

Storage

Power

Component Count: 10 100 200 500

3

http://www.google.com.tw/url?url=http://en.wikipedia.org/wiki/Apple_S1&rct=j&frm=1&q=&esrc=s&sa=U&ei=ZhbjVJLbOs738QWXr4DwDw&ved=0CBUQ9QEwAA&sig2=p-d_wrzFXscPOToGDB2MHA&usg=AFQjCNESk3UG6md75JrM8etlFHrVTR1oyw



Wireless AP

Module

WWAN/WiFi/BT

Modem Module

WWAN/WiFi/BT

RF and FE

4G/Connectivity/5G SiP Module Trend

http://www.google.com.tw/url?url=http://en.wikipedia.org/wiki/Apple_S1&rct=j&frm=1&q=&esrc=s&sa=U&ei=ZhbjVJLbOs738QWXr4DwDw&ved=0CBUQ9QEwAA&sig2=p-d_wrzFXscPOToGDB2MHA&usg=AFQjCNESk3UG6md75JrM8etlFHrVTR1oyw



Trend and Examples

5


ASE Confidential / Security-C 6

RF/FEM •Cu Pillar FC (irregular) •Conformal/Compartment Shielding •Embedded substrate

Sensor •Non-standard form factor •Extended BOM •HD SMT, molding, shielding

Storage •Die & package stacking •Double-side Molding •Low Frq. Conformal Shielding

MPU/MCU •2.5D Organic/Si/Glass Interposer •3D TSV Die Stack •HB PoP

Wireless Connectivity •EMI Shielding •Embedded substrate •Double-side Molding •Antenna on Package

MEMS •Embedded Substrate •Wafer Level MEMS

Power Management •Embedded substrate •Low Frq. Conformal Shielding •Thermal mgmt.

DC/DC PMIC

Open cavity mold Combo sensor

Combo WiFi, BT, GPS, FM Low Power Wireless

Integration / Miniaturization Optimization / Simplification

FEM PAM Tx/Rx

Camera Module Biometric Sensor

Component Flash Micro SSD High BW PoP 2.5D/3D TSV

SiP Opportunities for Smartphone

ASE Confidential



SiP Opportunities for Wearable

ASE Confidential

RF Shielding •Conformal Shielding

•Compartment Shielding

Antenna on Package •Stamping Antenna (<5GHz)

•LCP/Laminate Antenna (>5GHz) •Simulation, Design and Validation

Embedded SBS •Embedded Passive SBS •Embedded Active SBS

-aEASi -SESUB

Double-Side Structure •Solder Frame Board

•Double-Side & Exposed Molding •HDSMT

Multi-Sensor Integration

•MCU+ RF+ Sensors •ARM(M0~M4), Firmware/Algorithm

•Motion (Accelerator, Gyro.) •Physiological Sign (HRM, ECG, SpO2..) •Environment (O2, CO, CO2, Security)

Multi-Sensor Embedded SiP

(Chips on Board)

• Advanced SiP solutions technology by integrating ASE group capability

7

Reduce X Y dimension

Reduce dimension and lower thickness

WiFi

Flash

MEMS

Optical Power

Antenna

MCU

GPS

BLE

Saving space



Miniaturization Trend

Million units shipment proven record to global leading accounts with

state-of-the-art miniaturization technology into LTE module

1st gen. LTE 2nd gen. LTE 3rd gen LTE

Mass Production 2014 Jun 2015 Aug 2016

Dim: X-Y (mm) 23x26 20x21.1 15x15

Dim: Z (mm) 1.95 1.5 2.1

Component Count 372 273 218

Miniaturize

Technology

5mil HD SMT, molding with compartment

shielding

WLCSP chipset,

5mil HD SMT,

BT Substrate, metal Lid

Solder Bumping chipset ,

Memory die stacking,

wire bond,

double side 4mil HD SMT

0402

DDR Die

SF Die

Inductor

X’tal TCXO

0201

0201

ALT6401 Bumped Die

ALT1160 Bumped Die

RF

Front End

component

SUS

52% Area Reduction

30 % Area Reduction



LTE Dual-Band Module Dimension

PMIC

Baseband

RF

25.9 mm

22

.4 m

m

Dual-Band LTE Data Modem.

25.9x22.4x1.85(mm).

High-Density SMT.

CPS Molding.

ALT-3100 inductor

t mm

1.2mm

0.05mm

0.07mm

FR4,6L

2-2-2(W)

0.63

Component (mm) 1.2

Solder Past (mm) 0.07

Molding (mm) 0.05

H (mm) 1.9

t (mm)

6LItem

Molding

H mm



RF

BB BB

Compartmental Shielding & Molding



WLCSP in LTE Modem SiP Module 20.7mm

21.8

mm

18.8±0.1mm

27.6

±0.1

mm

Top View



WLCSP for Dimension Reduction

SQN3221 1.0 mm

0.15 mm

PA

Shielding case

LPDDR

Cap PA

0.3 mm

0.1 mm

Total Height = 1.55 mm (Max.)

20.7mm

21

.8m

m

Shielding Can = 0.1mm

Clearance = 0.15mm

Component + Soldering = 1.0 mm

PCB = 0.3 mm

----------------------------------------------------------------

Total Height = 1.55 mm (Max.)



Comparison of Two SiP Module Structure: Single Side vs. Double Side

Lower Cost Lower Cost

Side View

Placement

Baseband

PA

LPDDR Cap

PA

0402

DDR Die SF Die

Inductor X’tal TCXO

0201

0201 RF Bumped Die

BB Bumped Die

RF

Front End

component SUS

Single Side HD SMT Double Side HD SMT

Low Z-height Smallest X-Y Lower Cost Lower Cost

Structure

Advantage



A Proposed IoT Module Architecture w/ Double Side

Item Height (mm)

Die Bond + Wire Bond Stacking Die 0.2

Clearance 0.1

T1 (Bottom Side Height) Ball 0.43

T2 (SUS_M) BT, 8L,

anylayer 0.435(MAX)

TOP Side Component 0.9

space between component

& shielding 0.1

Shielding can thickness 0.15

H 2.015 mm

Extreme small in X-Y

Consistent Baseband

Flexible on RF variants

14 14

T2 mm

T1 mm

1.15mm H mm

0402

DDR Die

SF Die

Inductor X’tal TCXO

0201

0201 RF Bumped Die

BB Bumped Die

RF

Front End

component

SUS



Heterogeneous SiP Module Co-design Capability

15



EE/RF Design Services

Schematics Design

• Platform Evaluation

• Circuit design

• Component selection

• Power consumption

Substrate Layout

• Dimension evaluation

• Placement

• PCB stack-up

• Trace Routing

• DFM

Simulation

• PI

• SI

• Thermal

• Warpage

• Circuit & SiP Level Simulation, behavior prediction

System Validation

• EVB design

• Fixture design

• Signal quality

• Power rail

• RF calibration & Test, compensate component/substrate variety

Pre-Certification

• Program management

• Pre-scan

• Lab execution

• Documentation

• Carrier certification support

• RF performance optimization



Case Study: Mutual K by Close Lump L

17

C3

L3

Larger the K factor in simulation:

1. Attenuation at 1~2.2GHz is getting worse

2. Notch @832MHz shift to lower frequency

Spacing (L1, L4): 4.2mil

Mutual inductance

by 4.2mil spacing is

serious in this case.

Simulation with K=0.005 between L1 & L4

Measurement (affects by mutual inductance)

Simulation without K



Case Study: Open-terminal Simulation for FA

18

Pin3 Disconnect

Parasitic effect fitting in Pin 3

vcc

Cp

Simulation Measurement



Co-design for

Optimization

System

IC Package

Co-Design with Package Designer, IC Designer

Die pad information

XY location

Net list Package type Original BGA BGA aQFN

Layer 4L (1+2+1) 2L 1L

Package size 6x6.5mm 6x6.5mm 9x9mm

Total thickness 1.2mm 1.1mm 0.85mm

Mold thickness 0.54mm 0.54mm 0.675mm

SBS thickness 0.26mm 0.21mm 0.125mm

Lead/IO count 132 IO 132 IO 134 IO

Ball size 0.25mm 0.25mm N/A

Ball pitch 0.5mm 0.5mm 0.5mm

Wire DIA. 0.8 mil (Cu wire) 0.8 mil (Cu wire) 0.8 mil (Cu wire)

Finger pitch 0.09mm 0.09mm NA

Trace pitch 0.08mm 0.08mm NA

Special process

TOP: Ni/Au

Bottom: Cu

MSAP, 1+2+1

TOP: Ni/Au

Bottom: Cu

MSAP

TOP: PPF

Bottom: PPF

D/B material Epoxy Epoxy Epoxy

RemarkNetlist follow

customerNetlist free assign Netlist free assign

Ball out

Cost comparison High Midle Low

Package proposal

rough cost evaluation

Impedance

Control Crosstalk

Analysis Timing

Analysis

Eye

Diagram

Driver

Strength

Design

Module size evaluation

Module cost evaluation

Warpage, Thermal, SI/PI simulation

19



Role of Software in SiP Design Flow

Signal Function System Certification

Manufacture

Station in Factory – FW download

– Baseband test

[Testing and Verification] GPIO pin: high/low

Control/data bus: signal/clock timing

Power circuit: voltage/current

Station in Factory – RF calibration/ verification – Function test (FCT)

[Testing and Verification ] Cellular (2G/3G/LTE) Connectivity ( Wifi,

Bluetooth, … etc.) Sensor, audio,

multimedia, … etc.

System Optimization/ Stabilization

– Function Stress ( Voice call , Data transmission, … etc.)

– System Stress ( Repeat on/off , Long-cycle operation, ... etc.)

– Power Optimization ( Standby, continuous operation, … etc.)

Certification of SiP Module – CE/FCC/IC

– GCF, PTCRB

– WHQL, WIFI

– Carrier certification (Verizon, AT&T, … etc.)

[Service] Pre-scan

Documentation

Lab execution/debugging

Supporting Services



Define FA Process Flow (General SiP Testing in Factory)

NPI-FA Management in SiP

SMT Underfil Pre-Mold

Panel Test Pre-Burn Molding

FA

Post-Mold

Panel Test

CPS De-panel CFS SiP

BB Test SiP

RF Test

SiP

Burn in IMEI

Fail Sample

Process Test

21

Frontend Process

System functional test

Backend Process



22

Test Fixture for Panel level test

Panel Level:

Power

Analog interface

Others

EVB

PC Test

Instrument



Pin1 Pin2 Pin3

NPI – FA Capabilities

23

•Scope & Multi-meter check impedance & signal

•TDR check variation b/w impedance & trace length

•Simulate performance decrease root cause

•AOI/x-ray/CT/SAT/CSA

•Scope check signal timing

•Multi-meter check impedance & voltage level

•RF Test Box check RF performance

•Shielding effect of fixture

•Contact between SiP & EVB

•Connection between EVB & Fixture

•Software test tool issue

FA for Testing

FA for Electrical

FA for Component

Defect

FA for Process



Configuration of Rework Machines

24



Conclusion

New Generation of Consumer Electronics for Smartphone and Beyond Smartphone Calles for High Density SiP Integration

Heterogeneous SiP Module Integration Requires Close Working Relationship Between IC House and OSAT

D4M, Test Development, and FA are Crucial for the High Density SiP Module to Achieve Low Cost and Time to Market

Generators of such High Density, Heterogeneous SiP Module are being Developed in the Industries Using This New Working Relationship

ASE Confidential / Security-C ASE Confidential / Security-C 26

Thank You

www.aseglobal.com