Transcript
Page 1: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

DEPFET,a vertex detector for the

ILC• DEPFET Principle• Basic system• Ladder proposal• ILC demands• Testbeam performance• Device simulation• Summary & Outlook

J.J. Velthuis for the DEPFET collaboration

Page 2: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

DEPFET Principle

• Monolithic Active Pixel detector• A p-FET transistor is integrated in every pixel.• By sidewards depletion potential minimum created below

internal gate.• Electrons, collected at internal gate, modulate transistor current

~1µm

p+

p+ n+

rear contact

drain bulksource

p

sym

met

ry a

xis

n+

ninternal gate

top gate clear

n -

n+p+

--

++

++

- 50

µm

------

MIP

Page 3: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

DEPFET Principle

• Advantages:– Fast signal collection due to fully depleted bulk– Low noise due to small capacitance and

amplification in pixel– Transistor can be switched off by external gate

– charge collection is then still active !– Non-destructive readout

• Disadvantages:– Need to clear internal gate. – Need steering chips.

Page 4: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Basic system

• Select and Clear signals provided by SWITCHER – 64 x 2 outputs– Max ΔV = 25V

• Read out row-wise: CURO– current based read out– 128 channels– CDS – real time hit finding

& zero-suppression– row rate up to 24 MHz

• DEPFET matrix parameters are being optimized– Various pixel sizes– Various doping profiles

n x mpixel

IDRAIN

DEPFET- matrix

VGATE, OFF

off

off

on

off

VGATE, ON

gate

drain VCLEAR, OFF

off

off

reset

off

VCLEAR, ON

reset

output

0 suppression

VCLEAR-Control

Gate Switche

r

ClearSwitche

r

Current Readout CUROII

DEPFET Matrix64x128 pixels, 36 x

28.5µm2

Page 5: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

ILC requirements

• Time structure: 1 train of 2820 crossings in ~1 ms every ~200ms– Hit density: for r = 15 mm: ~ 100 tracks / mm2 / train– Plan to read out 20x during train

• Row readout rate: > 20 MHz • Turn off in between to save power

– Occupany < 0.5 %• Radiation length: ~0.1% X0 per layer

– thinned sensors (50 μm) – low power consumption -> no active cooling

• Radiation tolerance: 200 krad (for 5 years operation)

• Resolution: few µm ( pixel size ≤ 25 x 25 µm2)• Impact parameter resolution a<5µm && b<10µm

Page 6: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Ladder proposal

• Modules have active area ~13 x 100 mm2

• Read out on both sides.

• Detectors 50µm thick, with 300µm thick frame yields 0.11% X0

• SWITCHER & CURO chips connected by bump bonding

SWITCHER

CURO

Page 7: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

ILC Power• Challenge: no active cooling• Measured Power Dissipation:

– Switcher: 6.3 mW per active channel at 50MHz– CURO: 2.8 mW / channel

• Assumed Power Dissipation of DEPFET Sensor:– 0.5 mW per active pixel– duty cycle: 1/200

• Only active pixel dissipate power– 1024 active pixels per module– 8 modules in Layer 1 => 8192 active pixels

• Expected Power Dissipation in Layer 1– Sensor: 8192 x 0.5 mW / 200 = 20 mW– Switcher: 16 x 6.3 mW / 200 = 0.5 mW– Curo: 8192 x 2.8 mW / 200 = 114 mW

• For Layer 1 Sum: 135 mW

For 5 Layer DEPFET Vertex Detector: Total ~ 3.6 W no active cooling

(note Bill Cooper@ILC workshop Ringberg:Can remove up to 80W using gasflow)

Page 8: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Thinning

sensor wafer

handle wafer

1. implant backside on sensor wafer

2. bond wafers with SiO2 in between

3. thin sensor side to desired thick.

4. process DEPFETs on top side

5. etch backside up to oxide/implant

first ‘dummy’ samples:50µm silicon with 350µm frame

thinned diode structures:leakage current: <1nA /cm2

Thinning technology for active area established

Currently with 150mm wafers at BSOI at TraciT, Grenoble

• Challenge: 50µm thick detectors

Page 9: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Radiation hardness

• Challenge: rad. hard up to 200 krad• Irradiations with 60Co and X-rays (~17keV) up to ~1Mrad

(SiO2) • Threshold shift of the MOSFET (~4V) can be compensated

by bias voltage shift

60Co

Page 10: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Zero suppression

• CURO (readout chip) has a 0-suppression feature

• Have used it in August testbeam. Analysis in progress…

It works!!

Test columnsinject current

Page 11: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Testbeam

• DESY test beam with 6 GeV e- • Bonn ATLAS telescope system:

– double sided strip detectors– pitch 50 µm (no intermediate strips)– readout rate 4.5 kHz (telescope only)

• DUT: 450µm thick DEPFET with CCG and HE– Row rate 2.5 MHz (no 0-suppression)

DEPFET

beam

1 2 3 4Scintillator Scintillator3 x 3 mm²

Page 12: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Pedestal & Noise

• Pedestal calculated as average signal after hit removal• Noise is σ of signal distribution after pedestal & common mode

subtraction & hit removal• Some pixels are blocked because they are:

– Very noisy– Strange pedestal– Hot

Page 13: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Clustering

• Look for hits:– pixel with largest signal

&& >5σ– Add neighbors with signal

≥2σ in maximum area

• Clusters mostly confined to 3x3

• S/N=112.0±0.3

Size Signal

3x3 1835±4

5x5 1854±4

7x7 1873±4

Page 14: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Position resolution

• Using CoG:– σX=8.7±0.1µm

σY=7.0±0.1µm

• Using η:– σX=8.1±0.1µm

σY=7.1±0.1µm pixel size=36x22µm

• Note in Y η worse than CoG– Remaining crosstalk in Y

direction. Still under study….

• Numbers still include uncertainty in predicted position (6 GeV particles)

Page 15: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Multiple Scattering

• From GEANT simulation, found √(σ2int+σ2

MS)=6.94µm

• Uncertainty not well known, but point is σ≤5µm. High energy testbeam ended Sept 3rd; analysis in progress

XCoGcorr YCoG

corr Xηcorr Yη

corr

5.2 0.9 4.2 1.5

Page 16: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Efficiency

• Look for clusters in ROI of predicted position ±2 pixels– Efficiency @ 5σ=99.75%

• Some hits at “wrong location” – due to multiple scattering ?

• Applying very modest χ2-cut– Efficiency @ 5σ=99.96%

Seed outside ROI

Page 17: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Purity

• Good cluster has a residual in both X and Y better than 30µm

• Bad clusters are number of clusters found in the background.

• Still, using seed cut 7σ purity & efficieny ≈100%– Note: MPV seed around

60σ

Page 18: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

New devices

• 2 Large chips in next production– Final ILC 512x4096

• Large area device– 512 x 512 matrix– Pixel size: 32x24µm²– array size: 16.38x12.29 mm² – Chip size: 21x18mm²

• Long ½ ladder size– 128 x 2048 matrix– pixel size: 24 x 24 µm²– array size: 3.07 x 49.15 mm² – chip size: 8.5 x 56 mm²

Page 19: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Performance of a DEPFET vertex detector at ILC

• Huge study simulating physics events using DEPFET vertex detector

• Here results with 450µm thick detector and 230e- noise:

• Correspondence is excellent!!

Page 20: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Simulation

• DEPFET implemented in MOKKA (GEANT4-ILC package)

• Digitization in Marlin:– Landau fluctuations– Charge transport, sharing

& diffusion– Lorentz shift (33º@4T)– Electronic noise (100 e- for

ILC, 230e- TB comparison)

• IP resolution very good! (demands: a<5µm b<10µm)

Page 21: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Summary

• DEPFET good candidate for ILC vertex detector. • Project is in full swing. Meets already demands on

– Radiation length (0.11 X0)– Radiation hardness (ΔVth shift~4V@1Mrad)– Power consumption (<5W full detector)– Zero suppression feature works– Position resolution (≲5µm)

• For a 450µm thick detector S/N=112.0±0.3• Efficiency & Purity ~100% at 7σ

• DEPFET vertex detector implemented in MOKKA– Correspondence between testbeam and simulation is

excellent!– DEPFET ILC proposal yields a very good IP resolution

• a=2.4µm and b=7.0µm at 3T

• Need to improve S/N and readout speed– S/N „easy“: DEPFET transistor ⇒ improve W/L

Page 22: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Outlook

• Currently analysing high energy testbeam data:– Detailed charge collection study– Quantatively test zero suppression– Precise resolution measurement

• Build large matrices (currently in production)– Also still developing in parallel different types of DEPFETs

• Further development of the readout chips ongoing– New SWITCHER chips are submitted. Expected early

December (0.35µm CMOS)– New CUROs are being designed

• Implement transimpedence amplifier• Implement ADC• Implement neighbor logic for 0-suppression

GOAL:Produce full scale prototype

ladder by 2010

Page 23: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Position resolution CoG

• Centre-of-Gravity assumes linear charge sharing

• σX=8.7±0.1µm σY=7.0±0.1µm pixel size=36x22µm

• Numbers still include uncertainty on predicted position

i

iiCoG Q

xQx 2

2

22

CoGiCoG xxS

N

Page 24: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

algorithm

• Writing CoG for 2 “strips”

• Linear charge sharing flat, but in real life is not.

• Reconstruct position:

leftrightleft

leftleftstrip x

QQ

Qxx2

0

0

0

0

1

Fxdd

dN

Nxx left

ev

evleft

Page 25: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Readout speed

Currently

0-supp ILC

Readout row (sample – clear –sample)

400 ns 400 ns 40 ns

Data-Transfer CURO DAQ-board

12.8 µs ~200 ns

Read out matrix (64 rows) 855 µs ~12 µs 2.6 µs

Noise 230 e- 100 e-• Still need to improve the readout speed

Page 26: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Clearing

• CURO measures: Isig,i+Iped,i & Iped,i+1

• Need to remove all charge such that Iped,i+1=Iped,i

• COMPLETE CLEAR @ Vclear=18V! Far too high for radiation hard technology

Clear completeAll charge removed

Page 27: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

HighE vs non-HighE

• HighE extra n-type implant– Moves internal gate

deeper into bulk– Clearing takes places

deeper in the bulk– Lower signals, but

easier clearing

clear

Internal gate

channel

Optional HighE implant

Page 28: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Clearing

• CURO measures: Isig,i+Iped,i & Iped,i+1

• Need to remove all charge such that Iped,i+1=Iped,i

• COMPLETE CLEAR possible for HighE with low voltages (~7V)⇒ possible to make radhard SWITCHER in standard CMOS

HighE

Page 29: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

DEPFET for Near Detector

• DEPFET advantages:– Fully active thickness of 450 µm– Tracking inside device – Event rate no problem (~5 Hz

pro plane)– Pixel size ok (IP τ≈60µm)

• Challenges:– 18 planes of 0.5x0.5 m2

– Need larger matrices ?– Mechanics (but no low mass

requirement)

Page 30: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Comparison with ILC

ILC Near Detector

Area ~0.3 m2 4.5 m2

Thickness 50 µm 450 µm

Signal (gain) x 4-6 Ok

Speed x 20 Ok

Zero suppression

vital not needed

Mechanics Low mass

High mass ok

Matrix size x 2 ??

Page 31: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Author list

Univ. of Bonn: M.Karagounis, R.Kohrs, H.Krüger, M. Mathes, L.Reuen, C.Sandow, E.von Törne, M.Trimpl,

J.Velthuis, N.Wermes

Univ. of Mannheim: P.Fischer, F.Giesen, I.Peric

Politecnico di Milano:M. Porro

MPI Halbleiterlabor Munich:O Hälker, S. Herrmann, L.Andricek, G.Lutz, H.G. Moser, R.H.Richter, M.Schnecke, L.Strüder,

J.Treis, P.Lechner, S. Wölfel

THCA of Tsinghua Univ.:C. Zhang, S.N. Zhang

Page 32: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

DEPMOS Technology

• DEPMOS pixel array cuts through one cell

Along the channel Perpendicular to the channel

Metal 2

Metal 1

Oxyd Poly 2

Metal 2

Metal 1

Poly 2

Clear Gclear Channnel

pDeep n

n+Deep p

Poly 1

Double poly / double aluminum process on high ohmic n- substrate

Low leakage current level: < 200pA/cm² (fully depleted – 450µm)

Page 33: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Readout

• Readout current based: 1) SWITCHERs turn on a

row using an external Gate

2) CURO measures Signal+Pedestal current

3) Signal charge removed4) CURO measures

Pedestal current

• CDS in CURO chip

GATE-SWITCHER

CLEAR-SWITCHER

CURO

64x128DEPFETMatrix

time

GATESWITCHER

CLEARSWITCHER

SAMPLECURO

2 3 41

Page 34: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Excellent noise

• Single pixel device • 10 µs shaping• Room

temperature (22° C)

Page 35: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Excellent noise

• Large structure (64x64):– 75 x 75 µm2 pixel size – 45 µm gate circumference

/ 5 µm gate length– Drain in center of pixel– Cut gate geometry– Curved edge– Double metal

• Operated at:– Pixel current 30 µA– Line processing time 25 µs

0 1 2 3 4 5 6 71

10

100

1000

10000

Si-KAl-K

Mn-KMn-K

Cou

nts

Energy (keV)

Escape Peak

Energy resolution: 126 eV FWHM @ Mn-Ka Line

corresponding to 4.9 e- ENC

-60 -40 -20 0 20

10

20

30

40

50

60

70

2.78

5.56

8.33

11.11

13.89

16.67

19.44

Normal cycles (tInt

= 3 ms)

Reference cycles (tInt

= 5 s)

Pix

el r

ea

do

ut n

ois

e (

e-

EN

C)

Pix

el r

ea

do

ut n

ois

e (

eV

)

Temperature (°C)

Noise dependence

Pixel readout noise: 63 – 14eV (17 – 3.6 e- ENC)

Page 36: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

WIMS

• Wide-band Imaging and Multi-band Spectrometer (WIMS) is part of China’s spacelab mission .

• Observe high-energy bursts, transients and fast-varying sources over a broad spectral range simultaneously

• Using Macro pixels– Pixel size 0.5x0.5 mm2

– “Si-drift chamber readout using DEPFET”

0 1000 2000 3000 4000 5000 6000 70000

100

200

300

400

500

600

700

800

FWHM = 209 eV

ENC = 19.1 el r.m.s

Room temperatureBack side illuminates, fast drain readoutShaping time: 3μsClear pulse period 1 ms with width 3 μs

Page 37: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Switcher und CUROSteuer-ASIC SWITCHER II:• 0.8µm AMS HV Technologie• Maximaler Spannungshub: 25 V• Leistungsaufnahme:

1mW/Kanal @ 30MHz• 2x64 Kanäle mit internem Sequenzer

1 0 1 1

U = 20V = 30 MHz

20ns

20V !

Switching 20V @ 30MHz

Auslese-ASIC CURO II:• 0.25µm CMOS Technologie• 128 Kanal Stromauslesechip• Pedestalstrom-Korrektur (CDS)• Trefferidentifikation und Null-Unterdrückung• Trefferzwischenspeicher• Leistungsaufnahme:

2.5mW/Kanal @ 20MHz• Rauschen 43±1 nA

cascode currentbuffer A

currentbuffer B

Hit-Finder

HIT-RAM

storage:

Iped + Isig

currentcompare

serial-out

1/0

hit-address

analog

FIFO

cells

(Iped + Isig) or Iped

IsigIsig

channel i

outA

outB

DIGITAL - Part

ANALOG - Channel

Output MUX

Mixed Signal FIFO

Page 38: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

SWITCHER

• Steering-ASIC SWITCHER II:

• 0.8µm AMS HV Technology• Maximum Voltage swing:

25 V• Power dissipation:

1mW/Channel @ 30MHz• 2x64 channels with

internal sequencer

1 0 1 1

U = 20V = 30 MHz

20ns

20V !

Page 39: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Readout

- Read filled cells of a row- Clear the internal gates of the row - Read empty cells

Low power consumption

Fast random access to specific array regions

Page 40: DEPFET, a vertex detector for the ILC

Jaap Velthuis, Bonn University

Thinning

• Material (Top and Handle): 150mm, FZ, ≈130 Ohm.cm

• Oxidation 230 nm• Full sheet P-implant back side

top wafer

• Engineered BSOI at TraciT, Grenoble:

• Wafer Bonding • Annealing 1050 degC, 4h• Grinding, CMP: 50 μm top wafer • Edge treatment, polishing Top

and Handle wafer

p+

Aln+

SiO2

structured p+ on topunstructured n+ in bond

region

Simplified standard technology

guard ring


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