Digital Control of dc-dc Boost Converters with Inductor Current Estimation

P. Mattavelli DIEGM, University of Udine

Udine, Italy mattavelli@uniud.it

Abstract— This paper investigates a digital control of dc-dc boost converter operating in Continuous-Conduction Mode (CCM) sensing only the output voltage and possibly the input voltage. In order to improve the dynamic performance compared to voltage mode control, the inductor current is estimated and used for the implementation of an internal sensorless current loop. Different solutions, either based on the prediction of inductor current variations or on state observers, are discussed, showing that the sensorless current mode control gives some advantages only if input voltage feedforward is used. The digital control has been implemented in a Field Programmable Gate Array (FPGA) using a hardware description language (VHDL), providing flexibility and technology independence. Experimental results on a 100 W dc-dc boost converter confirm the properties and limitations of the proposed approach.

Keywords: digital control, dc-dc converters, sensorless control

I. INTRODUCTION Recent research activities [1,2] have shown the feasibility

and advantages of using digital controller ICs specifically developed for high-frequency switching converters, highlighting a challenging future trend in Switched-Mode Power Supplies (SMPS) applications. In fact, up to a few years ago, the application of digital control for SMPS was unpractical due to the high cost and low performance of DSP and microcontroller systems even if the advantages that digital controllers offer, such as the immunity to analog component variations, the ability to implement sophisticated control schemes and system diagnostics, were well known. Moreover, digital controller ICs potentially offer other advantages from the integrated design point of view, such as faster design process, ease of integration with other digital systems, lower silicon area and power consumption than standard analog ICs.

The investigation of digital control techniques for dc-dc converters is not new and several works are available up to now [1-12]. Main research activities have been focused on the analysis of typical digital implementation issues, such as sampling effects, dynamic characteristics of the closed-loop system using sample-data models, rounding and quantization effects, etc. . Deadbeat control for dc-dc converters has been also investigated in [10], where the current error is reduced to zero in a finite number of sampling periods. Moreover, digital control has been used for the implementation of sophisticated control techniques [11] and adaptive control [12].

Multi-loop control for dc-dc converters using an internal current-mode control is usually considered superior to voltage mode control, due to overcurrent protection capability, better

input voltage rejection and increased stability margin ensured by the fast inner current loop. This latter feature is particularly evident for dc-dc converters having a right-half-plane zero in the transfer function between duty-cycle and output voltage. However, the use of a digital current-mode controller requires the sensing of the switch or inductor current and thus an additional dedicated signal conditioning circuit and/or A/D converter. Sensorless current mode controllers, which use an internal current loop based on the estimated inductor current, have been proposed [13], but mainly in the analog domain. The direct translation in the digital domain is not straightforward since they usually require the instantaneous reconstruction of the inductor current waveform. Finally, an estimation of the load current in a digitally controlled dc-dc converter has been proposed in [14] for the identification of the boundary between DCM and CCM.

This paper investigates the use of a simple estimation algorithm of the inductor current variations for dc-dc boost converters operating in CCM. The main goal is to achieve a dynamic performance comparable to that obtainable with conventional multi-loop control even without the measurement of the inductor current. Instead, since only inductor current variations are estimated, overcurrent protection capability is not available, as in any voltage-mode controller, so that an additional protection circuit is needed. Using an equivalency with voltage-mode controller, the proposed investigation shows that the effective advantages of the digital sensorless current control can be obtained only if the input voltage feedforward is used. The proposed control law can be applied in any second-order system (buck, boost and buck-boost). A boost prototype has been realized using a FPGA for the digital control implementation. An analog controller with peak current mode control has been designed for the same converter and compared with the digital solution highlighting properties and limitations of the proposed approach.

II. PROPOSED CONTROL METHOD

A. System model Fig. 1 shows the basic scheme of a dc-dc boost converter

with the proposed control, where the voltage loop determines a reference ∆iLref for the internal current loop. Inductor current sensing is avoided and its variation ∆iL is estimated using the measurement of the output voltage vO, the complement of the duty cycle δ’ (δ’=1 - δ), and possibly the input voltage vin. According to the state space averaging method [15-16] and

assuming CCM operation, the average system dynamic behavior is described by the following equations

)t(i)t(i)t()t(v

dtdC

)t(v)t()t(v)t(idtdL

oL'

o

o'

inL

−⋅δ=

⋅δ−= (1)

where input voltage vin and output current io are considered as external disturbances. Under small-signal assumptions, we can derive the following small-signal model [15-16]

)t(i)t(i'DI)t()t(v

dtdC

)t(v'DV)t()t(v)t(idtdL

oLL'

o

oo'

inL

∆−∆+⋅δ∆=∆

∆−δ∆−∆=∆ (2)

where symbol “∆” means perturbation around a steady state working point (i.e. x(t)=X+∆x(t), being X the steady-state point and ∆x(t) the small-signal perturbation).

Assuming that the input voltage vin(t), the output current io(t) and the duty-cycle δ(t) are constant between sampling instants (zero-order-hold sampling of the system), the discrete time dynamic equations can be written as:

)k(u)k(')k(x)1k(x d21 ∆Γ+δ∆Γ+∆Φ=+∆ (3)

where [ ]ToL )k(v)k(i)k(x ∆∆=∆ , [ ]Toind )k(i)k(v)k(u ∆∆=∆ and matrixes Φ , 1Γ , 2Γ are given by:

( ) ( )

( ) ( )

ωωω

ωω

−ω=Φ

swoswoo

swoo

swo

TcosTsinC'D

TsinL'DTcos

(4.a)

( ) ( )( )

( )( ) ( )

ωω

+ω−−

ω−−ωω

−=Γ

swoo

Lswo

o

swoL

swoo

o

1Tsin

CITcos1

'DV

Tcos1'D

ITsin

LV

(4.b)

( ) ( )

( ) ( )

ωω

−ω−

ω−ωω=Γ

swoo

swo

swoswo

o2

TsinC

1'D

Tcos1'D

Tcos1TsinL

1

(4.c)

In (4), Tsw is the sampling period and CL'Do =ω is the angular resonance frequency of the second order system. Under the assumption that the sampling frequency swsw T1f = is much greater than the open-loop resonance frequency of the boost converter (i.e. 1Tswo <<ω ), (3-4) can be approximated as:

[ ]'D)k(vV)k(')k(vL

T)k(i)1k(i ooin

swLL ∆−δ∆−∆+∆≅+∆ (5.a)

[ ])k(i'D)k(iI)k('C

T)k(v)1k(v oLL

swoo ∆−∆+δ∆+∆≅+∆ (5.b)

B. Prediction of inductor current variations In CCM operation only variations of the inductor current

can be estimated, since the actual inductor current is not observable in CCM steady-state conditions using only input and output voltage measurements unless resistive parasitics are considered. Let us first consider the case where input voltage vin is not sensed.

Estimation of ∆iL can be evaluated using an observer on (4) or (5). The simplest algorithm is based on the inductor current prediction based on the integration of the inductor voltage perturbation, either using (4) or (5.a). Thus,

[ ]'D)k(vV)k(')k(ia)1k(i ooLcL ∆+δ∆β−∆=+∆ (6)

where )Tcos(a swoc ω= , )L(a os ω=β , being )Tsin(a swos ω= . Algorithm (6) has been obtained using the

first row of (4.a) and (4.b) and setting the steady-state inductor value IL equal to zero, since its contribution is negligible as shown in (4.b). Similarly, (6) can be obtained from the approximated (5.a).

The multi-loop control based on the following estimation scheme is reported in Fig. 2. For the current loop regulator, only a proportional gain kPi is used since tracking of the dc component is not needed. Moreover, if the coefficient kPi is properly designed, then a dead-beat type current control with one-cycle response can be achieved as long as the computational delay is negligible compared to the switching period. Inspection of the scheme of Fig. 2 indicates that the algorithm is not very sensitive on parameter variations since any possible error on the magnitude of the inductor current is reflected on loop gain variations on the current and voltage loop bandwidth, so that relatively high estimation errors can be easily managed if control gains are properly designed. From the implementation point of view, the contribution associated

L

+

v-o

D ioioiLiL

+

-

v inv in

currentloop regulator

AD

vorefvoltage

loop regulator

DPWM

+

_

driver

vovo

∆i L

δestimation of

iL perturbations

vovo

+_

∆i Lref

δ’AD

’

C

(optional)v inv in

Fig. 1 – Fully digital control of dc-dc boost converter with inductor current estimation.

to the voltage error ∆vO(k) in (6) can be moved within the voltage loop controller, possibly simplifying control calculations, as described in section II.D.

In order to highlight the properties of the current control with the estimated inductor current, the transfer function between ∆iLref and vo has been reported in Fig. 3 using (a) the inductor current measurement and (b) the estimation scheme of Fig. 2. The converter parameters are given in Table I and correspond to those used for the converter prototype. Fig. 3 shows that there are only small differences between the two approaches in the frequency range closed to the voltage loop bandwidth, since they have almost the same phase and small differences in magnitude. At the same time, however, Fig. 3 shows a significant decrease of the magnitude at lower frequencies, which may affect output voltage tracking in the low-frequency range. This problem can be justified from the fact that (6) is practically an integral action on the perturbed inductance voltage and any dc error between the output voltage and its reference or between the duty-cycle and its nominal value (usually only roughly known and dependent on input voltage) leads to an linearly increasing estimation of inductor current. Thus, a PI-type voltage loop control does not ensure a zero steady-state error if its output, i.e. the inductance current reference ∆iLref, is linearly increasing. Although (6) is not a pure integrator (since ac<1) and thus steady-state errors on the output voltage do not appear, some provisions may be needed in order to improve system performance, either limiting the current estimation in the high-frequency range, thus increasing the low-frequency gain of the transfer function between ∆iLref(z) and vo(z), or introducing an input voltage feedforward.

The former solution can be implemented reducing the dc-gain of (6), thus reducing coefficient ac as follows:

[ ]'D)k(vV)k(')k(ia)1k(i ooLcL ∆+δ∆β−∆=+∆ α (7)

where αca ( cc aa <α ) determines the cutoff frequency of the

current loop estimator. The effect of this provision is reported in the trace (c) of Fig. 3, showing an increased low-frequency gain at the expense of a small phase reduction.

-15

-10

-5

0

5

10

Mag

nitu

de

(dB

)

103

104

105

106

-270

-225

-180

-135

-90

-45

0

Pha

se

(d

eg

)

Bode Diagram

Frequency (rad/sec)

(a)

(a)

(c)

(c)

(b)

(b)

Nyquistfrequency

Fig. 3 – Transfer function between ∆iLref(z) and vo(z) with (a) inductor current measurement, (b) inductor current estimation using (6) and (c) inductor current estimation using (7) with 02.0aa cc −=α .

C. Input voltage feedforward In order to improve dynamic performance in presence of

input voltage variations and to provide a more precise control of the set-point for (6-7), a better solution is to introduce the input voltage in the estimation algorithm. When the input voltage vin is sensed, the estimation algorithms (6-7) can be modified as:

)]k(v'DV)k(')k(v[)k(ia)1k(i ooinLcL ∆−δ−β+∆=+∆ (8)

At the same time, the steady-state duty-cycle D’ in (8) should be evaluated as orefin V/)k(v'D = , although its contribution due to the input voltage variations is usually quite small and practically negligible in our test-case. Using input voltage feedforward, a better rejection of input voltage and output voltage variations is introduced, as depicted in Fig. 4, which reports the closed-loop audiosusceptibility using (a) inductor current sensing, (b) inductor current estimation without input voltage feedforward and (c) inductor current estimation with input voltage feedforward. Fig. 4 shows the improvement obtainable with the input voltage feedforward, which gives some advantages even over the case of current-mode sensing. Indeed, since the input current variations due to the input voltage variations are delayed by the integration process, we can reject the disturbance one-step ahead since the cause of current variations, i.e. the input voltage, is already available within the controller.

∆iL (z)∆iL (z)^

_

+D’

gate signalDPWM

∆iLref (z)∆iLref (z) _

+kPi

vo(z)vo(z)Vorefβ

z−acβ

z−ac

_ +δ‘(z)Voref

D’

__

Estimation of inductor current variations

kPv++

_

z−1

+Voref

current loopvoltage loop

vo(z)

δ‘(z)

+

kIv

Fig. 2 – Multiloop control with estimation of inductor current variations.

103

104

105

106

-50

-40

-30

-20

-10

0

10M

agn

itud

e (

dB)

Bode Diagram

Frequency (rad/sec)

(a)

(c)

(b)

Fig. 4 – Converter audiosusceptibility with (a) inductor current measurement, (b) inductor current estimation using (7) and (c) inductor current estimation with input voltage feedforward (voltage loop bandwidth = 12 kHz).

D. Equivalency with voltage mode controller Some of the properties and limitations of the scheme

reported in Fig. 2 can be analysed rearranging the control block diagram in an equivalent voltage mode control. Indeed, any linear control scheme, which is based on the measurement of only the output voltage, can be rearranged in a voltage mode configuration with an equivalent transfer function between the output voltage error and the duty-cycle. Using simple block manipulations, the scheme of Fig. 2 can be replaced with the equivalent block diagram reported in Fig. 5. Inspection of Fig. 5 shows that the transfer function between the complement of duty cycle δ’ and the modified reference ∆iLrefm and is given by:

)Vka(z

)az(k)z('

)z(i

orefPic

cPiLrefmβ−−

−−=

δ∆

(9)

which introduces a lead-lag action on the voltage loop and thus a stabilization network. However, since the zero is placed at low frequency, it decreases the low-frequency gain, confirming the previous analysis. Thus, in order to fully exploit the advantages of the sensorless control, the input voltage feedforward should be introduced since the same performance of the scheme without input voltage sensing can be achieved with an equivalent voltage mode controller. In the latter case, the proposed analysis gives only an additional insight on the design of the voltage loop regulator.

∆iLm (z)∆iLm (z)^

∆iLrefm (z)∆iLrefm (z) _

+kPi

β·Vorefz−ac

_

+D’

kPv++

_

z−1

+Voref

lead-lag actionmodified integral term

vo(z)

δ‘(z)+

kIv

z−ac

β·D’

+_

Fig. 5 – Control scheme equivalent to Fig. 2.

E. Inductor current estimation using state observer An approach alternative to (6) for the estimation of the

inductor current is based on the use of state observer on the small signal model (4). The state observer can be firstly written in its basic form:

))k(v)k(v(C)k(')k(x)1k(x oos1 −+δ∆Γ+∆Φ=+∆ (10)

where ToL ])k(v)k(i[)k(x ∆∆=∆ and [ ]T21s ccC = ,

being c1 and c2 the estimator gains. In (10) we have neglected the presence of input voltage variations, taking into account the case where the input voltage is not measured.

Solving (10) for )k(iL∆ gives the following estimation algorithm:

( ) 121

2oo1o1

Lcz1ccz

)z(v)bzb()z(')aza()z(i

−−++∆++δ∆+

=∆ (11)

where coefficients c1 and c2 determine the speed of response of the estimator and coefficients a1, a0, b1, and b0 depend on converter and estimator parameters c1 and c2, with small contribution from the unknown IL, which we have neglected. The main advantage of this approach is the possibility to estimate the exact inductor current deviation from its unknown steady-state point. The actual inductor current is still unknown, but the estimation process does not reduce the low-frequency gain, as in the previous case. This is confirmed also by Fig. 6, which reports the transfer function between ∆iLref and vo using (a) the inductor current measurement and (b) the estimation scheme using (6) and (c) the estimation scheme using (11) with a deadbeat estimator (c1=c2=0). High gain at low frequency is ensured at the expense of a lower phase. Of course, an improved behaviour is achievable by reducing the estimation response time. Even with an optimized estimator design, we were not able to find significant advantages compared to the simpler algorithm (6-7). Thus, the results obtained with this approach will not be reported hereafter due to space constrains.

-20

-10

0

10

20

30

40

Mag

nitu

de

(dB

)

103

104

105

106

-270

-225

-180

-135

-90

-45

0

Pha

se

(d

eg

)

Bode Diagram

Frequency (rad/sec )

(a)

(a)

(c)

(c)(b)

(b)

Fig. 6 – Transfer function between ∆iLref(z) and vo(z) with (a) inductor current measurement, (b) inductor current estimation using (6) and (c) inductor current estimation using (11) with c1=c2=0.

III. SIMULATION RESULTS The proposed algorithm has been initially tested by

simulation tools so as to verify the performed theoretical analysis. The converter parameter are reported in Table I and the voltage loop bandwidth has been designed to be equal to 12 kHz. In order to ensure a high-performance digital control, the control delays due to the sampling process and the calculation time need to be kept small compared to the switching period, so that the duty-cycle update can be done within the same switching period of the output voltage sampling. Without this provision, the estimation algorithm can be still applied, but the dynamic performance would have been strongly deteriorated by control delays.

Fig. 7 reports the load step variations with the inductor current sensing and Fig. 8 the results with the inductor current estimation in the same operating conditions. Note that the performance is quite similar, besides higher transients associated to the modified term α

ca in (7). If (6) is used, we found that there isn’t any significant difference from the case reported in Fig.7. In Fig. 8 we have also introduce a mismatch on the steady-state duty-cycle with an error of 5% (D’=0.55). We have also introduced other mismatches in the inductor and capacitor values, without noting significant problems. While the proposed system gives good performance in terms of load current variations, it does not ensure good rejection of input voltage variations. This is evident also from Fig. 9 which reports a step variation of the input voltage at full load from 24V to 28V. Note that input voltage rejection of the proposed solution (trace (b)) is very poor compared to current-mode control (trace (a)), while the introduction of the input voltage feedforward (trace (c)) strongly improves control performance.

0 0.2 0.4 0.6 0.8 146

47

48

49

50

[V]

[ms]

0 0.2 0.4 0.6 0.8 10

2

4

6

8

[A]

[ms]

vo

iL

Fig. 7 – Step load variations with inductor current measurement.

0 0.2 0.4 0.6 0.8 146

47

48

49

50

[V]

[ms]

0 0.2 0.4 0.6 0.8 10

2

4

6

8

[A]

[ms]

vo

iL

Fig. 8 – Step load variations with inductor current estimation.

0.15 0.2 0.25 0.3 0.35 0.447

47.5

48

48.5

49

49.5

50

50.5

51

51.5

52

[ms]

[V]

(a)

(b)

(c)

Fig. 9 – Step Input voltage variations from 24V to 28V with (a) inductor

current sensing, (b) inductor current estimation using (7), (c) inductor current estimation using input voltage feedforward.

IV. EXPERIMENTAL RESULTS The proposed controller has been tested on a boost

prototype whose converter parameters are reported in Table I. The digital control has been implemented using a Field Programmable Gate Array (FPGA) by Altera (specifically the EP1C6 device, a member of Cyclone family) and the control algorithm has been developed using a hardware description language (VHDL), providing flexibility and technology independence. Fast A/D converters have been used ensuring the conversion time to be slightly less than 1 µs. In our prototype the digital PWM has been organized as depicted in Fig. 10, where the sampling instant has been set after 300 ns of the switch turn-on. Taking into account 1 µs conversion time for the A/D converter and a few digital clock cycles for the FPGA calculations, the duty-cycle update δ(k) was obtained within the same sampling period k. This provision has reduced control delays in the feedback loop. During large-signal transient, a delay equal to one sampling period may appear, which does not affected the small signal behavior of the proposed controller.

PWM carrier

PWM Sync

PWM Sync

ADC conversion time FPGA control

Steady-stateturn-off

Duty-cycle updateSamplinginstant

Driver signal

Fig. 10 – PWM modulation strategy.

As far as the FPGA implementation is concerned, the estimated inductor current can reach higher values, depending on the effective parameter mismatch in the actual prototype. It was interesting to note, however, that we didn’t take any particular provision to handle the possible overflow of the inductor current, neither extending the number of bits of the internal representation nor introducing saturating actions. In fact, the two complements representation inherently handles the overflow.

Fig. 11 shows the converter behavior in presence of step load variations from 47 Ω to 23.5 Ω and viceversa. The response time is in good agreement with the simulation results and confirms the theoretical analysis. It has been verified that the use of inductor current sensing give results very similar to those reported in Fig. 11, showing the effectiveness of the sensorless control for rejecting load variations. In order to force the system to move to DCM operation, at least during transient conditions, the load has been reduced, imposing a step variations from 100 Ω to 32 Ω. The results, reported in Fig. 12, shows that during DCM operation the output voltage recovery becomes much slower due to the error introduced by the estimation scheme which assumes CCM operation. This clearly shows a limitation of the proposed scheme, which is unsuited for DCM operation and for any variable disturbance which is not modeled in (4), due to the reduced low-frequency voltage gain introduced by the estimation action.

For comparison, we have implemented an analog control with peak current mode control, having a voltage-loop bandwidth of 16 kHz and a switching frequency equal to 210 kHz. Fig. 13 shows the results obtained using the same conditions of Fig. 12. Note that the dynamic behavior under load step-up is quite similar, while much better results are obtained under load current step-down. Moreover, during step-up the undershoot is slightly smaller in the analog implementation due to the slightly higher voltage loop bandwidth. Note also that our digital implementation presents a non-negligible jitter which is due to the significant sampling noise of our prototype.

TABLE I. CONVERTER PARAMETERS

Input voltage Vin 24 V ±20%

Output voltage Vo 48 V

Inductance L 28 µH

Output capacitance 10 µF

Switching frequency 180 kHz

Nominal output power 100 W

vo

iL

io

Fig. 11 – Load step variations (47 Ω → 23.5 Ω → 47 Ω) with the proposed

solution (vO - 2V/div, iL - 2A/div, iO - 2A/div, time – 100 µs/div).

vo

iL

io

Fig. 12 – Load step variations (100 Ω → 32 Ω → 100 Ω) with the proposed

solution (vO - 2V/div, iL - 2A/div, iO - 2A/div, time – 100 µs/div).

vo

iL

io

Fig. 13 – Load step variations (100 Ω → 32 Ω → 100 Ω) with analog

controller (vO - 2V/div, iL - 2A/div, iO - 2A/div, time – 100 µs/div).

CONCLUSIONS This paper has discussed advantages and drawbacks of

digital sensorless current control for dc-dc boost converters operating in Continuous-Conduction Mode (CCM). A simple algorithm based on the prediction of inductor current variations, possibly using the input voltage sensing, is investigated, showing to be more convenient than state observer techniques. Using an equivalency with voltage mode controller, it is verified that the sensorless current mode control gives some advantages only if input voltage feedforward is used. Experimental results on a 100 W dc-dc boost converter controlled by a FPGA confirm the properties and limitations of the proposed approach.

ACKNOWLEDGMENTS The author thanks Dr. Marco Degano for his valuable

support in the experimental activity and in VHDL program development for FPGA. The author thanks also Altera for providing hardware support.

REFERENCES [1] B.J. Patella, A. Prodic, A. Zirger, D. Maksimovic, “High-frequency

digital controller IC for dc/dc converters”, IEEE Trans. on Power Electronics, Vol. 18, No. 1, January 2003, pp. 438-446.

[2] J. Xiao, A.V. Peterchev, S.R. Sanders, “Architecture and IC implementation of a digital VRM controller”, IEEE Trans. on Power Electronics, Vol. 18, No. 1, January 2003, pp. 356-364.

[3] F. Huliehel, S. Ben-Yaakov, “Low-frequency sampled-data models of switched mode DC-DC converters”, IEEE Transactions on Power Electronics, Vol. 6, No. 1, Jan. 1991, pp 55 -61.

[4] A. Prodic, D. Maksimovic, R.W. Erickson “Design and implementation of a digital PWM controller for a high-frequency switching dc-dc power converter”, IEEE IECON’01, 2001, pp. 893-898.

[5] F. Kurokawa, T. Sato, H. Matsuo, H. Eto, “Output characteristics of DC-DC converter with DSP control” 24th Annual International Telecommunications Energy Conference, 2002, (INTELEC’02), pp: 421 -426.

[6] C. Kranz, “Complete Digital Control Method for PWM dc-dc Boost Converter” IEEE Power Electronics Conference 2003 (PESC’03), Acapulco, Mexico, June 2003.

[7] A.V. Peterchev, S.R. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters”, IEEE Trans. on Power Electronics, Vol. 18, No. 1, January 2003, pp. 301-308.

[8] J. Chen, A. Prodic , R. W. Erickson and D. Maksimovic, “Predictive digital current programmed control,” IEEE Trans. on Power Electronics, Vol. 18, No. 1, pp. 441-419, January 2003.

[9] A.Prodic, D.Maksimovic, R. W. Erickson, "Digital controller chip set for isolated DC power supplies," IEEE Applied Power Electronics Conference, February 2003, pp. 866-872.

[10] S. Bibian, J. Hua, ”High performance predictive dead-beat digital controller for DC power supplies“ IEEE Transactions on Power Electronics, Vol. 17, no. 3, May 2002, pp. 420-427.

[11] T. Gupta, R.R. Boudreaux, R.M. Nelms, J.Y. Hung, “Implementation of a fuzzy controller for DC-DC converters using an inexpensive 8-b microcontroller”, IEEE Transactions on Industrial Electronics, Vol. 44, No. 5 , Oct. 1997, pp. 661 -669.

[12] A.J. Forsyth, I.K. Ellis, M. Moller, “Adaptive control of a high-frequency DC-DC converter by parameter scheduling” IEE Proceedings of Electric Power Applications, Vol. 146, No. 4, July 1999, pp: 447 -454.

[13] P. Midya, P.T. Krein, M. F. Greuel, “Sensorless current mode control-an observer-based technique for DC-DC converters”, IEEE Transactions on Power Electronics, Vol. 16, No. 4, July 2001 pp. 522 -526.

[14] A. Prodic, D. Maksimovic, “ Digital PWM Controller and current estimator for a low-power switching converter” in Proc. of 7th Workshop on Computers in Power Electronics, pp. 123-128, 2000.

[15] R. W. Erickson and D. Maksimovic, “Fundamentals of Power Electronics,” 2nd Edition, Kluwer Academic Publishers, 2001.

[16] J. G. Kassakian, M. F. Schlecht, G. C. Verghese, Principle of Power Electronics, Addison Wesley, 1991.