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Implementation Design Ideas

for

CMOS VLSI Practicals

MICROWIND. giving you the squeeze of nanometer based designs

By :ni logic Pvt. Ltd.,21/22, Bandal Dhankude Plaza,

Opp. PMT Depot, Paud oad, !oth"ud,Pune # $11 %&', (ndiaTele)*a+: -1 ) 2% ) 22' -$'in0oni2deign.co3444.ni2deign.co3

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5MO6 7L6( P"actical 8ing M(5O9(D 7&.1

Experiment 1: CMOS Inverter

Aim:To deign and i3ple3ent logic inve"te" uing MO6*;T.

!eor": The inve"te" i p"o


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La"o$t design $sing %&1'$m ec!nolog":

P!"sical La"o$t:(it! %&1f) load

Comments:= vi"tual capacito" o0 %.10* ha


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Voltage Vs C$rrent grap!

Comments:Ee"e 4e can o


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E"e Diagram of O*P Vs& I*p



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Sim$lation es$lts for %&1'$m:

Voltage*ime or ransient +,it! %&1p) load- and Po,er Cons$mption::



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ransfer c!aracteristics of inverter :+o.p voltage vs& i.p voltage-

Comments:9e can o


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La"o$t design $sing 23nm ec!nolog":

P!"sical La"o$t:(it! %&1f) load

Comments:= vi"tual capacito" o0 %.10* ha


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E"e Diagram of O*P Vs& I*p



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Sim$lation es$lts for 23 nm:

Voltage*ime or ransient +,it! %&1p) load- and Po,er Cons$mption:



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ransfer c!aracteristics of inverter :+o.p voltage vs& i.p voltage-

Comments:9e can o


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'D Vie,:

%&1' $m 23 nm



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Experiment ': CMOS 6A6D and 6O

Aim:To deign and i3ple3ent 5MO6 =D and O Logic gate.

!eor":=D and O a"e unive"al gate, any gate can 1@ give 0unction o0=D gate. (n 5MO6 deign, the =D gate conit o0 t4o MO6 in e"ie connected tot4o PMO6 in pa"allel. The che3atic diag"a3 o0 5MO6 =D gate i ho4n 1@, othe"4ie output i >%@, give 0unction o0O gate. (n 5MO6 deign, the O gate conit o0 t4o PMO6 in e"ie connected to t4oMO6 in pa"allel. The che3atic diag"a3 o0 5MO6 O gate i "epo"ted


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1


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P!"sical La"o$t:

La"o$t design $sing %&1'$m ec!nolog":

NAND Layout with capacitive load 0.01pf: NOR Layout with capacitive load 0.01pf:

Area /tili0ation for 6A6D: Area /tili0ation for 6O:9idth: $.$G3 HK& la3


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Sim$lation es$lts for 6A6D +%&1'$m ec!nolog"-:

Voltage*ime or ransient +,it! o$t load-:



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Voltage Vs C$rrent grap!s:

(it! O$t load:

Comments:ote the po4e" conu3ption.

(it! Load +%&%1 pf-:

Comments:ote the change in po4e" conu3ption.e0e" co3pa"ative ta


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E"e Diagram of O*P Vs& I*p:(it! O$t load:



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La"o$t design $sing 23nm ec!nolog":

NAND Layout with capacitive load 0.01pf: NOR Layout with capacitive load 0.01pf:

Area /tili0ation for 6A6D: Area /tili0ation for 6O:9idth: 2.KG3 HK la3


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Sim$lation es$lts for 6A6D +23 nm ec!nolog"-:

Voltage*ime or ransient +,it! o$t load-:



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Voltage Vs C$rrent grap!s:

(it! O$t load:

Comments:note the po4e" conu3ption.

(it! load+%&%1 pf-:

Comments:note the change in po4e" conu3ption.e0e" co3pa"ative ta


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E"e Diagram of O*P Vs& I*p:

(it! O$t Load:



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'D Vie, of 6A6D 7ate:%&1' $m 23 nm



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Experiment 4: Differential Amplifier

Aim:To deign Baic di00e"ential =3pli0ie" uing cu""ent 3i""o" logic.

!eor":The


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P!"sical La"o$t:La"o$t design $sing %&1' 9m ec!nolog":

Area /tili0ation for Differential Amplifier in %&1' $m tec!nolog":9idth: &.&G3 H la3


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Sim$lation es$lts:

Voltage*ime or ransient:

7ain es$lt 7rap!:

2K


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and (idt! es$lt 7rap!:

*"o3 a


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4D Vie,+53 degtree- of Differential Amplifier:

La"o$t design $sing 23 nm ec!nolog":

Area /tili0ation for Differential Amplifier in 23nm tec!nolog":9idth: 1.-G3 H la3


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Sim$lation es$lts:

Voltage*ime or ransient:



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and (idt! es$lt 7rap!:

Comments:*"o3 a


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'D Cross Sectional Vie,:%&1' $m 23 nm



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Experiment 5: ';it Parallel Adder

Aim:To deign and i3ple3ent 2


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P!"sical La"o$t:

La"o$t design $sing 23 n m ec!nolog" +$sing Verilog 6etlist to La"o$t Conversion-:

Area /tili0ation for Differential Amplifier in 23 nm tec!nolog":9idth: K.2G3 H2% la3


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7lo#al Dela" Anal"0er:

Dela" (it! in t!e Inter Connections is calc$lated $sing #elo, )orm$la:

Dela" eportfor 23nm ec!nolog" for %&1'$m ec!nolog":

Ma+i3u3 path delay: &$p Ma+i3u3 path delay: 2Kp

&


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Sim$lation es$lts:

Voltage*ime or ransient +23 nm ec!nolog"-:



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Voltage Vs C$rrent grap! +23 nm ec!nolog"-:



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Experiment 3: Sc!mitt rigger

Aim: To Deign 6ch3itt t"igge" ci"cuit 4ith 8TPJ %.'7 and LTP J %.27. Plot t"an0e" cu"veanalyi

!eor": The 6ch3itt t"igge" ha 0ound 3any application in nu3e"ou ci"cuit,


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(or8ing:=u3ing the output i highHJ7DDI and the input i lo4 H%7I.=


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La"o$t design $sing 23 n m ec!nolog":

Area /tili0ation for Differential Amplifier in 23 nm tec!nolog":9idth: 2.G3 HK& la3


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Sim$lation es$lts:Voltage*ime or ransient Anal"sis +23 nm ec!nolog"-:



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LTP voltage cu"ve:

*"o3 the a


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4D Vie, of Sc!mitt trigger +53 degree Vie,-:

es$lt: 8ing a