Download pdf - Tiva C Series TM4C123GH6ZRB Microcontroller Data Sheet ... · 15.3.1 BitRateGeneration.....989 15.3.2 FIFOOperation.....989

Tiva™ TM4C123GH6ZRB Microcontroller

DATA SHEET

Copyr ight © 2007-2014Texas Instruments Incorporated

DS-TM4C123GH6ZRB-15842.2741SPMS378E

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

June 12, 20142Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 39About This Document .................................................................................................................... 43Audience .............................................................................................................................................. 43About This Manual ................................................................................................................................ 43Related Documents ............................................................................................................................... 43Documentation Conventions .................................................................................................................. 44

1 Architectural Overview .......................................................................................... 461.1 Tiva™ C Series Overview .............................................................................................. 461.2 TM4C123GH6ZRB Microcontroller Overview .................................................................. 471.3 TM4C123GH6ZRB Microcontroller Features ................................................................... 501.3.1 ARM Cortex-M4F Processor Core .................................................................................. 501.3.2 On-Chip Memory ........................................................................................................... 521.3.3 Serial Communications Peripherals ................................................................................ 541.3.4 System Integration ........................................................................................................ 581.3.5 Advanced Motion Control ............................................................................................... 641.3.6 Analog .......................................................................................................................... 661.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 681.3.8 Packaging and Temperature .......................................................................................... 681.4 TM4C123GH6ZRB Microcontroller Hardware Details ....................................................... 691.5 Kits .............................................................................................................................. 691.6 Support Information ....................................................................................................... 69

2 The Cortex-M4F Processor ................................................................................... 702.1 Block Diagram .............................................................................................................. 712.2 Overview ...................................................................................................................... 722.2.1 System-Level Interface .................................................................................................. 722.2.2 Integrated Configurable Debug ...................................................................................... 722.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 732.2.4 Cortex-M4F System Component Details ......................................................................... 732.3 Programming Model ...................................................................................................... 742.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 742.3.2 Stacks .......................................................................................................................... 752.3.3 Register Map ................................................................................................................ 752.3.4 Register Descriptions .................................................................................................... 772.3.5 Exceptions and Interrupts .............................................................................................. 932.3.6 Data Types ................................................................................................................... 932.4 Memory Model .............................................................................................................. 932.4.1 Memory Regions, Types and Attributes ........................................................................... 962.4.2 Memory System Ordering of Memory Accesses .............................................................. 962.4.3 Behavior of Memory Accesses ....................................................................................... 972.4.4 Software Ordering of Memory Accesses ......................................................................... 972.4.5 Bit-Banding ................................................................................................................... 982.4.6 Data Storage .............................................................................................................. 1012.4.7 Synchronization Primitives ........................................................................................... 1012.5 Exception Model ......................................................................................................... 1022.5.1 Exception States ......................................................................................................... 103

3June 12, 2014Texas Instruments-Production Data


2.5.2 Exception Types .......................................................................................................... 1032.5.3 Exception Handlers ..................................................................................................... 1082.5.4 Vector Table ................................................................................................................ 1082.5.5 Exception Priorities ...................................................................................................... 1092.5.6 Interrupt Priority Grouping ............................................................................................ 1102.5.7 Exception Entry and Return ......................................................................................... 1102.6 Fault Handling ............................................................................................................. 1132.6.1 Fault Types ................................................................................................................. 1142.6.2 Fault Escalation and Hard Faults .................................................................................. 1142.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1152.6.4 Lockup ....................................................................................................................... 1152.7 Power Management .................................................................................................... 1162.7.1 Entering Sleep Modes ................................................................................................. 1162.7.2 Wake Up from Sleep Mode .......................................................................................... 1162.8 Instruction Set Summary .............................................................................................. 117

3 Cortex-M4 Peripherals ......................................................................................... 1243.1 Functional Description ................................................................................................. 1243.1.1 System Timer (SysTick) ............................................................................................... 1253.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1263.1.3 System Control Block (SCB) ........................................................................................ 1273.1.4 Memory Protection Unit (MPU) ..................................................................................... 1273.1.5 Floating-Point Unit (FPU) ............................................................................................. 1323.2 Register Map .............................................................................................................. 1363.3 System Timer (SysTick) Register Descriptions .............................................................. 1393.4 NVIC Register Descriptions .......................................................................................... 1433.5 System Control Block (SCB) Register Descriptions ........................................................ 1583.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1873.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 196

4 JTAG Interface ...................................................................................................... 2024.1 Block Diagram ............................................................................................................ 2034.2 Signal Description ....................................................................................................... 2034.3 Functional Description ................................................................................................. 2044.3.1 JTAG Interface Pins ..................................................................................................... 2044.3.2 JTAG TAP Controller ................................................................................................... 2064.3.3 Shift Registers ............................................................................................................ 2064.3.4 Operational Considerations .......................................................................................... 2074.4 Initialization and Configuration ..................................................................................... 2094.5 Register Descriptions .................................................................................................. 2104.5.1 Instruction Register (IR) ............................................................................................... 2104.5.2 Data Registers ............................................................................................................ 212

5 System Control ..................................................................................................... 2145.1 Signal Description ....................................................................................................... 2145.2 Functional Description ................................................................................................. 2145.2.1 Device Identification .................................................................................................... 2145.2.2 Reset Control .............................................................................................................. 2155.2.3 Non-Maskable Interrupt ............................................................................................... 2205.2.4 Power Control ............................................................................................................. 2205.2.5 Clock Control .............................................................................................................. 221


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5.2.6 System Control ........................................................................................................... 2295.3 Initialization and Configuration ..................................................................................... 2335.4 Register Map .............................................................................................................. 2335.5 System Control Register Descriptions ........................................................................... 2395.6 System Control Legacy Register Descriptions ............................................................... 433

6 System Exception Module ................................................................................... 4996.1 Functional Description ................................................................................................. 4996.2 Register Map .............................................................................................................. 4996.3 Register Descriptions .................................................................................................. 499

7 Hibernation Module .............................................................................................. 5077.1 Block Diagram ............................................................................................................ 5087.2 Signal Description ....................................................................................................... 5087.3 Functional Description ................................................................................................. 5097.3.1 Register Access Timing ............................................................................................... 5097.3.2 Hibernation Clock Source ............................................................................................ 5107.3.3 System Implementation ............................................................................................... 5117.3.4 Battery Management ................................................................................................... 5127.3.5 Real-Time Clock .......................................................................................................... 5137.3.6 Battery-Backed Memory .............................................................................................. 5157.3.7 Power Control Using HIB ............................................................................................. 5157.3.8 Power Control Using VDD3ON Mode ........................................................................... 5167.3.9 Initiating Hibernate ...................................................................................................... 5167.3.10 Waking from Hibernate ................................................................................................ 5167.3.11 Arbitrary Power Removal ............................................................................................. 5167.3.12 Interrupts and Status ................................................................................................... 5177.4 Initialization and Configuration ..................................................................................... 5177.4.1 Initialization ................................................................................................................. 5177.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5187.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5197.4.4 External Wake-Up from Hibernation .............................................................................. 5197.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5197.5 Register Map .............................................................................................................. 5197.6 Register Descriptions .................................................................................................. 520

8 Internal Memory ................................................................................................... 5388.1 Block Diagram ............................................................................................................ 5388.2 Functional Description ................................................................................................. 5398.2.1 SRAM ........................................................................................................................ 5398.2.2 ROM .......................................................................................................................... 5408.2.3 Flash Memory ............................................................................................................. 5428.2.4 EEPROM .................................................................................................................... 5488.3 Register Map .............................................................................................................. 5548.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 5558.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 5738.6 Memory Register Descriptions (System Control Offset) .................................................. 590

9 Micro Direct Memory Access (μDMA) ................................................................ 5999.1 Block Diagram ............................................................................................................ 6009.2 Functional Description ................................................................................................. 600



9.2.1 Channel Assignments .................................................................................................. 6019.2.2 Priority ........................................................................................................................ 6029.2.3 Arbitration Size ............................................................................................................ 6029.2.4 Request Types ............................................................................................................ 6029.2.5 Channel Configuration ................................................................................................. 6039.2.6 Transfer Modes ........................................................................................................... 6059.2.7 Transfer Size and Increment ........................................................................................ 6139.2.8 Peripheral Interface ..................................................................................................... 6139.2.9 Software Request ........................................................................................................ 6139.2.10 Interrupts and Errors .................................................................................................... 6149.3 Initialization and Configuration ..................................................................................... 6149.3.1 Module Initialization ..................................................................................................... 6149.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6159.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6169.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6189.3.5 Configuring Channel Assignments ................................................................................ 6209.4 Register Map .............................................................................................................. 6209.5 μDMA Channel Control Structure ................................................................................. 6229.6 μDMA Register Descriptions ........................................................................................ 629

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 66310.1 Signal Description ....................................................................................................... 66310.2 Functional Description ................................................................................................. 66810.2.1 Data Control ............................................................................................................... 67010.2.2 Interrupt Control .......................................................................................................... 67110.2.3 Mode Control .............................................................................................................. 67310.2.4 Commit Control ........................................................................................................... 67310.2.5 Pad Control ................................................................................................................. 67310.2.6 Identification ............................................................................................................... 67310.3 Initialization and Configuration ..................................................................................... 67310.4 Register Map .............................................................................................................. 67510.5 Register Descriptions .................................................................................................. 678

11 General-Purpose Timers ...................................................................................... 72911.1 Block Diagram ............................................................................................................ 73011.2 Signal Description ....................................................................................................... 73111.3 Functional Description ................................................................................................. 73311.3.1 GPTM Reset Conditions .............................................................................................. 73411.3.2 Timer Modes ............................................................................................................... 73511.3.3 Wait-for-Trigger Mode .................................................................................................. 74411.3.4 Synchronizing GP Timer Blocks ................................................................................... 74511.3.5 DMA Operation ........................................................................................................... 74611.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 74611.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 74611.4 Initialization and Configuration ..................................................................................... 74811.4.1 One-Shot/Periodic Timer Mode .................................................................................... 74811.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 74911.4.3 Input Edge-Count Mode ............................................................................................... 74911.4.4 Input Edge Time Mode ................................................................................................. 75011.4.5 PWM Mode ................................................................................................................. 750


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11.5 Register Map .............................................................................................................. 75111.6 Register Descriptions .................................................................................................. 752

12 Watchdog Timers ................................................................................................. 80012.1 Block Diagram ............................................................................................................ 80112.2 Functional Description ................................................................................................. 80112.2.1 Register Access Timing ............................................................................................... 80212.3 Initialization and Configuration ..................................................................................... 80212.4 Register Map .............................................................................................................. 80212.5 Register Descriptions .................................................................................................. 803

13 Analog-to-Digital Converter (ADC) ..................................................................... 82513.1 Block Diagram ............................................................................................................ 82613.2 Signal Description ....................................................................................................... 82713.3 Functional Description ................................................................................................. 82813.3.1 Sample Sequencers .................................................................................................... 82913.3.2 Module Control ............................................................................................................ 82913.3.3 Hardware Sample Averaging Circuit ............................................................................. 83313.3.4 Analog-to-Digital Converter .......................................................................................... 83413.3.5 Differential Sampling ................................................................................................... 83713.3.6 Internal Temperature Sensor ........................................................................................ 83913.3.7 Digital Comparator Unit ............................................................................................... 84013.4 Initialization and Configuration ..................................................................................... 84413.4.1 Module Initialization ..................................................................................................... 84413.4.2 Sample Sequencer Configuration ................................................................................. 84513.5 Register Map .............................................................................................................. 84513.6 Register Descriptions .................................................................................................. 847

14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 92514.1 Block Diagram ............................................................................................................ 92614.2 Signal Description ....................................................................................................... 92614.3 Functional Description ................................................................................................. 92714.3.1 Transmit/Receive Logic ............................................................................................... 92814.3.2 Baud-Rate Generation ................................................................................................. 92814.3.3 Data Transmission ...................................................................................................... 92914.3.4 Serial IR (SIR) ............................................................................................................. 92914.3.5 ISO 7816 Support ....................................................................................................... 93114.3.6 Modem Handshake Support ......................................................................................... 93114.3.7 9-Bit UART Mode ........................................................................................................ 93214.3.8 FIFO Operation ........................................................................................................... 93314.3.9 Interrupts .................................................................................................................... 93314.3.10 Loopback Operation .................................................................................................... 93414.3.11 DMA Operation ........................................................................................................... 93414.4 Initialization and Configuration ..................................................................................... 93514.5 Register Map .............................................................................................................. 93614.6 Register Descriptions .................................................................................................. 938

15 Synchronous Serial Interface (SSI) .................................................................... 98615.1 Block Diagram ............................................................................................................ 98715.2 Signal Description ....................................................................................................... 98715.3 Functional Description ................................................................................................. 988



15.3.1 Bit Rate Generation ..................................................................................................... 98915.3.2 FIFO Operation ........................................................................................................... 98915.3.3 Interrupts .................................................................................................................... 98915.3.4 Frame Formats ........................................................................................................... 99015.3.5 DMA Operation ........................................................................................................... 99815.4 Initialization and Configuration ..................................................................................... 99915.5 Register Map ............................................................................................................ 100115.6 Register Descriptions ................................................................................................. 1002

16 Inter-Integrated Circuit (I2C) Interface .............................................................. 103116.1 Block Diagram ........................................................................................................... 103216.2 Signal Description ..................................................................................................... 103216.3 Functional Description ............................................................................................... 103316.3.1 I2C Bus Functional Overview ...................................................................................... 103316.3.2 Available Speed Modes ............................................................................................. 103816.3.3 Interrupts .................................................................................................................. 104016.3.4 Loopback Operation .................................................................................................. 104116.3.5 Command Sequence Flow Charts .............................................................................. 104116.4 Initialization and Configuration .................................................................................... 104916.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 104916.4.2 Configure the I2C Master to High Speed Mode ............................................................ 105016.5 Register Map ............................................................................................................ 105116.6 Register Descriptions (I2C Master) .............................................................................. 105216.7 Register Descriptions (I2C Slave) ............................................................................... 106916.8 Register Descriptions (I2C Status and Control) ............................................................ 1079

17 Controller Area Network (CAN) Module ........................................................... 108217.1 Block Diagram ........................................................................................................... 108317.2 Signal Description ..................................................................................................... 108317.3 Functional Description ............................................................................................... 108417.3.1 Initialization ............................................................................................................... 108517.3.2 Operation .................................................................................................................. 108617.3.3 Transmitting Message Objects ................................................................................... 108717.3.4 Configuring a Transmit Message Object ...................................................................... 108717.3.5 Updating a Transmit Message Object ......................................................................... 108817.3.6 Accepting Received Message Objects ........................................................................ 108917.3.7 Receiving a Data Frame ............................................................................................ 108917.3.8 Receiving a Remote Frame ........................................................................................ 108917.3.9 Receive/Transmit Priority ........................................................................................... 109017.3.10 Configuring a Receive Message Object ...................................................................... 109017.3.11 Handling of Received Message Objects ...................................................................... 109117.3.12 Handling of Interrupts ................................................................................................ 109317.3.13 Test Mode ................................................................................................................. 109417.3.14 Bit Timing Configuration Error Considerations ............................................................. 109617.3.15 Bit Time and Bit Rate ................................................................................................. 109617.3.16 Calculating the Bit Timing Parameters ........................................................................ 109817.4 Register Map ............................................................................................................ 110117.5 CAN Register Descriptions ......................................................................................... 1102


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18 Universal Serial Bus (USB) Controller ............................................................. 113318.1 Block Diagram ........................................................................................................... 113418.2 Signal Description ..................................................................................................... 113418.3 Functional Description ............................................................................................... 113518.3.1 Operation as a Device ............................................................................................... 113518.3.2 Operation as a Host ................................................................................................... 114118.3.3 OTG Mode ................................................................................................................ 114418.3.4 DMA Operation ......................................................................................................... 114618.4 Initialization and Configuration .................................................................................... 114718.4.1 Pin Configuration ....................................................................................................... 114718.4.2 Endpoint Configuration .............................................................................................. 114818.5 Register Map ............................................................................................................ 114818.6 Register Descriptions ................................................................................................. 1154

19 Analog Comparators .......................................................................................... 124919.1 Block Diagram ........................................................................................................... 125019.2 Signal Description ..................................................................................................... 125019.3 Functional Description ............................................................................................... 125119.3.1 Internal Reference Programming ................................................................................ 125219.4 Initialization and Configuration .................................................................................... 125419.5 Register Map ............................................................................................................ 125519.6 Register Descriptions ................................................................................................. 1255

20 Pulse Width Modulator (PWM) .......................................................................... 126520.1 Block Diagram ........................................................................................................... 126620.2 Signal Description ..................................................................................................... 126820.3 Functional Description ............................................................................................... 127020.3.1 Clock Configuration ................................................................................................... 127020.3.2 PWM Timer ............................................................................................................... 127020.3.3 PWM Comparators .................................................................................................... 127020.3.4 PWM Signal Generator .............................................................................................. 127120.3.5 Dead-Band Generator ............................................................................................... 127220.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 127220.3.7 Synchronization Methods .......................................................................................... 127320.3.8 Fault Conditions ........................................................................................................ 127420.3.9 Output Control Block .................................................................................................. 127520.4 Initialization and Configuration .................................................................................... 127520.5 Register Map ............................................................................................................ 127620.6 Register Descriptions ................................................................................................. 1279

21 Quadrature Encoder Interface (QEI) ................................................................. 134421.1 Block Diagram ........................................................................................................... 134421.2 Signal Description ..................................................................................................... 134621.3 Functional Description ............................................................................................... 134721.4 Initialization and Configuration .................................................................................... 134921.5 Register Map ............................................................................................................ 135021.6 Register Descriptions ................................................................................................. 1350

22 Pin Diagram ........................................................................................................ 136723 Signal Tables ...................................................................................................... 136823.1 Signals by Pin Number .............................................................................................. 1369



23.2 Signals by Signal Name ............................................................................................. 138523.3 Signals by Function, Except for GPIO ......................................................................... 139823.4 GPIO Pins and Alternate Functions ............................................................................ 140923.5 Possible Pin Assignments for Alternate Functions ....................................................... 141323.6 Connections for Unused Signals ................................................................................. 1417

24 Electrical Characteristics .................................................................................. 141924.1 Maximum Ratings ...................................................................................................... 141924.2 Operating Characteristics ........................................................................................... 142024.3 Recommended Operating Conditions ......................................................................... 142124.4 Load Conditions ........................................................................................................ 142324.5 JTAG and Boundary Scan .......................................................................................... 142424.6 Power and Brown-Out ............................................................................................... 142624.6.1 VDDA Levels ............................................................................................................ 142624.6.2 VDD Levels ............................................................................................................... 142724.6.3 VDDC Levels ............................................................................................................ 142824.6.4 VDD Glitches ............................................................................................................ 142924.6.5 VDD Droop Response ............................................................................................... 142924.7 Reset ........................................................................................................................ 143124.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 143424.9 Clocks ...................................................................................................................... 143524.9.1 PLL Specifications ..................................................................................................... 143524.9.2 PIOSC Specifications ................................................................................................ 143624.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 143624.9.4 Hibernation Clock Source Specifications ..................................................................... 143624.9.5 Main Oscillator Specifications ..................................................................................... 143724.9.6 System Clock Specification with ADC Operation .......................................................... 144124.9.7 System Clock Specification with USB Operation .......................................................... 144124.10 Sleep Modes ............................................................................................................. 144224.11 Hibernation Module ................................................................................................... 144424.12 Flash Memory and EEPROM ..................................................................................... 144624.13 Input/Output Pin Characteristics ................................................................................. 144724.13.1 GPIO Module Characteristics ..................................................................................... 144724.13.2 Types of I/O Pins and ESD Protection ......................................................................... 144724.14 Analog-to-Digital Converter (ADC) .............................................................................. 145124.15 Synchronous Serial Interface (SSI) ............................................................................. 145524.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 145824.17 Universal Serial Bus (USB) Controller ......................................................................... 145924.18 Analog Comparator ................................................................................................... 146024.19 Pulse-Width Modulator (PWM) ................................................................................... 146124.20 Current Consumption ................................................................................................. 1462

A Package Information .......................................................................................... 1465A.1 Orderable Devices ..................................................................................................... 1465A.2 Device Nomenclature ................................................................................................ 1465A.3 Device Markings ........................................................................................................ 1466A.4 Packaging Diagram ................................................................................................... 1467


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List of FiguresFigure 1-1. Tiva™ TM4C123GH6ZRB Microcontroller High-Level Block Diagram ....................... 49Figure 2-1. CPU Block Diagram ............................................................................................. 72Figure 2-2. TPIU Block Diagram ............................................................................................ 73Figure 2-3. Cortex-M4F Register Set ...................................................................................... 76Figure 2-4. Bit-Band Mapping .............................................................................................. 100Figure 2-5. Data Storage ..................................................................................................... 101Figure 2-6. Vector Table ...................................................................................................... 109Figure 2-7. Exception Stack Frame ...................................................................................... 112Figure 3-1. SRD Use Example ............................................................................................. 130Figure 3-2. FPU Register Bank ............................................................................................ 133Figure 4-1. JTAG Module Block Diagram .............................................................................. 203Figure 4-2. Test Access Port State Machine ......................................................................... 206Figure 4-3. IDCODE Register Format ................................................................................... 212Figure 4-4. BYPASS Register Format ................................................................................... 212Figure 4-5. Boundary Scan Register Format ......................................................................... 213Figure 5-1. Basic RST Configuration .................................................................................... 217Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 217Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 218Figure 5-4. Power Architecture ............................................................................................ 221Figure 5-5. Main Clock Tree ................................................................................................ 224Figure 5-6. Module Clock Selection ...................................................................................... 231Figure 7-1. Hibernation Module Block Diagram ..................................................................... 508Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 511Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 511Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 512Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 515Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 515Figure 8-1. Internal Memory Block Diagram .......................................................................... 538Figure 8-2. EEPROM Block Diagram ................................................................................... 539Figure 9-1. μDMA Block Diagram ......................................................................................... 600Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 606Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 608Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 609Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 611Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 612Figure 10-1. Digital I/O Pads ................................................................................................. 669Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 670Figure 10-3. GPIODATA Write Example ................................................................................. 671Figure 10-4. GPIODATA Read Example ................................................................................. 671Figure 11-1. GPTM Module Block Diagram ............................................................................ 730Figure 11-2. Reading the RTC Value ...................................................................................... 738Figure 11-3. Input Edge-Count Mode Example, Counting Down ............................................... 740Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 741Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 743Figure 11-6. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 743



Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 744Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 744Figure 11-9. Timer Daisy Chain ............................................................................................. 745Figure 12-1. WDT Module Block Diagram .............................................................................. 801Figure 13-1. Implementation of Two ADC Blocks .................................................................... 826Figure 13-2. ADC Module Block Diagram ............................................................................... 827Figure 13-3. ADC Sample Phases ......................................................................................... 831Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 831Figure 13-5. Skewed Sampling .............................................................................................. 832Figure 13-6. Sample Averaging Example ............................................................................... 834Figure 13-7. ADC Input Equivalency ...................................................................................... 835Figure 13-8. ADC Voltage Reference ..................................................................................... 836Figure 13-9. ADC Conversion Result ..................................................................................... 837Figure 13-10. Differential Voltage Representation ..................................................................... 839Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 840Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 842Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 843Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 844Figure 14-1. UART Module Block Diagram ............................................................................. 926Figure 14-2. UART Character Frame ..................................................................................... 928Figure 14-3. IrDA Data Modulation ......................................................................................... 930Figure 15-1. SSI Module Block Diagram ................................................................................. 987Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 991Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 992Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 993Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 993Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 994Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 995Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 995Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 996Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 997Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 998Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 998Figure 16-1. I2C Block Diagram ........................................................................................... 1032Figure 16-2. I2C Bus Configuration ....................................................................................... 1033Figure 16-3. START and STOP Conditions ........................................................................... 1034Figure 16-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1034Figure 16-5. R/S Bit in First Byte .......................................................................................... 1035Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1035Figure 16-7. High-Speed Data Format .................................................................................. 1040Figure 16-8. Master Single TRANSMIT ................................................................................ 1042Figure 16-9. Master Single RECEIVE ................................................................................... 1043Figure 16-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1044Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1045Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1046Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1047Figure 16-14. Standard High Speed Mode Master Transmit ..................................................... 1048Figure 16-15. Slave Command Sequence .............................................................................. 1049


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Figure 17-1. CAN Controller Block Diagram .......................................................................... 1083Figure 17-2. CAN Data/Remote Frame ................................................................................. 1085Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1093Figure 17-4. CAN Bit Time ................................................................................................... 1097Figure 18-1. USB Module Block Diagram ............................................................................. 1134Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1250Figure 19-2. Structure of Comparator Unit ............................................................................ 1251Figure 19-3. Comparator Internal Reference Structure .......................................................... 1252Figure 20-1. PWM Module Diagram ..................................................................................... 1267Figure 20-2. PWM Generator Block Diagram ........................................................................ 1267Figure 20-3. PWM Count-Down Mode .................................................................................. 1271Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1271Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1272Figure 20-6. PWM Dead-Band Generator ............................................................................. 1272Figure 21-1. QEI Block Diagram .......................................................................................... 1345Figure 21-2. QEI Input Signal Logic ...................................................................................... 1346Figure 21-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1348Figure 22-1. 157-Ball BGA Package Pin Diagram (Top View) ................................................. 1367Figure 24-1. Load Conditions ............................................................................................... 1423Figure 24-2. JTAG Test Clock Input Timing ........................................................................... 1424Figure 24-3. JTAG Test Access Port (TAP) Timing ................................................................ 1425Figure 24-4. Power Assertions versus VDDA Levels ............................................................. 1427Figure 24-5. Power and Brown-Out Assertions versus VDD Levels ........................................ 1428Figure 24-6. POK assertion vs VDDC ................................................................................... 1429Figure 24-7. POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1429Figure 24-8. POR-BOR0-BOR1 VDD Droop Response ......................................................... 1430Figure 24-9. Digital Power-On Reset Timing ......................................................................... 1431Figure 24-10. Brown-Out Reset Timing .................................................................................. 1432Figure 24-11. External Reset Timing (RST) ............................................................................ 1432Figure 24-12. Software Reset Timing ..................................................................................... 1432Figure 24-13. Watchdog Reset Timing ................................................................................... 1432Figure 24-14. MOSC Failure Reset Timing ............................................................................. 1433Figure 24-15. Hibernation Module Timing ............................................................................... 1445Figure 24-16. ESD Protection on Fail-Safe Pins ...................................................................... 1448Figure 24-17. ESD Protection on Non-Fail-Safe Pins .............................................................. 1449Figure 24-18. ADC External Reference Filtering ..................................................................... 1453Figure 24-19. ADC Input Equivalency Diagram ....................................................................... 1454Figure 24-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1456Figure 24-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1456Figure 24-22. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1457Figure 24-23. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1457Figure 24-24. I2C Timing ....................................................................................................... 1458Figure A-1. Key to Part Numbers ........................................................................................ 1465Figure A-2. TM4C123GH6ZRB 157-Ball BGA Package Dimensions ..................................... 1467



List of TablesTable 1. Revision History .................................................................................................. 39Table 2. Documentation Conventions ................................................................................ 44Table 1-1. TM4C123GH6ZRB Microcontroller Features ......................................................... 47Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 75Table 2-2. Processor Register Map ....................................................................................... 76Table 2-3. PSR Register Combinations ................................................................................. 82Table 2-4. Memory Map ....................................................................................................... 93Table 2-5. Memory Access Behavior ..................................................................................... 97Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 99Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 99Table 2-8. Exception Types ................................................................................................ 105Table 2-9. Interrupts .......................................................................................................... 105Table 2-10. Exception Return Behavior ................................................................................. 113Table 2-11. Faults ............................................................................................................... 114Table 2-12. Fault Status and Fault Address Registers ............................................................ 115Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 117Table 3-1. Core Peripheral Register Regions ....................................................................... 124Table 3-2. Memory Attributes Summary .............................................................................. 128Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 130Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 131Table 3-5. AP Bit Field Encoding ........................................................................................ 131Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 132Table 3-7. QNaN and SNaN Handling ................................................................................. 135Table 3-8. Peripherals Register Map ................................................................................... 136Table 3-9. Interrupt Priority Levels ...................................................................................... 166Table 3-10. Example SIZE Field Values ................................................................................ 194Table 4-1. JTAG_SWD_SWO Signals (157BGA) ................................................................. 203Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 204Table 4-3. JTAG Instruction Register Commands ................................................................. 210Table 5-1. System Control & Clocks Signals (157BGA) ........................................................ 214Table 5-2. Reset Sources ................................................................................................... 215Table 5-3. Clock Source Options ........................................................................................ 222Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 225Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 225Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 226Table 5-7. System Control Register Map ............................................................................. 234Table 5-8. RCC2 Fields that Override RCC Fields ............................................................... 264Table 6-1. System Exception Register Map ......................................................................... 499Table 7-1. Hibernate Signals (157BGA) .............................................................................. 508Table 7-2. Hibernation Module Clock Operation ................................................................... 518Table 7-3. Hibernation Module Register Map ....................................................................... 520Table 8-1. Flash Memory Protection Policy Combinations .................................................... 543Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 547Table 8-3. Flash Register Map ............................................................................................ 554Table 9-1. μDMA Channel Assignments .............................................................................. 601Table 9-2. Request Type Support ....................................................................................... 603


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Table 9-3. Control Structure Memory Map ........................................................................... 604Table 9-4. Channel Control Structure .................................................................................. 604Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 613Table 9-6. μDMA Interrupt Assignments .............................................................................. 614Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 615Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 616Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 617Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 617Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 618Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 619Table 9-13. μDMA Register Map .......................................................................................... 621Table 10-1. GPIO Pins With Special Considerations .............................................................. 664Table 10-2. GPIO Pins and Alternate Functions (157BGA) ..................................................... 664Table 10-3. GPIO Pad Configuration Examples ..................................................................... 674Table 10-4. GPIO Interrupt Configuration Example ................................................................ 675Table 10-5. GPIO Pins With Special Considerations .............................................................. 676Table 10-6. GPIO Register Map ........................................................................................... 677Table 10-7. GPIO Pins With Special Considerations .............................................................. 693Table 10-8. GPIO Pins With Special Considerations .............................................................. 700Table 10-9. GPIO Pins With Special Considerations .............................................................. 702Table 10-10. GPIO Pins With Special Considerations .............................................................. 705Table 10-11. GPIO Pins With Special Considerations .............................................................. 712Table 11-1. Available CCP Pins ............................................................................................ 731Table 11-2. General-Purpose Timers Signals (157BGA) ......................................................... 731Table 11-3. General-Purpose Timer Capabilities .................................................................... 734Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 735Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 737Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 737Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 737Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 739Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 740Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 742Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 745Table 11-12. Timers Register Map .......................................................................................... 752Table 12-1. Watchdog Timers Register Map .......................................................................... 803Table 13-1. ADC Signals (157BGA) ...................................................................................... 827Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 829Table 13-3. Differential Sampling Pairs ................................................................................. 837Table 13-4. ADC Register Map ............................................................................................. 845Table 14-1. UART Signals (157BGA) .................................................................................... 927Table 14-2. Flow Control Mode ............................................................................................. 932Table 14-3. UART Register Map ........................................................................................... 937Table 15-1. SSI Signals (157BGA) ........................................................................................ 988Table 15-2. SSI Register Map ............................................................................................. 1001Table 16-1. I2C Signals (157BGA) ...................................................................................... 1032Table 16-2. Examples of I2C Master Timer Period Versus Speed Mode ................................. 1038Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode ................................ 1039



Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1051Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1057Table 17-1. Controller Area Network Signals (157BGA) ........................................................ 1084Table 17-2. Message Object Configurations ........................................................................ 1090Table 17-3. CAN Protocol Ranges ...................................................................................... 1097Table 17-4. CANBIT Register Values .................................................................................. 1097Table 17-5. CAN Register Map ........................................................................................... 1101Table 18-1. USB Signals (157BGA) .................................................................................... 1135Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1146Table 18-3. Actual Bytes Read ........................................................................................... 1146Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1147Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1148Table 19-1. Analog Comparators Signals (157BGA) ............................................................. 1250Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1252Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1253Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1254Table 19-5. Analog Comparators Register Map ................................................................... 1255Table 20-1. PWM Signals (157BGA) ................................................................................... 1268Table 20-2. PWM Register Map .......................................................................................... 1276Table 21-1. QEI Signals (157BGA) ..................................................................................... 1346Table 21-2. QEI Register Map ............................................................................................ 1350Table 23-1. GPIO Pins With Special Considerations ............................................................ 1368Table 23-2. Signals by Pin Number ..................................................................................... 1369Table 23-3. Signals by Signal Name ................................................................................... 1385Table 23-4. Signals by Function, Except for GPIO ............................................................... 1398Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1409Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1413Table 23-7. Connections for Unused Signals (157-Ball BGA) ............................................... 1418Table 24-1. Absolute Maximum Ratings .............................................................................. 1419Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1419Table 24-3. Temperature Characteristics ............................................................................. 1420Table 24-4. Thermal Characteristics ................................................................................... 1420Table 24-5. Recommended DC Operating Conditions .......................................................... 1421Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1421Table 24-7. GPIO Current Restrictions ................................................................................ 1421Table 24-8. GPIO Package Side Assignments ..................................................................... 1422Table 24-9. JTAG Characteristics ....................................................................................... 1424Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1426Table 24-11. Reset Characteristics ....................................................................................... 1431Table 24-12. LDO Regulator Characteristics ......................................................................... 1434Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1435Table 24-14. Actual PLL Frequency ...................................................................................... 1435Table 24-15. PIOSC Clock Characteristics ............................................................................ 1436Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1436Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1436Table 24-18. Main Oscillator Input Characteristics ................................................................. 1437


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Table 24-19. Crystal Parameters .......................................................................................... 1439Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1440Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1441Table 24-22. System Clock Characteristics with USB Operation ............................................. 1441Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1442Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1442Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1444Table 24-26. Hibernation Module AC Characteristics ............................................................. 1444Table 24-27. Flash Memory Characteristics ........................................................................... 1446Table 24-28. EEPROM Characteristics ................................................................................. 1446Table 24-29. GPIO Module Characteristics ............................................................................ 1447Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1448Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1449Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1449Table 24-33. ADC Electrical Characteristics .......................................................................... 1451Table 24-34. SSI Characteristics .......................................................................................... 1455Table 24-35. I2C Characteristics ........................................................................................... 1458Table 24-36. Analog Comparator Characteristics ................................................................... 1460Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1460Table 24-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1460Table 24-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1461Table 24-40. PWM Timing Characteristics ............................................................................. 1461Table 24-41. Current Consumption ....................................................................................... 1462



List of RegistersThe Cortex-M4F Processor ........................................................................................................... 70Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 78Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 78Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 78Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 78Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 78Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 78Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 78Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 78Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 78Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 78Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 78Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 78Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 78Register 14: Stack Pointer (SP) ........................................................................................................... 79Register 15: Link Register (LR) ............................................................................................................ 80Register 16: Program Counter (PC) ..................................................................................................... 81Register 17: Program Status Register (PSR) ........................................................................................ 82Register 18: Priority Mask Register (PRIMASK) .................................................................................... 86Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 87Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 88Register 21: Control Register (CONTROL) ........................................................................................... 89Register 22: Floating-Point Status Control (FPSC) ................................................................................ 91

Cortex-M4 Peripherals ................................................................................................................. 124Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 140Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 142Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 143Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 144Register