Download docx - Verilog Lab Programs

Transcript
Page 1: Verilog Lab Programs

VERILOG LAB PROGRAMS

And gate:

Module andgate(A,B,Y);

Input A,B;

Output Y;

Assign Y=A&B;

EndModule

OR GATE:

Module orgate(A,B,Y);

Input A,B;

Output Y;

Assign Y=A|B;

EndModule

NOT GATE:

Module Notgate(x,y);

Input x;

Output y;

Assign y=~x;

EndModule

XOR GATE:

Module XORGATE(A,B,Y);

Input A,B;

Output Y;

Page 2: Verilog Lab Programs

Assign Y=A^B;

EndModule

NAND GATE:

Module nandgate(A,B,Y);

Input A,B;

Output Y;

Assign Y=~(A&B);

EndModule

NOR GATE:

Module norgate(A,B,Y);

Input A,B;

Output Y;

Assign Y=~(A|B);

EndModule

X-NOR GATE:

Module XNORgate(A,B,Y);

Input A,B;

Output Y;

Assign Y=~(A^B);

EndModule

Page 3: Verilog Lab Programs

ADDER AND SUBTRACTORS:

Half Adder:

Module halfadder(A,B,SUM,CARRY);

Input A,B;

Output SUM,Carry;

Assign SUM=A^B;

Assign CARRY=A&B;

Endmodule

Full adder:

Module fulladder(A,B,CIN,S,COUT);

Input A,B,CIN;

Output S,COUT;

Assign S=(A^b)^CIN;

Assign COUT=((A&b)|(A&CIN)|(B&CIN);

Endmodule

Half subtractor:

Module halfsubtractor(A,B,diff,borrow);

Input A,B;

Output diff,borrow;

Assign diff=A^B;

Assign borrow=(~A)&B;

Endmodule

Page 4: Verilog Lab Programs

Full subtractor:

Module fullsubtractor(A,B,C,S,d,b);

Input A,B,C;

Output d,b;

Assign d=(A^b)^C;

Assign b=((B&C)|(~A)&C|~(A)&B);

Endmodule

Flip Flops:

D-Flip Flops

Module diff_br(clk,reset,D,Q);

Input clk,reset,D;

Output Q;

Reg Q;

Always @(POSEDGE clk or POSEDGE reset)

Begin

If(reset)

Q<=0;

Else

Q<=D;

End

Endmodule

Page 5: Verilog Lab Programs

T-flip flop

Module tff_bh(clk,reset,T,Q);

Input clk,reset,T;

Output q;

Reg q;

Always @(POSEDGE clk or POSEDGE reset)

Begin

If(reset)

Q<=1’b0;

Else

Q<=!Q;

End

Endmodule

Page 6: Verilog Lab Programs

j-k flip flop:

Module jk_bh(clk,J,Q,K);

Input clk,J,K;

Output Q;

Reg Q;

Always @(POSEDGE clk)

Case{(J,K)}

2’b00 : Q<=Q;

2’b01:Q<=1’b0;

2’b10:Q<=1’b1;

2’b11:Q<=~Q;

Endcase

Endmodule

Page 7: Verilog Lab Programs

Multiplxer and demultiplexer:

4X1 Multiplexer:

Module mux4X1_gl(s1,s0,d0,d1,d2,d3,y);

Input d0,d1,d2,d3,s0,s1;

Output y;

Wire(x1,x2,x3,x4,s0_n,s1_n);

Not g0(s0_n,s0);

Not g1(s1_n,s1);

And g2(x1,s0,s1,d0);

G3(x2,s0,s1_n,d1);

G4(x3,s0_n,s1,d2);

G5(x4,s0_n,s1_n,d3);

Or g6(y,x1,x2,x3,x4);

Endmodule

Page 8: Verilog Lab Programs

8x1 multiplexer:

Module mux 8x1_gl(s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7,y);

Input s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7;

Output y;

Wire x0,x1,x2,x3,x4,x5,x6,x7,s0_n,s1_n,s2_n;

Not g0(s0_n,s0);

G1(s1_n,s1);

G2(s2_n,s2);

And g3(x7,s0,s1,s2,d0);

And g4(x6,s0,s1,s2_n,d1);

And g5(x5,s0,s1_n,s2,d2);

And g6(x4,s0,s1_n,s2_n,d3);

And g7(x3,s0_n,s1,s2,d4);

And g8(x2,s0_n,s1,s2_n,d5);

And g9(x1,s0_n,s1_n,s2,d6);

And g10(x0,s0_n,s1_n,s2_n,d7);

Or g11(y,x0,x1,x2,x3,x4,x5,x6,x7);

Endmodule

Page 9: Verilog Lab Programs

1X4 Demultiplexer:

Module demux 1X4_gl(E,S0,S1,D0,D1,D2,D3);

Input SO,S1,E;

Output D0,D1,D2,D3;

Wire S0_n,s1_n;

Not g0(S0_n,S0);

G1(s1_n,s1);

And g2(D0,E,S1_n,S0_n);

And g3(D1,E,S1,S0_n);

And g4(D2,E,S1_n,S0);

And g5(D3,E,S1,S0);

Endmodule.

Page 10: Verilog Lab Programs

1X8 Demultiplexer:

Module demux 8x1_gl(E,s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7);

Input s2,s1,s0,E;

Output d0,d1,d2,d3,d4,d5,d6,d7;

Wire s0_n,s1_n,s2_n;

Not g0(s2_n,s2);

G1(s1_n,s1);

G2(s0_n,s0);

And g3(d0,E,s0,s1_n,s2_n);

And g4(d1,E,s2,s1_n,s0_n);

And g5(d2,E,s1,s2_n,s0_n);

And g6(d3,E,s2,s1,s0_n);

And g7(d4,E,s1_n,s2_n,s0);

And g8(d5,E,s2,s1_n,S0);

And g9(d6,E,s2_n,s1,s0);

And g10(d7,E,s1,s2,s0);

Endmodule

Page 11: Verilog Lab Programs

2-BIT MAGNITUDE COMPARATOR:

Module comp(a,b,agb,aeb,alb);

Input [1:0]a,b;

Output agb,aeb,alb;

reg agb,aeb,alb;

always @(a or b)

begin

if(a>b)

agb=1;

else

agb=0;

if(a<b)

alb=1;

else

alb=0;

end

endmodule

Page 12: Verilog Lab Programs

BINARY TO GRAYCODE:

Module bg_gl(b3,b2,b1,b0,g3,g2,g1,g0);

Input b3,b2,b1,b0;

Output g3,g2,g1,g0;

Assign g3=b3;

Xor g1(g3,b3,b2);

Xor g2(g1,b2,b1);

Xor g3(g0,b1,b0);

Endmodule

GRAYCODE TO BINARY:

Module gb_gl((b3,b2,b1,b0,g3,g2,g1,g0);

Input g3,g2,g1,g0;

Output b3,b2,b1,b0;

Assign b3=g3;

Xor g1(b2,g3,g2);

Xor g2(b1,b2,g1);

Xor g3(b0,b1,g0);

Endmodule


Recommended