VHDL 360©

by: Mohamed Samy Samer El-Saadany

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VHDL 360 © 2

Module 6

Structural Description

Objective

• Modeling Hierarchy• Creating Testbenches• Skills gained:

– Reuse design units several times in a design hierarchy

– Automate testing of design units

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Outline

• Generics• Structural Description• Testbench• Generate Statement• Configuration Statement

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How to create a generic DU?• VHDL provides an easy way to create generic design

units that can be used several times with different properties in the design hierarchy

4-bit counter

8-bit counter

N-bit counter

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Generic Clause

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LIBRARY ieee; USE ieee.NUMERIC_STD.all; -- required to use "unsigned" type

Entity generic_multiplier is generic (N : integer := 4 ); port(A, B: in unsigned(N-1 downto 0); Z : out unsigned(2*N-1 downto 0) ); End entity;

Architecture behave of generic_multiplier is Begin Z <= A * B; End architecture;

Example 1:

Syntax:• Declared inside the entity• The default value can be overridden at

component instantiation• If the optional default_value is missing

in generic clause declaration, it must be present when the component is instantiated

generic ( <identifier>: type [:= default_value]; <identifier>: type [:= default_value]));

Exercise 1

library IEEE; use IEEE.std_logic_1164.all; Entity or_n is <Here> port(<Here> Z : out std_logic ); End or_n ; Architecture behave of or_n is Begin process(A) variable temp : std_logic; begin temp := '0' ; for i in <Here> loop temp := temp or A(i); end loop; Z <= temp; end process; End behave;

A1

ZA2

An

.

.

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• Construct an N-input OR gate by doing the following:• Declare a generic value (N) with default value = 5• Declare an input port (A) of size N• Use the 'range attribute to loop on the input A bits

Exercise 1 (Soln.)

library IEEE; use IEEE.std_logic_1164.all; Entity or_n is generic (N : integer := 5) ; port(A : in std_logic_vector(N-1 downto 0); Z : out std_logic ); End or_n ; Architecture behave of or_n is Begin process(A) variable temp : std_logic; begin temp := '0' ; for i in A'range loop temp := temp or A(i); end loop; Z <= temp; end process; End behave;

A1

ZA2

An

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• An N-input OR gate

Generic ClauseExample 2: N-input AND gate

library IEEE; use IEEE.std_logic_1164.all; Entity and_n is generic ( N : integer := 4 ) ; port(A : in std_logic_vector(N-1 downto 0); Z : out std_logic ); End entity;

Architecture behave of and_n is Begin process(A) variable temp : std_logic ; begin temp := '1' ; for i in A'range loop temp := temp and A(i) ; end loop ; Z <= temp ; end process ; End architecture;

10VHDL 360 ©

A1

ZA2

An

Reference page

Structural Description• Models complex digital system

through a set of components (design units) and their interconnection in a hierarchical fashion

• Hierarchical design approach is always preferred over flat design approach because it reduces the complexity

VHDL 360 © 11

A

EB C

D

Structural Description• Structural modeling involves the following:

– Component declaration• Declaring component names and ports; can be done in the architecture declaration

area or in a package

– Component instantiation and Interconnections• Creating instances of declared components• Connecting instances' ports to appropriate signals

Component declaration

12

Architecture arch of Alu7 is -- component declaration

Component ALU generic (width: integer := 3); port(A, B, Cin: in bit; Result: out bit_vector(8 downto 0)) ; end component; Begin

Example 3:component <component_name> generic( <generic name>: type [:= default_value]); port (<port_names>: <mode> <type>;

: );end component;

Syntax:

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Structural Modeling• Component instantiation and Interconnects

– The instance name is the name of this particular instance

• The component name is the name of the component declared earlier using the component declaration statement

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Example 4:

f1: Alu generic map (Width => 32); port map (A => in1, B => in2, Cin => cin, Result => out1);

<instance_name>: <component_name > generic map( <generic_name> => <value>, …); port map( <port_name> => <sig_name>, …);

Syntax:

Component InstantiationThere are two ways to connect ports:• Positional

– The first signal in the component instantiation corresponds to the first port in the component declaration, the second signal => second port (signal2), etc

– Use “OPEN” keyword to leave port unconnected

• Named

– Explicitly specify port names and the connected signal

– Preferred as it's more readable and avoids misconnection of ports

– Use “OPEN” keyword to leave port unconnected

Reference page

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instance_name: component_name

port map (signal1,

signal2,…);

Syntax:

instance_name: component_name

port map (port2 => signal2,

port1=> signal1,…);

Syntax:

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library IEEE; use IEEE.std_logic_1164.all; Entity top is port(In1: in std_logic_vector(9 downto 0); In2: in std_logic_vector(31 downto 0); In3: in std_logic_vector(4 downto 0); out1, out2, out3 : out std_logic); End entity ; ARCHITECTURE struct OF top is COMPONENT and_n GENERIC (N : integer := 4 ); PORT (A : IN std_logic_vector(N-1 downto 0); Z : OUT std_logic ); END COMPONENT; COMPONENT or_n GENERIC (N : integer := 5); PORT (A : IN std_logic_vector(N-1 downto 0); Z : OUT std_logic ); END COMPONENT; BEGIN OR5 : or_n PORT MAP (A => In3, Z => out3); -- use the default generic value OR32 : or_n GENERIC MAP (N => 32) PORT MAP (A => In2, Z => out2); -- overrides default generic

value AND10: and_n GENERIC MAP (N => 10) PORT MAP (A => In1, Z => out1); END architecture;

Structural ModelingExample 5:

16VHDL 360 ©

fulladder

X

Z

Y

S

C

Example 6: 1-bit Full-Adder

Structural Modeling

ENTITY fullAdder IS PORT(X, Y, Z : IN bit; S : OUT bit; C : OUT bit);END fullAdder; ARCHITECTURE expr OF fullAdder IS

signal temp : bit; BEGIN

temp <= X XOR Y; S <= temp XOR Z;

C <= (X AND Y) OR (Z AND temp);END expr;

Entity my_adder2 is port(a, b: in bit_vector( 1 downto 0); cin : in bit; cout: out bit; z : out bit_vector(1 downto 0));End entity; Architecture arch of my_adder2 is -- component declaration

Component fulladder port(x ,y, z: in bit; c, s : out bit) ; end component; signal t: bit; Begin -- component instantiation f1: fulladder port map (x => a(0), y => b(0), z => cin, c => t, s => z(0));

f2: fulladder port map (x => a(1), z => t, c => cout, s => z(1), y => b(1));

End arch;

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f1

fulladder

f2

fulladder

z

cout

cin

t

X

Y

Z

S

C

X

Y

Z

S

C

Example 7: 2-bit Full-Adder using the 1-bit Full-Adder of Example 6

Structural Modeling

Structural ModelingExample 8:

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY gent_exp2 IS port(A, B, C: in std_logic; G: out std_logic); END ENTITY;

ARCHITECTURE behave OF gent_exp2 IS component or_n generic (N : integer := 5); port(A : in std_logic_vector(N-1 downto 0); Z : out std_logic ); end component;

signal temp1: std_logic; BEGIN

temp1 <= A and B; U: or_n generic map(N => 2) port map (temp1 & C, G); END ARCHITECTURE;

Expression in port map; supported only in VHDL 2008

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Exercise 2

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• Use the T-FF code shown to create a 2-bit counterLIBRARY ieee; USE ieee.std_logic_1164.all;

entity t_ff is port(T, clk, rst: in std_logic; q: out std_logic); end entity;

architecture behave of t_ff is signal temp: std_logic; begin process(clk,rst) begin if rst = '1' then temp <= '0'; else if rising_edge(clk) then if T = '1' then temp <= not temp; end if; end if; end if; end process; q <= temp; end architecture;

TESTBENCH

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Testbench• Testbenches are used to test the design

in a programmatic way• Testbenches can apply the same set of

tests on different abstraction levels of the design

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Is my design functioning correctly?

Testbench

UUT Tester

Testbench

UUT

Stimulusgenerators

& Monitors

• Testbench is used to:– Generate stimulus & apply it to the entity

under test– Compare output responses against expected

values

• Stimulus generators & monitors can be encapsulated in a tester block

Stimulus Generation• We have seen in “module 3”* how to use “wait” statements to generate

waveforms & counter patterns• One other way to generate a waveform is the “after” keyword

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*Module 3: Write More Complex Models* Delays are not synthesizable

a <= '1' , '0' after 10 ns, '1' after 25 ns, '0' after 30 ns;

Example 9:

• The “after” keyword can also be used to model delays*

b <= a after 15 ns;Example 10:

Stimulus Generation

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Entity and_tb is -- do we need ports here? End entity;

LIBRARY ieee; USE ieee.std_logic_1164.all; architecture waveform of and_tb is --component declaration of the DUT component AND_gate port (a : in std_logic; b : in std_logic; c : out std_logic); end component; -- signal declaration signal x, y, z : std_logic; Begin x <= '0' , '1' after 40 ns; y <= '0' , '1' after 20 ns, '0' after 40 ns, '1' after 60 ns;

uut : AND_gate PORT MAP ( a => x, b => y, c => z ); End architecture;

Testbench

ANDStimulus

generators

Example 11: A Simple stimulus generation example for an “AND” gate testbench

Monitors• One way to monitor & report outputs is using

assertions

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assert <condition> report <message> severity <level>;

Syntax:

• An assertion statement checks that a specified condition is true and reports a message if it is not.

• When the specified condition is false, the ASSERT statement triggers and the report is issued in the simulation console– severity levels

– Note -- relays information about conditions to the user– Warning -- alerts the user to conditions that are not expected, but not fatal– Error -- relays conditions that will cause the model to work incorrectly– Failure -- stops the simulation

assert not ((s='1') AND (r='1')) report "Set and Reset are both 1" severity ERROR;

Example 12:

Testbench

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Entity and_tb isEnd entity;

LIBRARY ieee; USE ieee.std_logic_1164.all; architecture waveform of and_tb is component AND_gate port (a : in std_logic; b : in std_logic; c : out std_logic); end component; signal x, y, z : std_logic; Begin x <= '0', '1' after 40 ns; y <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns;

uut : AND_gate PORT MAP ( a => x, b => y, c => z );

assert not (z = '1') report "Now we have completed our testing" severity failure; -- Monitor the occurrence of a '1' and abort process begin -- Monitor the inputs outputs relation and abort in case of failure wait on x, y for 1 ns; assert (z = (x and y)) report "Error found, The output port Z is not the ANDing of inputs a and b“ severity failure; end process;End architecture;

Example 13: A Simple testbench example for an “AND” gate testbench

Testbench

ANDStimulus

generators Monitors

Testbench• Let’s create a testbench for the shown ALU and test all operations with

all operand values

Example 14: ALU Design Unit

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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY alu IS port (cin : in std_logic; sel : in std_logic_vector(3 downto 0); a, b : in std_logic_vector(7 downto 0); cout : out std_logic; y : out std_logic_vector(7 downto 0) ); END ENTITY alu; ARCHITECTURE behav OF alu IS signal result : std_logic_vector(8 downto 0); BEGIN y <= result (7 downto 0); cout <= result (8); process (cin, sel, a, b) begin case (sel) is when X"0" => result <= ('0' & a) + ('0' & b) + cin; when X"1" => result <= ('0' & a) - ('0' & b) - cin; when X"2" => result <= ('0' & a) and ('0' & b); when X"3" => result <= ('0' & a) or ('0' & b); when X"4" => result <= ('0' & a) xor ('0' & b);

when X"5" => result <= not('1' & a) ; when X"6" => result <= ('1' & a) nand ('1' & b); when X"7" => result <= ('1' & a) nor ('1' & b); when X"8" => result <= ('1' & a) xnor ('0' & b); when X"9" => if (a > b) then result(8) <= '1'; result(7 downto 0) <= (others => 'Z'); else result(8) <= '0'; result(7 downto 0) <= (others => 'Z'); end if; when X"A" => if (a < b) then result(8) <= '1'; result(7 downto 0) <= (others => 'Z'); else result(8) <= '0'; result (7 downto 0) <= (others => 'Z'); end if; when X"B" => if (a >= b) then result(8) <= '1'; result(7 downto 0) <= (others => 'Z'); else result(8) <= '0'; result(7 downto 0) <= (others => 'Z'); end if; ...

Testbench

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when X"C" => if (a <= b) then result(8) <= '1'; result(7 downto 0) <= (others => 'Z'); else result(8) <= '0'; result(7 downto 0) <= (others => 'Z'); end if; when X"D" => if (a = b) then result(8) <= '1'; result(7 downto 0) <= (others => 'Z'); else result(8) <= '0'; result(7 downto 0) <= (others => 'Z'); end if; --when X"E" => --; --when X"F" => --; when others => result <= (others => 'Z'); end case; end process; END ARCHITECTURE behav;

TestbenchTestbench

LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY alu_tb IS END alu_tb;

ARCHITECTURE struct OF alu_tb IS SIGNAL cin : std_logic; SIGNAL sel : std_logic_vector(3 downto 0); SIGNAL a : std_logic_vector(7 downto 0); SIGNAL b : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; SIGNAL y : std_logic_vector( 7 downto 0 ); COMPONENT alu PORT ( cin : IN std_logic; sel : IN std_logic_vector(3 downto 0); a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); cout : OUT std_logic; y : OUT std_logic_vector(7 downto 0)); END COMPONENT; COMPONENT alu_tester PORT (cin : OUT std_logic; sel : OUT std_logic_vector(3 downto 0); a : OUT std_logic_vector(7 downto 0); b : OUT std_logic_vector(7 downto 0); cout : IN std_logic; y : IN std_logic_vector( 7 downto 0 )); END COMPONENT; …

BEGIN UUT : alu PORT MAP ( cin => cin, sel => sel, a => a, b => b, cout => cout, y => y ); Tester : alu_tester PORT MAP ( cin => cin, sel => sel, a => a, b => b, cout => cout, y => y ); END struct;

Example 14: ALU Testbench

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TestbenchLIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all; ENTITY alu_tester IS PORT (cin : OUT std_logic; sel : OUT std_logic_vector(3 downto 0); a : OUT std_logic_vector(7 downto 0); b : OUT std_logic_vector(7 downto 0); cout : IN std_logic; y : IN std_logic_vector( 7 downto 0 ));END alu_tester; ARCHITECTURE all_tester OF alu_tester IS signal temp : std_logic_vector(20 downto 0) := (others => '0'); BEGIN -- generate the stimulus temp <= temp + 1 after 20 ns; -- drive the dut i/p signals cin <= temp(0); b <= temp(8 downto 1); a <= temp(16 downto 9); sel <= temp(20 downto 17); -- now start monitoring whenever the stimulus changes process begin wait for 2 ns; case (temp(20 downto 17)) is when X"0" => assert ((cout & y) = conv_std_logic_vector((conv_integer(temp(16 downto 9)) + conv_integer(temp(8 downto 1)) + conv_integer(temp(0))),9)) report "Addition failed!!" severity failure; when X"1" => assert ((cout & y) = conv_std_logic_vector((conv_integer(temp(16 downto 9)) - conv_integer(temp(8 downto 1)) - conv_integer(temp(0))),9)) report "Subtraction failed!!" severity failure; …

when X"2" => assert (cout = '0' and y = (temp(16 downto 9) and temp(8 downto 1))) report "AND operation failed!!" severity failure;when X"3" => assert (cout = '0' and y = (temp(16 downto 9) or temp(8 downto 1))) report "OR operation failed!!" severity failure; when X"4" => assert (cout = '0' and y = (temp(16 downto 9) xor temp(8 downto 1))) report "XOR operation failed!!" severity failure;when X"5" => assert (cout = '0' and y = not (temp(16 downto 9))) report "NOT operation failed!!" severity failure;when X"6" => assert (cout = '0' and y = (temp(16 downto 9) nand temp(8 downto 1))) report "NAND operation failed!!" severity failure;when X"7" => assert (cout = '0' and y = (temp(16 downto 9) nor temp(8 downto 1))) report "NOR operation failed!!" severity failure; when X"8" => assert (cout = '0' and y = (temp(16 downto 9) xnor temp(8 downto 1))) report "XNOR operation failed!!" severity failure;when X"9" => assert (y = "ZZZZZZZZ") report "Output y should be equal to Z" severity failure; if (temp(16 downto 9) > temp(8 downto 1)) then assert (cout = '1') report "Relational operation greater than failed!!" severity failure;…

Example 14: ALU Tester

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Testbench else assert (cout = '0') report "Relational operation greater than failed" severity failure; end if; when X"A" => assert (y = "ZZZZZZZZ") report "Output y should be equal to Z" severity failure; if (temp(16 downto 9) < temp(8 downto 1)) then assert (cout = '1') report "Relational operation less than failed!!" severity failure; else assert (cout = '0') report "Relational operation less than failed" severity failure; end if; when X"B" => assert (y = "ZZZZZZZZ") report "Output y should be equal to Z" severity failure; if (temp(16 downto 9) >= temp(8 downto 1)) then assert (cout = '1') report "Relational operation greater than or equal failed!!" severity failure; else assert (cout = '0') report "Relational operation greater than or equal failed" severity failure; end if; …

when X"C" => assert (y = "ZZZZZZZZ") report "Output y should be equal to Z" severity failure; if (temp(16 downto 9) <= temp(8 downto 1)) then assert (cout = '1') report "Relational operation less than or equal failed!!" severity failure; else assert (cout = '0') report "Relational operation less than or equal failed" severity failure; end if; when X"D" => assert (y = "ZZZZZZZZ") report "Output y should be equal to Z" severity failure; if (temp(16 downto 9) = temp(8 downto 1)) then assert (cout = '1') report "Relational operation equal failed!!" severity failure; else assert (cout = '0') report "Relational operation equal failed" severity failure; end if; --when X"E" => -- when X"F" => when others => assert ((cout & y) = "ZZZZZZZZZ"); end case; wait on temp; end process; -- Stop the simulation when temp is all 1s assert (temp /= ('1' & X"FFFFF")) report "Simulation ended!!" severity failure; END ARCHITECTURE all_tester;

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GENERATE STATEMENT

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Generate Statement

– For-generate (Iterative mode)• <Label> mandatory to identify the generate statement• <Range> loop range

– If-generate (Conditional mode)• <Label> mandatory to identify the generate statement• <condition> Boolean expression that evaluates to

either TRUE or FALSE• "elsif" and "else" branches were added in VHDL 2008*

– Case-generate* (Conditional mode)• <Label> mandatory to identify the generate statement• <choice> constants representing one of possible

<expression> values

<Label>: for n in <range> generate -- list of concurrent statementsend generate <Label>;

Syntax:

<Label>: if <condition> generate -- list of concurrent statementselsif <condition> generate -- list of concurrent statementselse generate -- list of concurrent statementsend generate <Label>;

Syntax:

<Label>: case <expression> generate when choice => concurrent statements when choice => concurrent statementsend generate <Label>;

Syntax:

*VHDL 2008 is not yet supported by all tools in the market 32VHDL 360 ©

• A concurrent statement used for iterative or conditional logic inference

Generate StatementExample 15: for-generate

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY gent_exp1 IS port(A, B, C: in std_logic_vector(3 downto 0); G: out std_logic_vector(3 downto 0)); END ENTITY;

ARCHITECTURE behave OF gent_exp1 IS component or_n generic (N : integer := 5); port(A : in std_logic_vector(N-1 downto 0); Z : out std_logic ); end component;

signal temp1: std_logic_vector(3 downto 0); type myType is array (3 downto 0) of std_logic_vector(1 downto 0); signal temp2: myType; BEGIN

ex1: for j in 0 to 3 generate temp1(j) <= A(j) and B(j); temp2(j) <= temp1(j) & C(j); U: or_n generic map(N => 2) port map (temp2(j), G(j)); end generate ex1;

END ARCHITECTURE;

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Generate StatementExample 16:

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY gent_exp3 IS port(A, B: in std_logic_vector(3 downto 0); G: out std_logic_vector(3 downto 0)); END ENTITY; ARCHITECTURE behave OF gent_exp3 IS BEGIN

L1: for j in 0 to 3 generate L2: if j = 2 generate G(j) <= A(j) xor B(j); end generate L2;

L3: if j /= 2 generate G(j) <= A(j) nor B(j); end generate L3; end generate L1;

END ARCHITECTURE;

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Generate StatementExample 17:

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY gent_exp4 IS port(A, B: in std_logic_vector(3 downto 0); G: out std_logic_vector(3 downto 0)); END ENTITY;

ARCHITECTURE behave OF gent_exp4 IS BEGIN

ex1: for j in 0 to 3 generate L1: case j generate when 0 | 2 => -- if j = 0 or j = 2 G(j) <= A(j) and B(j); when others => G(j) <= A(j) nand B(j); end generate L1; end generate ex1;

END ARCHITECTURE;

VHDL 2008 is not yet supported by all tools in the market

35VHDL 360 ©

Exercise 3• Create the n-bit shift register shown below

…

VHDL CONFIGURATIONS

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Configurations• Why do we need Configurations?

– VHDL design units are organized in libraries. Units in different libraries can have the same name but with different implementation. Designers can specify which one is needed via configurations

– VHDL allows designers to have the component name to be different than the entity name. Designers need a configuration to specify the bindings

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Lib1

ALU

cntrlr

du12

arch struct

fsm

behav rtl sim

Lib2

CPU

cache

ALU

sim syn

model

gte fastsim rtl

Lib3

ALU

Mem

cntrlr

arch

behave

sim synth

Which ALU should I use?

How to bind it in my design?

Configurations• VHDL offers different ways to specify bindings

39VHDL 360 ©

configuration <config_name> of <entity_name> is for <arch_name> [configuration_spec_statement] ; … end for;end configuration;

Syntax:– Configuration Design Unit

• Useful when the binding of component instances needs to be deferred to later time

– Configuration Specification Statement• Defined in the declarative region of the block

in which the component instance is created• <lib> library name where the entity resides• <ent> entity name to be used• <arch> architecture to be used for <ent>• <config> configuration design unit

for <inst_name | all | others> : <comp_name> use entity <lib>.<ent> (<arch>) [generic_map_aspect] [port_map_aspect] ;end for;

Syntax:

for <inst_name | all | others> : <comp_name> use configuration <lib>.<config>;end for;

Entity adder2 is port(a, b: in bit_vector( 1 downto 0); cin : in bit; cout: out bit; z : out bit_vector(1 downto 0)); End entity; Architecture arch of adder2 is signal t: bit; Component fa port(a ,b, c: in bit; d, e : out bit); end component; for all : fa use entity work.fulladder(expr) port map (X => a, Y => b, Z => c, S => d, C => e); Begin f1: fa port map (a => a(0), b => b(0), c => cin, d => t, e => z(0)); f2: fa port map (a(1), b(1), t, z(1), cout); End arch;

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Example 18: Using Configuration Specification statement

Configurations

ENTITY fullAdder IS PORT(X, Y, Z : IN bit; S : OUT bit; C : OUT bit); END fullAdder; ARCHITECTURE expr OF fullAdder IS signal temp : bit;BEGIN temp <= X XOR Y; S <= temp XOR Z; C <= (X AND Y) OR (Z AND temp); END expr;

*more on libraries in the next modules

library* name where the design unit resides

configuration adder_config of my_add3 is for arch -- Binding f1 to entity fulladder for f1 : fa use entity work.fulladder(expr); end for; -- Binding f2 to another entity cla_fad for f2 : fa use entity work.cla_fadd(behave); end for; -- for other instances of fa use another architecture of fulladder for others : fa use entity work.fulladder(expr2); end for; end for; end configuration;

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Example 19: Using Configuration Design Unit

Configurations

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Configurations• Example 20: In a design house, they need to create a test suite for the

ALU; the purpose was to reduce the run time & to test specific aspects in the ALU rather than the whole operation. To make it generic & minimize the coding they use configurations to bind different architectures to the same tester unit as shown below– The alu_tester entity will have several architectures each one tests a specific aspect in

the alu– The alu_tb instantiates the alu DUT & the alu_tester

Entities & their architecturesalu

alu_tb

alu_tester

behav

struct

arithrelational logical

Tests using Configurations

all_test

arith_test

rltn_test

lgc_test

crnr_cs_test

bug_fixes_testcrnr_cases

– Several VHDL configurations are created, each represents a test and binds a specific architecture to the alu_tester entity

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ConfigurationsTest1 : Testing arithmetic Operations

configuration arith_test of alu_tb is for struct for all : alu use entity work.alu(behav); end for; for all : alu_tester use entity work.alu_tester(arith); end for; end for; end configuration arith_test;

Test 2 : Testing Logical Operations Test 3 : Testing Relational Operations

configuration lgc_test of alu_tb is for struct for all : alu use entity work.alu(behav); end for; for all : alu_tester use entity work.alu_tester(logical); end for; end for; end configuration lgc_test;

configuration rltn_test of alu_tb is for struct for all : alu use entity work.alu(behav); end for; for all : alu_tester use entity work.alu_tester(relational); end for; end for; end configuration rltn_test ;

Example 20 (cont.):

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