VAX 8600, MC 68040,

SUN MICROSYSTEM SPARC,

&

SUPERSCALAR RISC

PROCESSOR

Presentation by

PRIYODARSHINI DHAR

IIEST Shibpur, M.Tech CST 2014-16

Introduction to

VAX 8600

VAX : Virtual Address Extension (32-bit extension of the older 16-bit early versions)

Manufacturer: Digital Equipment Corporation (DEC).

First Model: VAX-11/780

VAX is a family of popular and influential computers implementing VAX Instruction Set

Architecture.

The VAX 8600, ("Venus“,Oct 1984), had increased performance(4.2 times VAX-11/785),

I/O capacity, and included macro-pipelining and ECL (emitter coupled logic).

Cycle Time of VAX 8600 CPU: 80 ns(12.5 MHz)

Implements CISC architecture with micro programmed control.

300 instructions with 20 different addressing modes.

Two functional units for concurrent execution of instruction of integer and floating point

instructions.

16GPRs

Pipeline is built with six stages.

The instruction unit prefetches and decodes and handles branching operations.

A transistor look aside buffer (TLB) is used in memory for fast generation of the physical

address from the virtual address

Fig: The VAX

8600 CPU

CPU’s Major

Logical Section

E

Box

I

Box

M

Box

F

Box

ALU

Barrel

Shifte

r

16K Data

Cache

• Adder

module,

• Multiplier

module

(Executes all

instructions)

(fetches

and

decodes

instruct

ion)

( Control

memory & I/O,

Translate

Virtual addr to

physical addr.)

(accelerated

floating inst. ,

multiplication,

division)

SBI- Synchronous Backplane Interconnect

FEATURES :

• The MC68040 is a 0.8 µm HCMOS microprocessor containing more than 1.2 million

transistor.

• It's implemented over 100 instructions using 16 general-purpose register.

• 4kb of data cache and 4kb of instruction cache with separate memory management

unit (MMU's) supported by a address translation cache.

• Support 18 addressing modes, integer unit is organized in six stages of instruction

pipeline, floating point consist of 3 stages.

• Separate instruction and data buses are provided both addressing and data buses are of

32bits width.

• The complete memory unit is provided with a virtual demand paged operating system.

The CPU of MC 68040*ATC- Address Translation

Cache. (TLB)

• SPARC ("scalable processor architecture")

• Uses RISC instruction set architecture (ISA)

• Developed by Sun Microsystems

• Designed for optimizing compilers and easy pipelined hardware implementations.

• Exceptionally high execution rates(MIPS) and short time-to-market development

schedules.

• 3 major revisions to the SPARC architecture

- SPARC-V7, 32bit, 1986

- SPARC-V8, 32bit, 1990

- SPARC-V9, 64bit, 1993

ISA contains 69 basic instructions. 8 Global Registers

Runs procedure 32 bit Register

24 Window Register

Ins, OUTs, Locals

Shared among procedures Locally addressable by

each procedures

The calling procedure passes parameters to the called procedure via its Outs registers which are the Ins

Register of the called procedure.

Window of the

currently running

procedure

Current Window Pointer

.

Active

Window

A window invalid mask is used to indicate which

window is invalid .

The trap base register servers as a pointer to a trap

handler.

FEATURES:

Most important feature :-

Overlapped Register Window introduced by Berkeley RISC architecture.

It divides the register file into small groups ,called windows and each procedure uses one

window.

Adjacent windows can pass parameters and hence called overlapped.

8 overlapping windows (64

local registers ,64 overlapped

reg.) and 8 global registers .

Total = 136 reg. each 32 bit

Fig: Cypress CY7C601 SPARC processor

Superscalar processor is a multiple issue processor .

RISC – Reduced Instructions Set Computer.

RISC CPUs like Intel i960CA were the first microprocessors to use the superscalar concept.

It has 5 stage pipeline : fetch, dispatch, issue, execute and complete.

It has 3 execution units:

a) simple arithmetic and logic ( includes branch address computation)

b) complex arithmetic (multiply and divide), and

c) memory data access (includes a simple ALU)

All program memory and data memory busses are 16 bits wide.

The processor fetches at most one instruction but may issue up to 3 instructions at a

time for execution.

It has three functional units – branch processor, fixed-point unit and floating-point unit.These three can operate in parallel .

* The fixed point processor uses non privileged instructions

VAX 8600 MC 68040 SPARC SUPERSCALAR

RISC

CISC CISC RISC RISC

300 instructions

20 address mode

Plus 100 instr.

18 address mode

69 basic instr.

Few address mode

Few instr.

6 stage pipeline 6 stage pipeline- integer

unit, 3 stage - floating

point unit

4 stage pipeline 5 stage pipeline

16 GPRS 16GPRS (8 for addr., 8

for data)

40 to 520 GPRS 16GPRS

TLB used for 1st

time- 64 entries

TLB size- 64 entries Software Managed

TLB

Reorder Buffer- 32

entries.

Property:

Virtual Addressing

Concurrent

execution

1.2 Million Transistors .

Faster processor than

VAX, uses High Speed

CMOS

Exceptionally high

MIPS.

Overlapped Register

Window

Multi issue processor.

A short cycle time and

a low cycles-per-

instruction (CPI) ratio

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