SATA Protocol

Storage Interfaces

SATA

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Where ATA Resides in the PC Architecture

CD

HD

SATA

SATA

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History of Parallel ATA

Generation Standard Year Speed Key featuresIDE 1986 Pre-standard

ATA 1994 PIO modes 0-2, multiword DMA 0

EIDE ATA-2 1996 16 MB/secPIO modes 3-4,

multiword DMA modes 1-2, LBAs

ATA-3 1997 16 MB/sec SMART

ATA/ATAPI-4 1998 33 MB/secUltra DMA modes 0- 2, CRC, overlap, queuing,

80-wireUltra DMA

66 ATA/ATAPI-5 2000 66 MB/sec Ultra DMA mode 3-4Ultra DMA

100 ATA/ATAPI-6 2002 100 MB/sec Ultra DMA mode 5, 48-bit LBA

Ultra DMA 133 ATA/ATAPI-7 2003 133 MB/sec Ultra DMA mode 6

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• Bandwidth limited to 133 MB/s• Cyclic Redundancy Checking (CRC) for data but not commands• Support attachment of 2 devices per cable• Small switch or jumper for drive selection• High pin count on signaling interface adds cost to cables,

connectors and components• Wide cables are cumbersome and inhibit airflow making cooling

more difficult and expensive• Connectors hard to insert and remove• Prone to bent pins

Limitations of Parallel ATA

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Benefits of Serial Based Storage• Frame-based transaction protocol (OSI model)

– Small, inexpensive connectors and cables • Legacy support - ATA stack in SATA• Ease of integration – cabling, jumpers• Point-to-point connections (expanders, port multipliers)• Pathway to higher data rates; 6 Gb/s is on the roadmap• Improve bandwidth

– Wide ports permit several simultaneous connections, allowing for link aggregation (SAS)

• Lower cost

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PATA and SATA Comparisons

Source: SATA Working Group

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History of serial ATA

Generation Standard Year Speed Key featuresSerial ATA ATA/ATAPI-7 2002 150 MB/sec

Serial ATA II ATA/ATAPI-8 2005 300 MB/sec Native Command Queuing

Serial ATA III ATA/ATAPI-9? ? 600 MB/sec

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SATA Technology Today• SATA has been the most successful recent new storage interface

– It has been a multi billion dollar market for several years– In 2006 over 300 million hard disk drives will have SATA interfaces

• 400 Million Shipped in 2005 (source: Gartner)– Market Leader – Seagate 40% share– SATA has also made its appearance in solid state disks, DVD drives and

tape drives• In Desktop, notebooks, Consumer Products - DVR• In the Enterprise! (thanks to STP)

– Challenges SAS in the enterprise– Non-critical data– Near-line and offline storage– FC, SAS, and SATA will co-exist offering consumers with a choice of flexible

storage options at varying price-points

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SATA Layer Architecture

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SATA Layer Architecture

Connectivity

• Serial ATA is point-to-point topology

– Hosts can support multiple devices but requires multiple links

– 100% available link bandwidth

– Failure of one device or link does not affect other links

Link Characteristics

• SATA uses full-duplex links– Protocol only permits frame transfer in one

direction at a time– Each link consists of a transmit and a receive pair

• SATA uses low voltage levels– Nominal voltage +/-250mV differential

Power Management

• SATA has – Phy Ready – Capable of sending and receiving data. Main

phase locked loop are on and active– Partial – Physical layer is powered but in a reduced state.

Must be able to return to Phy Ready within 10 us.– Slumber – Physical layer is powered but in a reduced state.

Must be able to return to Phy Ready within 10 ms.

• ATA also defines IDLE, STANDBY, and SLEEP

• Necessary for newer laptop & mobile devices

SATA Architectural ModelDevice Control Software

Buffer Memory

DMA management

Serial digital transport control

Serial digital link control

Serial physical interface

Device Layers

Host Control Software

Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical

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Physical Layer - Summary

• Defines the connectors and cabling used to transmit and receive SATA signaling and data information

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Physical Layer - SATA Device Connector

Serial ATA signal connector(pin S1)

Appearance of Serial ATA Connectors(Drawing courtesy of Molex)

parallel ATA signals 4-pin power

3.5”Parallel

power signal2.5"

SerialDevice connector sizes and locations

Device plugconnector

Host receptacleconnector

power signal

3.5”Serial

Legacy Power(vendor specific)

Serial ATA power connector(pin P1)

(5.25” form factor also defined for devices like tape drives and DVDs)in comparison…

Graphics courtesy of the SCSI Trade Association and HP

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Physical Layer - SATA Cabling

Graphics courtesy of Molex

SATA to SATA (1), CO, STThe most common

internal for SATA (and

SAS); 1 meter

maximum length

SATA PowerTo provide

legacy power support

eSATA Power (2m)

External SATA;

designed for use with external storage

products; bypasses the

USB route

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Physical Layer - Summary

• OOB (Out of Band) Signaling• Speed Negotiations• Byte/dword synchronization

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Phy Layer - (OOB)• Most primitive level of communication is OOB • They are pattern of idle times and burst times, distinguished

by length of time between idles– Idle time (and negation time) are when there are voltage levels

• Also known as DC idle– Burst time is during the transmission of the ALIGN primitives– Since byte sync has not occurred yet, the actual bits sent are not

relevant – 40 bits will always been detected and consider an ALIGN

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Phy Layer - (OOB)• COMINIT/COMRESET and COMWAKE are bursts of 6 ALIGN (0) separated by

IDLEs• Length of the idle time determines the type of OOB signal• Senders sends 6 – receiver only need to detect 4 (per spec)• COMRESET are sent by hosts• COMINIT are sent by devices

OOB Signal Idle Time Negation TimeCOMWAKE 55 to 175 ns > 175 nsCOMINIT/COMRESET 175 to 525 ns > 525 ns

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Phy Layer - OOB COMWAKE

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Phy Layer - OOB COMINIT/COMRESETElectrically, COMINIT and COMRESET appear exactly the same, the only difference is the direction in which the ALIGN patterns are being sent. Host to device: COMRESET; device to host: COMINIT

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SATA Power-On Initialization

• Starts with the assertion of hardware reset• Begins Out-Of-Band (OOB) signaling• Allows host and device to initialize link

communications• Ends with successful transmission of ALIGN

primitives• Then speed negotiations

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Power-On Initialization ProcessHost Device

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SATA Power-On Initialization

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Error SituationExample: Host and Device are unable to establish a

connection. Continuous transmission errors are seen fromboth the Host and Device.

No COMINITs present. Indicates problem with Device connection

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Primitive HandshakingSender Receiver

X_RDYR_RDY

SOFFrame

.

.

.EOF

R_IP

R_OKWTRM

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Primitive HandshakingExample: Host sends commands but commands

are not completed

Trace indicates that Host is not properly handling primitive handshaking and is not receiving frames

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SATA Speed Negotiation

• Fast to slow progression– SATA target device sends ALIGN primitives at the

fastest supported rate– Waits for host to reply with ALIGNs– If no reply after sending 2048 (i.e., the host

doesn’t support this speed), step down to next slower speed and try again

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SATA Speed Negotiation• When host replies with ALIGNs, it has locked at the current

frequency and negotiation is complete

Speed Negotiation

Out of Band

• Part of normal power on sequence

• Allows host to issue a device hard reset

• Allows device to request a hard reset

• Brings device out of low power state

Out of Band Signals (cont.)

• COMWAKE– Can be originated by either host or device– Used as final phase of OOB initialization– Used to bring out of low power & test states

• Exit Partial• Exit Slumber• Exit BIST

Out of Band Signal Forms

COMRESET / COMINIT

COMWAKE

106.7 ns

106.7 ns 106.7 ns

320 ns

Out of Band Signaling Protocol

COMRESET

COMWAKE

COMINIT

COMWAKE

Host Device

SATA Port Model

Clock & Data Recovery

Serializer

Deserializer

Analog Front End

OOB Detect

COMRESET / COMINIT

COMWAKE

Data Out

RX Clock

Port Control

Logic

Tx ClockAlign Generator

Data In

Phy ResetPhy Ready

SlumberPartial

SPD ModeSystem Clock

SPD Select

Tx +

Tx -

Rx -

Rx +


Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical

Link Layer

• 8b / 10b encoding• Scrambles and descrambles data and control

words• Converts data from transport layer into frames• Conduct CRC generation and checking• Provides frame flow control

Encoding Concepts

• All 32 bit Dwords are encoded for SATA– 32 bits data = 40 bits of transmission

• Provides sufficient transition density– Guarantees transition (0s and 1s) even if data is

0x00 or 0xFF

• Provides an easy way to detect transmission error

Current Running Disparity (CRD)

• As each character is encoded a count is maintained of the number of 0’s and 1’s being transmitted– More 1’s than 0’s give positive disparity– More 0’s than 1’s gives negative disparity– Same number gives neutral disparity

• Only valid values of CRD are -1 and 1– Any other value indicates that a transmission error has

occurred

CRD+ & CRD- Encoded Characters

0 0 1 1 1 1 1 1

1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1

8b Character 0x3F

This 10b Character transmitted when CRD negative

This 10b Character transmitted when CRD positive

This character

6 ones

4 zeros

Disparity +2

This character

4 ones

6 zeros

Disparity -2

SATA Primitives

• Convey real-time state information

• Control transfer of information between host and device

• Provide host/device coordination

SATA Primitives

• ALIGN – Speed negotiation and at least every 256 Dword

• SYNC – Used when in idle to maintain bit synchronization

• CONT – Used to suppress repeated primitives

SATA Primitives

• X_RDY

• R_RDY

• R_IP

• R_OK

• R_ERR

SOF

EOF

HOLD

HOLDA

SATA Frame Structure

• All SATA frames consist of:– A start of frame (SOF) delimiter– A payload – transport layer information– A Cyclic Redundancy Check (CRC)– An end of frame (EOF) delimiter

SOF CRC EOFPayload Data

Link Layer Protocol (1)

SYNC SYNC SYNC SYNC SYNC SYNC


Host Device


SYNC SYNCX_RDYX_RDYX_RDYX_RDY


Host Device


X_RDYX_RDYX_RDYX_RDYX_RDYX_RDY

SYNC R_RDYR_RDYR_RDYR_RDY SYNC

Host Device


X_RDYX_RDY SOF DATA DATA DATA

R_RDY R_RDYR_RDYR_RDYR_RDYR_RDY

Host Device


DATA DATA DATA DATA DATA DATA

R_RDY R_IP R_IP R_IP R_IPR_RDY

Host Device


DATA DATA CRC EOF WTRM WTRM

R_IP R_IP R_IP R_IP R_IP R_IP

Host Device


CRC EOF WTRM WTRM WTRM WTRM

R_IP R_IP R_IP R_IP R_IP R_IP

Host Device


WTRM WTRM WTRM WTRM WTRM WTRM

R_IP R_OK R_OK R_OK R_OK R_IP

Host Device


WTRM WTRM SYNC SYNC SYNC SYNC

R_OK R_OK R_OK R_OK R_OK R_OK

Host Device

Link Layer Protocol (last)


R_OK SYNC SYNC SYNC SYNC R_OK

Host Device


Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical

Transport Layer

• Responsible for the management of Frame Information Structures (FIS)

• At the command of Application layer:– Format the FIS– Make frame transmission request to Link layer– Pass FIS contents to Link layer– Receive transmission status from Link layer and

reports to Application layer

Frame Information Structure (FIS)

• A FIS is a mechanism to transfer information between host and device application layers

– Shadow Register Block contents– ATA commands– Data movement setup information– Read and write data– Self test activation– Unique FIS Type Code

FIS types

FIS TYPE CODE

Description Direction

27h Register transfer host to device H D34h Register transfer device to host D HA1h Set Device bits D H39h DMA Activate D H41h DMA Setup D H58h BIST Activate D H5Fh PIO Setup D H 46h Data D H

Register – Host to Device FIS

Byte 3 Byte 2 Byte 1 Byte 0

Dword 0 Features Command Reserved FIS TYPE (27h)

Dword 1 Dev/Head Cyl High Cyl Low Sector Number

Dword 2 Features (exp)

Cyl High (exp)

Cyl Low (exp)

Sector Number

Dword 3 Control Reserved Sector Count

Sector Count

Dword 4 Reserved Reserved Reserved Reserved

BIST Activate FIS


0 Reserved [ TASLFPRV ] Reserved FIS Type 58h

1 Data [31:24] Data [23:16] Data [15:8] Data [7:0]

2 Data [31:24] Data [23:16] Data [15:8] Data [7:0]

T - Far end transmit only – transmit Dwords defined in words 1 & 2A - No ALIGN transmission (valid only with T)S - Bypass scrambling (valid only with T)L - Far end retimed loopback with ALIGN insertionF - Far end analog loopbackP - Transmit primitives defined in words 1 & 2 of the FISR - ReservedV - Vendor Unique Test Mode – other bits undefined

Data FIS


Dword 0 Reserved Reserved Reserved FIS TYPE (46h)

Dword 1

N Dwords of DataMinimum 1 Dword

Maximum 2048 Dwords

Dword 2

. . .

Dword N


Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical

Command / Application Layer

• Defined using a series of state diagrams– Register H D – Register D H– DMA data in– DMA data out

• Host command layer may be the same but may only support legacy commands

Compatibility SATA

• PCI SATA controller card

• Windows 2000/XP/2003/Vista

• Integrated SATA CRC on both levels of command and data packets

Engineering

SATA Protocol