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Combinational Logic Circuit
Yong Heui Cho @ Mokwon University
Some of slides are referred to:[1] 전재욱 , 논리회로 설계실험 , 성균관대학교 .[2] Imran Waris, Digital and Logic Design, slideshare, 2014.
2
Basic Computer Design
2. Introduction to Arduino
3. Basic Computer Archi-tecture4. Combinational Logic Circuit5. Sequential Logic Circuit
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Analog & Digital
3
V
T0
V
T0
Analog ( 유사성 ) Digital ( 숫자 집합 )
- Continuous @ time and amplitude- Precise representation- Sensitive to noise- Old theory
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
- Discrete @ time or amplitude- Approximate presentation- Robust to noise- Modern theory
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Analog
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Input Signal Output Signal
arithmetic sum
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Digital
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Input Signal Output Signal
logical sum□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Binary System○ Binary System
– 0 or 1– Notation: 10001001(2)
– Bit (binary digit)– Byte = 8 bits
○ Decimal to Binary Conversion
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65232 … 116 … 008 … 004 … 002 … 001 … 0
22222
1000001128 64 32 16 8 4 2
10 1 0 0 0 0 0 1Binary :
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
7 7
Power of 2
□ Courtesy to Imran Waris, Digital and Logic Design, slideshare.
8 8
Decimal & Hexadecimal
□ Courtesy to Imran Waris, Digital and Logic Design, slideshare.
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Boolean Algebra• Logical Sum : +
► A + B = Y 0 + 0 = 0 0 + 1 = 1 1 + 1 = 1
• Logical Product : •► A • B = Y
0 • 0 = 0 0 • 1 = 0 1 • 1 = 1
• Logical Not : ~, ‾, n,’► A ( ~A, nA, A’) = Y
0’ = 1 1’ = 0
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A B Y0 0 00 1 11 0 11 1 1
Truth Table
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Venn Diagram
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XY
XY XY
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
John Venn
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De Morgan Law
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A + B = A • B
A • B = A + B
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
Augustus De Morgan
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Logic Signals
□ Courtesy to Imran Waris, Digital and Logic Design, slideshare.
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Buffer & NOT Gate
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NOT Gate Buffer
Input Out-put
0 11 0
Input Output Input Output
Input Out-put
0 01 1
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Analog NOT Gate Circuit
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Input
Output
B
C
E
B = 0
B = 1
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
A NOT gate is a transistor (TR)!
15 15
Gate?• Logic gate– Physical device implementing a Bool-
ean function• “Gate” is the terminal name of a
vacuum tube.
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AND & NAND Gate
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AND Gate NAND (NOT + AND) Gate
Input AInput B Output
Input AInput B Output
Input A
Input B
Out-put
0 0 00 1 01 0 01 1 1
Input A
Input B
Out-put
0 0 10 1 11 0 11 1 0
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Analog AND Gate Circuit
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BC
E=> B
C E
Output
Input A Input B
< TR > < Switch >
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
An AND gate is series wire connection!
+5 [V]
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OR & NOR Gate
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OR Gate NOR (NOT + OR) Gate
Input A
Input BOutput
Input A
Input BOutput
Input A
Input B
Out-put
0 0 00 1 11 0 11 1 1
Input A
Input B
Out-put
0 0 10 1 01 0 01 1 0
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Analog OR Gate Circuit
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Input A Input B
Output
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
An OR gate is parallel wire connection!
+5 [V]
20
XOR & XNOR Gate
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XOR (Exclusive OR) Gate XNOR Gate
Input A
Input BOutput
Input A
Input BOutput
Input A
Input B
Out-put
0 0 00 1 11 0 11 1 0
Input A
Input B
Out-put
0 0 10 1 01 0 01 1 1
A ⊙ B = YA B = Y□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Combinational Logic
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Input A
Input B
Input C
Input D
Output
(A+B) (CD) = Output
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
22 22
Classification
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Half Adder
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HalfAdder
Input A
Input B
Sum
Carry
Input A
Input B
Sum Carry
0 0 0 00 1 1 01 0 1 01 1 0 1
0+000
0+101
1+001
1+110
0010011+1000001
1010010
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
HalfAdder
Carry ?
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Circuit of Half Adder
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Input A
Input BSUM
CARRY
(A B) = SUMA • B = CARRY
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Full Adder
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HalfAdder
HalfAdder
Input A
Input B
SUM
CARRYInput C
Input A
Input B
Input C SUM CARR
Y
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
Input A
Input B
Input C SUM CARR
Y
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
26
Circuit of Full Adder
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Carry
Input AInput B
SUM
CarryInput
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
27
Combination of Full Adder
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FullAdder
HalfAdder
FullAdder
FullAdder
FullAdder
FullAdder
FullAdder
FullAdder
A1 B1A2 B2A3 B3A4 B4A5 B5A6 B6A7 B7A8 B8
SUM1SUM2SUM3SUM4SUM5SUM6SUM7SUM8CARRY
10010011+10010001100100100
□ Courtesy to 전재욱 , 논리회로 설계실험 , 성균관대학교 .
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Encoder & Decoder
29 29
Digital Door Lock
