A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis

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AReconfigurableHebbianEigenfilterforNeurophysiologicalSpikeTrainAnalysis.

CONFERENCEPAPER·JANUARY2010

DOI:10.1109/FPL.2010.109·Source:DBLP

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7AUTHORS,INCLUDING:

FeiXia

NewcastleUniversity

94PUBLICATIONS414CITATIONS

SEEPROFILE

AlexYakovlev

NewcastleUniversity

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Availablefrom:FeiXia

Retrievedon:04February2016

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis

Bo Yu1,3, Terrence Mak1,2, Fei Xia1, Alex Yakovlev1, Xiangyu Li3, Yihe Sun3, Chi-Shang Poon4

1School of Electrical, Electronic & Computer Engineering

2Institute of Neuroscience Newcastle University, UK

3Institute of Microelectronic, Tsinghua University, China 4MIT-Harvard Health Science and Technology, MIT, US

2 September 2010

1 20th International Conference on Field Programmable Logic and Applications

Outline

• Background – BMI (Brain Machine Interface)

– Spike Sorting

• Hebbian Eigenfilter Based Spike Sorting Algorithm & Hardware

• Evaluation

2 20th International Conference on Field Programmable Logic and Applications

Outline

• Background – BMI (Brain Machine Interface)

– Spike Sorting

• Hebbian Eigenfilter Based Spike Sorting Algorithm & Hardware

• Evaluation

3 20th International Conference on Field Programmable Logic and Applications

Background • BMI (Brain machine interface)

– It is a direct communication pathway between brain and external devices (also called direct neural interface or brain computer interface).

4 20th International Conference on Field Programmable Logic and Applications

Background – Various BMI

5 20th International Conference on Field Programmable Logic and Applications

Background – Various BMI

6 20th International Conference on Field Programmable Logic and Applications

Background • Close-loop BMI

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Background

• Spike sorting

– Electrode may collect signal from more than one neurons.

– The need of hardware for real-time spike sorting.

8 20th International Conference on Field Programmable Logic and Applications

Outline

• Background

– BMI (Brain Machine Interface)

– Spike Sorting

• Algorithm Design & Hardware Implementation

• Evaluation

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Spike Sorting Algorithm • Our PCA based Spike Sorting Algorithm

– Algorithm Procedure

– Feature Extraction is done by PCA that is a widely used method for feature extraction.

– Classification is done by k-means clustering algorithm. It clusters data to K groups.

10 20th International Conference on Field Programmable Logic and Applications

Spike Sorting Algorithm • Our PCA based Spike Sorting Algorithm

– Algorithm Procedure

– Feature Extraction is done by PCA that is a widely used method for feature extraction.

– Classification is done by k-means clustering algorithm. It clusters data to K groups.

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Principal Component Analysis • Feature extraction

– Principal component analysis (PCA) algorithms require complicated numerical procedures • Eigenvalue decomposition of covariance matrix or single

value decomposition of data matrix • Covariance matrix computation, matrix inverse, matrix

diagonalization, symmetric rotation.

– We present a Hebbian eigenfilter (based on general Hebbian alogrithm (GHA) ) for PCA computation • It does not involve complex computation • It has the ability to compute only the first few most

important PCs • Easier to be implemented in hardware

12 20th International Conference on Field Programmable Logic and Applications

Spike Sorting Algorithm (I)

• Hebbian Eigenfilter

– Step 1: Initialize weight W and select learning rate

– Step 2: Pre-process to remove mean from data

– Step 3: Update weight W 1

( ( )) /N

i

x i N

( ) ( )x i x i

( ( ) )T TW y x LT y y W

W W W 13 20th International Conference on Field Programmable Logic and Applications

y W x

Spike Sorting Algorithm (II)

• K-means clustering algorithm

– K-means clustering compute K centroids in PCs’ space and cluster data into K groups

• Step 1: Initialize centroids

• Step 2: Assign each point to its nearest centroid

• Step 3: Update centroid

2

1 1

|| ||N K

nk n k

n k

J r x

nk nnk

nkn

r x

r

14 20th International Conference on Field Programmable Logic and Applications

Hardware Design • Hardware Implementation

– Structure of hardware Hebbian eigenfilter

15 20th International Conference on Field Programmable Logic and Applications

Hardware Design – Structure of hardware K-means algorithm

16 20th International Conference on Field Programmable Logic and Applications

Hardware Design • FPGA Implementation

– More flexible than specific hardware and higher performance than microprocessor

– Providing massive parallel computation resources,

suiting for multi-channel spike sorting hardware implementation.

Flexibility

Performance

microprocessor

Application Specific hardware

FPGA

17 20th International Conference on Field Programmable Logic and Applications

Outline

• Background

– BMI (Brain Machine Interface)

– Spike Sorting

• Algorithm & Hardware

• Evaluation

18 20th International Conference on Field Programmable Logic and Applications

Evaluation • Input spikes

– Clinical and synthetic dataset are used for the evaluation

– Synthetic spike train generating tool (University of Stirling) is used to generate synthetic data for evaluating software and hardware

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Evaluation • Benchmarks and scenarios of input spike

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Evaluation • Evaluation methodology

– Matlab and Xilinx System Generator are used for software and hardware simulations, respectively

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Evaluation • Algorithm evaluation

( )

( )

Max signalSNR

Max noise _ _

_

correct classified spike

total spike

Numcr

Num

22 20th International Conference on Field Programmable Logic and Applications

Evaluation • Hardware evaluation

, ,

, 2 , 2

| ||| || || ||

i software i hardware

i software i hardware

PC PCaccuracy

PC PC

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Evaluation • Hardware evaluation

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Evaluation • Clinical data sets

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Evaluation • Throughput and hardware resource

• Hardware is 10x faster than software • FPGA can approximately implement 20

parallel channels with real-time spike sorting

Word Length =10 bit

Software (Intel Core2 E8400@3GHz, Matlab 2009a)

Number of Logic 674(1.4%) --

Number of DSP 3(2.4%) --

Number of BRAM 45(31.8%) --

Clock Freq.(MHz) 50 --

Learning Latency (ms) 8.2 93.8

Projection Latency (ms) 43.4 10 23.2 10

26 20th International Conference on Field Programmable Logic and Applications

Conclusion

• We utilize Hebbian eigenfilter to accomplish feature extraction in PCA based spike sorting algorithm.

• We implemented Hebbian eigenfilter using FPGA and rigorously evaluated it using synthetic and clinical spike trains.

• Our future work is to improve the design and incorporate the FPGA systems into closed-loop feedback brain-machine-interface systems.

27 20th International Conference on Field Programmable Logic and Applications