1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW...

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Specifications Functionality: AND, OR , XOR, ADD

Maximum propagation delay : 2nsPower budget: 30mWArea: 200 µm ×400µm

Prepared by: Christie Ma, Manjul Mishra, Ka Yung

Presented to : Dr. David Parent

Date: 7th May, 2003

4-Bit ALU4-Bit ALU

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HighlightsHighlights

• Introduction- How does the circuit work

• Approach for the design

• Individual blocks – AND gate, OR gate, XOR gate, Full Adder, and 4-to-1 MUX

• Wiring of 1-bit and 4-bit ALU

• Verification of functionality – test vectors

• Post extracted simulation with propagation delay

• Power consumption

• Conclusions

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Circuit FunctionalityCircuit Functionality

A0B0

4:1MUX

F0

Cout0

S1S0

ADD

A0B0

A0B0

A0B0C0

Control signal S1 S0

Operation

0 0 A and B

0 1 A or B

1 0 A xor B

1 1 A add BBlock diagram for 1-bit ALU

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Block Diagram for 4-Bit ALUBlock Diagram for 4-Bit ALU

1-bit ALU

1-bit ALU

1-bit ALU

1-bit ALU

A0B0C0

A1B1

A2B2

A3B3

F0

F1

F2

F3

Cout0

Cout1

Cout2

S1 S0

Cout3

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Design FlowDesign Flow

Calculate Wn Wp for each block

Run Spice simulation to fix Wn, Wp

Draw schematic for each block

Layout for small blocks

Run DRC, LVS, extracted simulation for small blocks

Route small blocks together to form 1-bit ALU

Route four 1-bit ALUs to form a 4-bit ALU

Run DRC, LVS, extracted simulation for 4-bit ALU

Verify functionality

Measure delay time

Measure power usedSketch schematic according to Boolean Algebra

Find Euler Path

Draw stick diagram

Run DRC, LVS, extracted simulation for 1-bit ALU

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AND2 schematicAND2 schematic

Wp=5.4 m

Wn=15.15 m

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AND2 Layout & LVS ReportAND2 Layout & LVS Report

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OR2 SchematicOR2 Schematic

Wp=8.4m

Wp=5.85 m

Wn=10.2 m Wn=14.25 m

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OR2 Layout & LVS ReportOR2 Layout & LVS Report

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XOR2 SchematicXOR2 Schematic

Y = A xor B = AB’ + A’B

= (AB + A’B’)’ AOI21 = (AB + C)’if C = A’B’

C = (A+B)’ C = A nor B

Therefore, using one AOI21 and one NOR gate, we can implement XOR gate without using any INV.

Wp=15.9m

Wn=23.4m

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XOR2 Layout & LVS

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Full Adder Schematic

Wp=6.15mWn=3.6mCout=AB+ACin+ BCin = AB+Cin(A+B)

Sum= ABCin + (A+B+Cin)Cout’

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Full Adder Layout

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Full Adder LVS Report

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4-to-1 MUX schematic

F0= S0’(S1’Y00+S1Y10)+S0(S1’Y01+S1Y11)

2-to-1 MUX 2-to-1 MUX

2-to-1 MUX

Wp=9.9 m

Wn=6.45 m

Therefore, we need three 2-to-1MUXsto build a 4-to-1 MUX

F0= S1’ S0’Y00+ S1’S0Y01 +S1S0’Y10+S1S0Y11

2-to-1 MUX schematic

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4-to-1 MUX schematic (cont.)

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4-to-1 MUX Layout

One 2-to-1 MUX Three 2-to-1 MUXs to form a 4-to-1MUX

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4-to-1 MUX LVS Report

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1-bit ALU schematic

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1-bit ALU Layout

AND

XOR

OR

ADDER4-to-1 MUX

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1-bit ALU LVS Report

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4-bit ALU Schematic

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4-bit ALU LayoutArea = 197m 347.4 m

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4-bit ALU LVS Report

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Test VectorsTest Vectors

• Walking ones for inputs on all operations (1-8)• Testing for Cout and Cin (9, 10)

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Simulation ResultsSimulation ResultsA3 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation Results

A2 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation ResultsA1 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation Results

A0 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation ResultsB3 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation ResultsB2 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation ResultsB1 = 1, Ax = 0, Bx = 0

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Simulation ResultsSimulation Results

B0 = 1, Ax = 0, Bx = 0

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Simulation Results (Cout)Simulation Results (Cout)A3 = 1, B3 = 1

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Simulation Results (Cin)Simulation Results (Cin)C0 = 1, A0 =1, B0 =1

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Propagation Delay for AND gatePropagation Delay for AND gate

274.1ps

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Propagation Delay for OR gatePropagation Delay for OR gate

237.9 ps

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Propagation Delay for XOR gatePropagation Delay for XOR gate

226.7ps

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Propagation Delay for Full AdderPropagation Delay for Full Adder

495.5 ps

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Propagation Delay for 4-to-1 MUXPropagation Delay for 4-to-1 MUX

330.4 ps

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Propagation Delay For 4-bit ALU Propagation Delay For 4-bit ALU (when S1=S0=0 (when S1=S0=0 AND Operation)AND Operation)

t F2 = 705.9ps t F3 = 698.2ps

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Propagation delay For 4-bit ALUPropagation delay For 4-bit ALU ( when S1=0, S0=1 OR Operation)( when S1=0, S0=1 OR Operation)

t F2 = 693.8 ps t F3 = 673.2 ps

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Propagation Delay for 4-bit ALUPropagation Delay for 4-bit ALU(when S1=1, S0=0 XOR Operation)(when S1=1, S0=0 XOR Operation)

t F2 = 661.2 ps t F3 = 678.7 ps

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Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)

t F0 = 987.9 pst F1 = 1.383 ns

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Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)

t F2= 1.484 ns t F3 = 1.949 ns

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Propagation Delay for 4-bit ALU Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)

t Cout3 = 1.339 ns

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Power Simulation for 4-bit ALU Power Simulation for 4-bit ALU (when S1=S0=0 AND Operation)(when S1=S0=0 AND Operation)

Power = 26.8 mW

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Power Simulation For 4-bit ALUPower Simulation For 4-bit ALU ( when S1=0, S0=1 OR Operation)( when S1=0, S0=1 OR Operation)

Power = 26.69 mW

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Power Simulation for 4-bit ALUPower Simulation for 4-bit ALU(when S1=1, S0=0 XOR Operation)(when S1=1, S0=0 XOR Operation)

Power =21.38mW

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Power Simulation for 4-bit ALU Power Simulation for 4-bit ALU (when S1=S0=1 Add Operation)(when S1=S0=1 Add Operation)

Power =23.35mW

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ConclusionsConclusions

• We meet the specifications!

Specifications Our circuit

Largest Propagation delay

2.0 ns 1.95ns

Maximum Power 30 mW 26.8 mW

Area 200 µm ×400µm 197 µm ×347.4µm