1/76 Potentials of R&D for ICT in Cooperation with IPSI Belgrade An Overview of IPSI Belgrade...

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Potentials of R&D for ICT Potentials of R&D for ICT inin

Cooperation with IPSI Belgrade Cooperation with IPSI Belgrade

An Overview of IPSI Belgrade Projectsfor High-Tech Computer Industry

in the USA and EU

This material was developed with financial help of the WUSA fund of Austria.

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IPSI BelgradeIPSI Belgrade• IPSI BelgradeIPSI Belgrade - Jointly founded by German/USA/Japanese/Serbian capital

• Some of those responsible for launching: - Fraunhofer IPSI, Darmstadt, Germany - StorageTek, Colorado, USA - M.I.T. of Tokyo, Japan - Telecom Italia Learning Services, L’Aquila, Italy

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Employees and AssociatesEmployees and Associates• CEO:CEO:

Prof. Dr. Veljko Milutinovic, Fellow of the IEEE,Electrical Engineering, University of Belgrade, Serbia

• Senior Consultant:Senior Consultant:Prof. Dr. Erich Neuhold, Fellow of the IEEE, ResearchStudio, Vienna, Austria

• Initial Team: Jovic Darko, Babovic Zoran, Toskov Ivan, Vujovic Ivana, Vujnovic Damjan, Krunic Jelena, Milic Bratislav, Milutinovic Darko, Nikezic Gavro, Radakovic Miroslav, Skundric Nikola, Minic Predrag, Stanic Sasa, Korolija Nenad, Rudan Sasa, and Kovacevic Aleksandra.

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Selected IPSI Belgrade ServicesSelected IPSI Belgrade Services- Workspaces of the Future- Environments for Cooperative Working and Learning- Virtual Information and Knowledge Environments- Mobile Interactive Media- Open Adaptive Information Management Systems- Publication Engineering and Technology- Services on the WWW- Infrastructure for E-Business on the Internet

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General Project StructureGeneral Project Structure

Industrial Research:

Phase #1: Survey, and Generation of Embryonic Ideas

Phase #2: Analytic Analysis and Comparison (1+K)

Phase #3: Simulation Analysis and Comparison

Phase #4: Implementation Analysis and Comparison

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General Project StructureGeneral Project Structure

Industrial Development:

Phase #1: Product Requirements

Phase #2: Intra Module Coding

Phase #3: Inter Module Integration

Phase #4: Exhaustive Verification

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Some Recent Educ Projects Frankfurt/M, Frankfurt/O, Magdeburg, Berlin, Hagen, Koblenz,

Kaiserslautern, Erlangen, TUM, IPSI FhG, Karlsruhe, Ulm, ...

NYU, Purdue, Dartmouth, Hawaii, …

Modena, Ferrara, Siena, Pisa, Salerno, Napoli, …

Tech De Monterrey, Tech De Durango, UNAM, La Salle, …

St. Mary’s, Dalhousie, …

RIT, Skoevde, Karlskrona, Karlstadt, …

Valencia, Barcelona, Madrid, Oviedo, …

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Some RecentSome Recent R&D R&D ProjectsProjects

WSJ, DJ, Finsoft, Microsoft, NCR, Encore/HP, SUN/StT, Intel, …

Comshare, Zycad, QSI, Virtual, …

TechnologyConnect, BioPop, eT, MainStreetNetworks, …

Salerno, Pisa, Siena, L’Aquila, ...

Ulm, Darmstadt, Berlin, Karlsruhe, …

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R&D Methodology• Introduction• Problem Statement• Criticism of Existing Solutions• Proposed Solution• Conditions and Assumptions• Details (1+k)• Mathematical Analysis• Simulation Analysis• Implementation Analysis• Conclusion

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Internet Servers

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NCR: NextGen PC for E-Business Cache coherence maintenance: Hardware approach Cache coherence maintenance: Software approach Accelerator chip for windowing Accelerator board for dbase applications Prefetching on the "silence" for disk cacheing Accelerator chip for text compression Accelerator chip for JPEG/MPEG

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SMP in Action

MM

PP

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ENCORE/COMPAQ/HP

Improved RMS for PC, and its prototype The RM/MC for PC approach, and its analysis Simulation of selected DSM approaches, and their comparison (RMS, KSR, and SCI) Search for the optimal RMS inteconnect technology

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DSM in Action

In t e r co n n e c ti o nC o n t ro l le r

In te rc o n n e c t io nC o n tro lle r

In te r c o n n e c tio nC o n tro ll e r

D ire c to ry D i rec to ry D ire c to ryP ro c e s s o rs P ro c e s s o rs P ro c es so rsC a c h e s C ac h e s C a c h e s

D S M

C luster 1 C luster 2 C luste r N

IC N

D SMSharedA ddressSpace

D S MD S M

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Prologue

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Epilogue

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Cutting the Edge

Top Down Technologies i860 Selected microprocessor models

QSI An ATM router chip In-memory processing

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Response: Industry

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Response: Academia

Flynn, M. J., Computer Architecture, Jones and Bartlett, USA (96)position 1 (12 citations)

Bartee, T. C., Computer Architecture and Logic Design, McGraw-Hill, USA (91)position 1 (2 citations)

Tabak, D., RISC Systems (RISC Processor Architecture), Wiley, USA (91)position 1s (6 citations)

Stallings, W., Reduced Instruction Set Computers (RISC Architecture), IEEE CS Press, Los Alamitos, California, USA (90)position 1s (3 citations)

Heudin, J. C., Panetto, C., RISC Architectures, Chapman-Hall, London, England (92)position 3s (2 citations)

van de Goor, A. J., Computer Architecture and Design, Addison Wesley, Reading, Massachusetts, USA (2nd printing, 91)position 4s (3 citations)

Tannenbaum, A., Structured Computer Organization (Advanced Computer Architecures), Prentice-Hall, USA (90)position 5s (4 citations)

Feldman, J. M., Retter, C. T., Computer Architecture, McGraw-Hill, USA (94)position 7s (2 citations)

Stallings, W., Computer Organization and Architecture, Prentice-Hall, USA (96)position 9s (3 citations)

Murray, W., Computer and Digital System Architecture, Prentice-Hall, USA (90)position >10s (2 citations)

Wilkinson, B., Computer Architecture, Prentice-Hall, USA (91)position >10 (2 citations)

Decegama, A., The Technology of Parallel Processing (Parallel Processing Architectures), Prentice-Hall, USA (90)position >10s (2 citations)

Baron, R. J., Higbie, L., Computer Architecture, Addison-Wesley, USA (92)position >10s (1 citation)

Tabak, D., Advanced Microprocessors (Microcomputer Architecture), McGraw-Hill, USA (95)position >10s (1 citation)

Zargham, M. R., Computer Architecture, Prentice-Hall, USA (96)position >10s (1 citation)

Hennessy, J. L., Patterson, D. A., Computer Architecture: A Quantitative Approach, Morgan-Kaufmann, USA (96)na (0 citations)

Hwang, K., Advanced Computer Architecture, McGraw-Hill, USA (93)na (0 citations)

Kain, K., Computer Architecture, Addison-Wesley, USA (95)na (0 citations)

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N.B.

ERRORS MADE & LESSONS LEARNED

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1

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2

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3

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The Split Temporal/Spatial Cache

Veljko Milutinović, Boris Marković*, Milo Tomašević, Aleksandar Milenković, and MarkTremblay**

IFACT

Department of Computer Engineering School of Electrical Engineering University of Belgrade POB 35-54 11120 Beograde, Serbia

___________________________________________________________________________* Boris Marković is with the University of Montenegro, Podgorica, Montenegro** Mark Tremblay is with the SUN Microsystems, Palo Alto, California, USA

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C1.spat

COMPILE.time

C2.temp

C1.temp

RUN.time

PFB

SPLIT TEMPORAL/SPATIAL CACHE

MM

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The Injection Cache

Veljko Milutinović, Aleksandar Milenković, Davor Magdić,and Gad Sheaffer*

IFACTDepartment of Computer Engineering School of Electrical Engineering University of Belgrade POB 35-54 11120 Beograde, Serbia

________________________________________________________________________ * Gad Sheaffer is with the Intel Corporation, Beverton, Oregon, USA

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IN

PRODUCER

CONSUMER

C2

C1

P

EARLY LATE

tc

t

CACHE INJECTION

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Integrated Systems

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VLSI Detection for

Internet/Telephony InterfacesGoran Davidović, Miljan Vuletić, Veljko Milutinović,

Tom Chen, and Tom Brunett

* eT

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INTERNET SERVICE PROVIDER

REMOTESITE

Superposition/DETECTION Superposition/DETECTION

. . .

USERS...

HOME/OFFICE/FACTORY AUTOMATION ON THE INTERNET

SPECIALIZED

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Browser Acceleration

Gvozden Marinković, Dragan Jandrić, Vladimir Ivanović,

Veljko Milutinović, and Tom Chen

*MainStreetNetworks

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What is the Major Bottleneck?Rendering!S end the "IN FO R M A T IO N A B O U T E T F B E L G R A D E "

H T T P

T h e c lie n t se nd s H T T P m e ssa g e t o a c o m p u te rru n n in g a W e b S e rv e r p ro g ra m a n d a sk s fo r a d o c u m e n t

T he In form ationabout

E T F B E L G R A D E

T h e W eb server sen ds th e h yperm ed ia HT M L docum en ts to th e clien t.Y ou en d up seein g th e docum en t on your screen

C lie n t S e rv e r

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BioPoP

Veljko Milutinovic, Vladimir Jovicic, Milan Simic,Bratislav Milic, Milan Savic, Veljko Jovanovic,

Stevo Ilic, Djordje Veljkovic, Stojan Omorac,Nebojsa Uskokovic, and Fred Darnell

•isItWorking.com

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Testing the Infrastructure for EBI

• Phones• Faxes• Email• Web links• Servers• Routers• Software

• Statistics

• Correlation

• Innovation

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CNUCEIntegration and Datamining

on Ad-Hoc Networks and the Internet

Veljko Milutinović, Luca Simoncini,

and Enrico Gregory

*University of Pisa, Santanna, CNUCE

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GSM

DMAd-Hoc

InternetAd-Hoc

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Infrastructure for Collaboration

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Technology Transfer

Veljko Milutinović, Wendy Chin,

Bob Richardson, and Jerome Friedman

*TechnologyConnect.com

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BuyersBuyers

Reseller/R&D Reseller/R&D Manager/Manager/

Product Line Product Line Manager/Manager/Business Business

Development Development ManagerManager

License AgreementLicense AgreementReseller AgreementReseller AgreementDev. ContractDev. ContractAcquisitionAcquisitionMergerMerger

ConsultanConsultantstsBusiness Business

Development Development ConsultantConsultantServicesServices

ExpertiseExpertise

SellersSellersProduct Line Product Line

Manager/Manager/IP Licensing IP Licensing

ManagerManagerProductsProductsTechnologiesTechnologiesPatentsPatentsExpertiseExpertise

$ 216 B

<10 %

<1%

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SocratenonDistant Web Education Engine

Nenad Nikolić, Milan Milićević, Milan Trajković,

Dragan Milićev, Veljko Milutinović,

and Massimo Desanto

*University of Salerno

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Intranet

Internet

Database Server

Application Server

ClientWeb Browser

Web Server &Application

SQL Server

Web pages

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SSGRROrganizing Conferences via the Internet

Zoran Horvat, Natasa Kukulj, Vlada Stojanovic, Dusan Dingarac, Marjan Mihanovic, Miodrag Stefanovic,Dusan Savic, Bratislav Milic, Zaharije Radivojevic, Ivana Vujovic, and Ivan Toskov,

Veljko Milutinovic, and Frederic Patricelli

*SSGRR, L’Aquila

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2000:

Arno Penzias

2001:

Bob Richardson

2002:

Jerry Friedman

2003:

Harry Kroto

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University of UlmReverse Engineering of

GeForce2-4Sasa Jandric, Zaharije Radivojevic, Milos Cvetanovic,

and Veljko Milutinovic

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010101000001101101• Developing system control programs (drivers)

for GeForce 2-4, for the Plurix operating system• Main advantage of the GeForce chip

(called graphical processor) is the use of 3D accelerating functions

• Reversed engineering is used as a technology for finding previous information on the GeForce chip

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Intelligent Search

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Genetic Search with Spatial/Temporal Mutations

Jelena Mirković, Dragana Cvetković,and Veljko Milutinović

*Comshare

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Drawbacks of INDEX-BASED: Time to index + ranking

Advantages of LINKS-BASED: Mission critical applications + customer tuned ranking

Provider

Well organized markets: Best first searchIf elements of disorder: G w DB mutationsChaotic markets: G w S/T mutations

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Reconfigurable FPGA for SA

Božidar Radunović, Predrag Knežević, Veljko Milutinović,

Steve Casselman, and John Schewel*

* Virtual

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INTERNET

PROVIDER

. . .

USERS

VCC VCC

CUSTOMER SATISFACTION vs CUSTOMER PROFILE

SPECIALIZED

SERVICE

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IPSI FhG DarmstadtInternet 3D Gallery

Marinkovic Ivan, Stojanovski Aleksandar, Radakovic Miroslav, Nikezic Gavro, Skundric Nikola, Milutinovic Darko,

Zivic Marko, Anucojic Goran, Vujovic Ivana, Toskov Ivan, and Milutinovic Veljko

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Dream Search• Creating Web based art gallery with “look and feel”

of the real world exhibitions

• Dynamically generated, with content based search engine (including image recognition)

• Made in ASP.NET using C# as code-behind, and ADO.NET for database access; database server is SQL Server 2000; communication with the database through XML; 3D designed with VRML

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3D MMI

Serbia Forum

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Hermann Maurer, Jakob Salom, Aleksandar Mihajlovic, Vladisav Jelisavcic, Zoran Ognjanovic, Zoran Markovic,Veljko Milutinovic.

Heritage Mining in Serbia Forum

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SummaryThe world’s best journals - IEEE: A European record in ICT (50)

Books with Nobel Laureates (7): Kenneth Wilson, Ohio (North-Holland) Leon Cooper, Brown (Prentice-Hall) Robert Richardson, Cornell (Kluwer-Academics) Jerome Friedman, MIT (IOS Press)

Herb Simon (Kluwer-Academics) Harold Kroto (Academic Mind Press) Arno Penzias (Academic Mind Press)

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Recent NDA Projects• StorageTek, Colorado, USA• Panthesis (exBoeing), Oregon, USA• Fraunhofer IPSI, Darmstadt, Germany• Research Studio, Vienna, Austria• Finsoft, London, England• STC, Uppsala, Sweden• Wall Street Journal, New York, USA• DowJones, New York, USA

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DSFS - Digital Sealed File System• Goal: System for Data

Modification Detection• StampTool = Smart Card

– Input: Hash – Output: Stamp + Public Key

• Verification Body– Calculation of Hash Value– Comparison with Encrypted Stamp

• PublishingTool – Public Key Distribution– Several Possible Solutions

Depending on a Purpose

StorageTek/A

StampTool

Server

Signer PublishingTool

Verification Body

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Multi-Domain Metadata for a More Automated ILM Storage Manager

• Motivation: The human componentof the TCO (total cost of ownership)becomes significant today due tocosts of monitoring and control.

• Idea: More important and useful data (or metadata) about stored information can be gleaned and collected from the storage systems and the servers that use them.

StorageTek/B

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MPEG-1/2 Multiplexer

• A Software Tool/Framework for Creating MPEG-1/2 System Stream

• Input Streams for Multiplexing: – MPEG-1/2 Audio Streams– MPEG-1/2 Video Streams– AC3 Audio Stream

• Proposed Solution is full Object Oriented,

Implemented in C++, and Easy to Use

Fraunhofer/A

PS

Mux

TS

Mux

VideoEncoder

AudioEncoder

PacketizerVideo PES

Audio PES

Video

Data

Audio

Data

Program

Stream

Transport

Stream

Extent of Systems Specification

Packetizer

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Business Process Matchmaking

• The Goal of this Project was to Develop a Matchmaking Engine,

the Multi-tiered J2EE Application, that will Enable Efficient Business Process Matchmaking

• Business Processes were Described Using the Annotated Finite-state Automata

Fraunhofer/B

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Panthesis/A

• E-Learning with SWAN

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Panthesis/B

• Improvements of E-Learning with SWAN

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FP6 + FP7

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FP6: WeGo

• Interoperability Framework WB/EU• Partners• Goals

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FP6: HiPeac1

• Cooperation with UPC (12+8)• Partners• Goals

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FP7: BalCon

• Knowledge Engineering in Business Appl• Partners• Goals

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FP7: ProSense

• Sensor Nets in Medical Applications• Partners• Goals

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FP7: ARTreat

• Concept Modeling• Partners• Goals

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FP7: HiPeac2

• Cooperation with U. of Siena• Partners• Goals

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Veni, Vidi, Vici

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Major Current Software Projects

• GTECH • ASSECO• Maxeler • Moskowitz-Jacobs

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Quo Vadis Domine?

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http://home.etf.rs/~vm

e-mail: vm@etf.rs