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7/21/2019 298-843-1-PB
1/5
International Journal
Communication Technolog
www.ijrcct.org
Design of Low Power
M. Tech , Em
Geethanjali College of
Email:ralla
Abstract- This paper presents an
successive-approximation-register (
digital converter (ADC) for biomedic
low-power applications designer need
compromise among speed, resol
power.To reduce energy consum
redistribution technique is used alo
technique for comparator offset canc
consumptions of the capacitive
converter (DAC), latch comparator,
circuit of the proposed ADC are low
conventional SAR ADC.ADC is de
CMOS technology in such a way tha
minimized while medium samplin
resolution are achieved.
Index Terms-Analog-to-digital co
CMOS analog integrated circu
offset,autozero,low supply volt
approximation.
I. INTRODUCTIONIn the last few years, there h
interest in the design of wireless s
portable, wearable or implant
applications. These sensing devices aredetecting and monitoring biomedica
electrocardiographic (ECG), elect
(EEG), and electromyography (EMG
Most biomedical signals are often ver
limited dynamic range. A typical
interface consists of a band-pass
amplifier and an analog-to-digital con
digitalization of the sensed biomedica
performed by ADCs with moderate re
and sampling rate (11000kS/s). In su
efficiency and long battery life aregoals. Particularly, ADCs for implantneed microwatt operation to run on
decades. Therefore, energy efficie
challenge for ADCs design.battery l
design goals. Particularly, ADCs for
devices need microwatt operation tbattery for decades.Therefore, energ
critical challenge for ADCs d
approximation register (SAR) ADC h
power efficiency compared with other
(e.g., pipelined ADC). Furthermore,
from technology downscaling beca
reasons:(1) SAR ADC mainly consistwhich get faster in deep sub-micron tec
of Research in Computer and
, Vol 2, Issue 8, August -2013
ISSN(Online
ISSN (Print
SAR-ADC in 0.18m Mixed-Mode CRVNR Suneel Krishna , Aleti Shankar
edded systems , Associate professor, Dept. of EC
Engineering and Technology,Rangareddy Dist, A.P, I
handiSK@gmail. com , shanker4244@gmail. com
energy efficient
SAR) analog-to-
l applications.For
to come up with a
tion and speed
tion, a charge
g with auto zero
ellation.The power
digital-to-analog
nd digital control
er than those of a
signed in 0.18m
the total power is
rate and 8 bit
nverters (ADCs),
its, low power,
age, successive
as been a growing
ensing device for
able biomedical
generally used for l signals such as
roencephalography
), to name a few.
y slow and exhibit
biomedical sensor
ilter, a low-noise
verter (ADC). The
l signals is usually
olution (812 bits)
ch devices, energy
paramount design ed medical devices small battery for
cy is a critical
ife are paramount
implanted medical
run on a small y efficiency is a
sign. Successive
s the advantage of
ADC architectures
AR ADC benefits
se of two major
s of digital circuits hnologies; and (2)
SAR ADC is another words, SAR ADC doe
high bandwidth opamps to gu
performance opamp consum
from short channel effect
advanced process nodes. Theof designers which is reflect
publications.SAR ADCs
biomedical acquisition syste
consumption and simplicity,p
sub-circuits.The comparator
the only two analog compone
Fig. 1. Overall syste
The overall system architect
designed and implemented aand results are validated
Analog Design Environment I
II. CONVERTER PRINCIPL
Successive Approxi
Charge Redistribution Princi
2. Binary weighted capacito
switching point of the comp
value of the input signal.
comparator input positive
referred to analog groundcontinuously decreasing wit
steps performed within a
Consequently, at the end owhen highest precision is
inputs are operated near analo
) 2278-5841
2320-5156
Page 654
MOS Process
,
ndia-50130
pamp-free architecture. In s not require high gain and
arantee the linearity.A high-
es large power, and suffers
nd low supply voltage in
e reasons arouse the interest ed in the number of recent
are commonly used in
s due to their low power
articularly for simple analog
and sampling switches are
ts..
Architecture of SAR-ADC
re is shown in Fig.1. We
ll the blocks of SAR-ADC sing CADENCE Virtuoso
C 6.1.5 tool.
E
ation Converter based on a
le is characterized in Fig.
s are used for the DAC. The
arator is independent of the
During conversion, at the
and negative voltages VC
occur, whose magnitude is the number of conversion
omplete conversion cycle.
the conversion cycle, i.e., emanded, both comparator
g ground [1].
7/21/2019 298-843-1-PB
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International Journal of Research in Computer and
Communication Technology, Vol 2, Issue 8, August -2013
ISSN(Online) 2278-5841
ISSN (Print) 2320-5156
www.ijrcct.org Page 655
Fig. 2. SAR-ADC Based on a Charge
Redistribution Principle
III. THE SAMPLE & HOLD CIRCUIT DESIGN
The Sample & Hold circuit is completelypassive. It contains just a sampling switch, a dummy
switch, a sampling capacitor and two clock buffers Fig.3. The passive S/H circuit gives a simple solution to the
requirements of both small offset and wide input
bandwidth of the SA-ADC to be used in an ADC array
[2].
Fig. 3. Passive Sample & Hold Circuit
In this architecture Fig.3, one dummy switch is used to
minimize clock feed through error [3]. The theory behind
this technique is that if the width of M1 is one half of M0
transistor, and clock wave form is fast enough then charge
will cancel. The Fig.4, shows the schematics of Sample
and Hold circuit. The value of holding capacitor is 1pF.Where transistor M0 operating in linear region, the
condition for operating in linear region is
> (1)
< = (2)
= (3)
Where,
= , =Gate Source Voltage
= (3)
=Supply Voltage, =Threshold voltage
=
( ) (4)
The calculated value of W/L for M0 & M1 is given in
Table I the Fig.5, shows the simulation result of S&H
circuit Fig.4.
TABLE I: ASPECT RATIO OF SAMPLE & HOLD
CIRCUIT
Transistor W L
M0 2u 0.5u
M1 1u 0.5u
III. CAPACITOR ARRAY DAC
The Binary weighted Capacitor DAC or Charge
scaling DAC architecture is as shown in Fig.6.In this
architecture, a parallel array of the binary weighted
capacitors is connected [3],[8]. The voltage output,VOUT, can be expressed as relation (6)
= (6)
Where, VOUT is the analog voltage output, VREF is the
reference voltage, K is a scaling factor and the digital
word D is given by relation (7)
= + + + + (7)
N is the total number of bits of the digital word, and bi is
the ith coefficient and is either 0 or 1. The relation (8)gives the value of VOUT for any digital word.
= (8)
Fig. 6 Architecture of Charge Scaling DAC
We have implemented the architecture shown in Fig.6
using CMOS capacitors and transistor switches as shown
in
Fig.7, which is simulated using CADENCE Analog
Design Environment.The values of capacitors
CMSB..CLSB are used as a multiple of unit
capacitor of 20fF. Here we are assuming the unit
capacitance is 20fF.
The calculated values of all capacitors are given in Table
II.
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International Journal
Communication Technolog
www.ijrcct.org
DAC
capacitor C7
capacitor value 2.
NMOS/PMOS Switch in um 0.2
RON (NMOS) 2
RON (PMOS) 2
Switch-1 PMOS, NMOS co
and connects to VREF.
Fig. 8. DAC Switch archit
Switch-2 PMOS, NMOS combination
connects to ground when bit-1 is reset [calculated the W/L of switch transistor
Table II.
Fig. 9. Schematic of D
of Research in Computer and
, Vol 2, Issue 8, August -2013
ISSN(Online
ISSN (Print
Fig. 7. Schematic of
IV. DAC SWITCH DESIGN
This design is usedand clock feed through error
and NMOS switches sho
transistors are operating in li8 shows a unit capacitor con
is set (High).
TABLE II
SWITCHES SIZES AND ON RESISTANCES
For 0.18m Technology
(MSB) C6 C5 C4 C3
.56pF 1.28pF 640fF 320fF 160fF
7/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.27/0.18 0.2
.04K 2.04K 2.04K 2.04K 2.04K 2.
.96K 2.96K 2.96K 2.96K 2.96K 2.
bination goes ON
ecture
oes ON and
4], [6]. We have and is given in
C switches
The Fig. 9 shows implemen
RON resistance of PMOS andcalculated using relation (9).
= `
(
The Charge Scaling DAC is
process. The threshold voltag
and -0.4064V for the pMOS d
value of DNL is 0.7L
respectively.
V. COMPARATOR
The comparator i
regenerative resettable circuit
by inverters for signal lev
comparator is use positive fecompare two signals. The ad
there is no steady state po
current will be the one require
approach is based on slew ra
delay constraints. Apart fro
comparator is working as ex
be controlled by the bias
Fig.13, both transistor Msaturation region and drain c
given by equation (10)
=
( ) (
) 2278-5841
2320-5156
Page 656
Charge scaling DAC
to reduce charge injection s by complimentary PMOS
n in Fig.8. All MOS
ear region [4], [5].The Fig. necting to VREF when bit-1
C2 C1 C0(LSB)
0fF 40fF 20fF
7/0.18 0.27/0.18 0.27/0.18
.04K 2.04K 2.04K
.96K 2.96K 2.96K
tation of DAC switch. The
NMOS transistor can be
) (9)
simulated in 0.18um CMOS
s are 0.327 V for the nMOS
evice. It is observed that a
B and INL is 0.8LSB
s designed as a simple
Fig. 12, [1], [8] followed
el recovery. This type of
ed back bi-stable element to antage of this circuit is that
er consumption. The only
d by bias circuit. The design
te and optimum propagation
offset related issues, the
ected. The bias current can
transistor is as shown in
2 and M3 is operating in rrent of M2 and M3 can be
+ ) (4)
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International Journal
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We have assumed 2uA bias current to
ratio of the transistor M2 & M3.The astransistor M2 & M3 given in Table
schematic of comparator is as shown in
Fig. 12. Schematic of Regene
Fig. 13 Schematic of biasing cu
Circuit MOS
Bias Current
Source
M2 2
M3 0.
Differential
Pair
M4 0.
M5 0.
Switches M6.M7 0.
M8,M9 0.
Inverter PMOS 3
NMOS 0.
of Research in Computer and
, Vol 2, Issue 8, August -2013
ISSN(Online
ISSN (Print
calculate the W/L
ect ratios of III. The complete
Fig.12.
rative Comparator
rrent source
The current ID or bias curr
which flows through M4
differential pair transistor. Ton Vin1 and Vin2 which c
(11).
= 0.5 + 0.25 .
Where =
T
TRANSIS
The Autozero technique
Fig.14: The auto
The auto zero technique r
frequency noise based on
method has been extensivel
reduction in comparators an
nowadays A/D converters wi
use of auto-zeroed compar
principle of an auto zero am
clock, the sampling phase, th
of the amplifier configured a
capacitor C.The output y(t) i
as long as the open loop
large:
( )=
( ) ( )
VI. SAR LOGIC DESIGN
A successive appro
digital control circuit, which i
flop. We have designed D fli
It has a parallel world outpu
input of an nbit D/A converte
L
u 0.4u
3u 0.4u
4u 0.18u
4u 0.18u
5u 0.18u
7u 0.18u
u 0.18u
3u 0.18u
) 2278-5841
2320-5156
Page 657
nt split in to ID1 and ID2
and M5 respectively in
is two current are depends n be expressed as relation
(11)
BLE III
OR SIZE
zero technique
duces the offset and low
sampling methods. This
used in the past for offset
amplifiers [4]. Most of the
ith offset cancellation make
ators. Fig.14 illustrates the
plifier. In the phase 1 of the
e offset and the flicker noise
s a buffer is sampled on the
s actually the offset voltage
gain of the amplifier is
(12)
(13)
imation register (SAR) is a
s implemented using D flip-
-flop using Verilog-A code.
t, which is connected to the
r. The input of the SAR is a
7/21/2019 298-843-1-PB
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International Journal
Communication Technolog
www.ijrcct.org
one bit digital signal, which is taken
the comparator. To start the conversio
is set to 1 and all the other bit are sethigher than the output of DAC then
set to d0=1 other wise d0=0.The c
changed to [d0 1 0.0] in the secon0.0] in the third step. The procedur
approximation is continued until the
reached. The classic SAR algorithmshown in Fig. 15 and the logic dia
approximation register is shown in Fi
Fig. 16. Logic diagram of successive a
register
Fig. 15. SAR algorithm flow c
VII. CONCLUSION
A successive approximation
for operation at low supply voltage
standard 0.18um MOS technology.building blocks of SAR-ADC usin
threshold voltages of approximately
of Research in Computer and
, Vol 2, Issue 8, August -2013
ISSN(Online
ISSN (Print
from the output of
, MSB in the SAR
to 0. If the input is SB of the SAR is
ontent of SAR is
d step, and [d0 d1 1 e of the successive
esired accuracy is
flow chart is as ram of successive
.16.
proximation
hart
converter suitable
is designed in a
e design all the g transistors with
0.327V for NMOS
and 0.4064 for PMOS. Th
that the circuit achieves 8-bit
monotonic conversion at hinonlinearity less than 1 LSB
standard CMOS technology
results are validated usingVirtuoso Analog Design E
tool.
VIII.REFERENCES
[1] Jens Sauerbrey, Doris
Thewes, A 0.5V, 1W
ADC,IEEE Journal of Solid
[2] Jiren Yuan and ChristerSuccessive Approximation A
ADC Array in 1.2- pm CM
State Circuits, Vol. 29, No. 8,
[3] David A. Johns and KenCircuit Design2nd Ed. 2002
Pvt. Ltd. Singapore.
[4] P. E. Allen, Holberg, C
(New York Oxford Uni. Press
[5] Jens Sauerbrey, Doris
Thewes, A 0.5V, 1W
ADC,IEEE Journal of Solid[6] National Semiconductor
Nicholas Gray, November 24
[7] V. Peluso, P. Vancorenla
and W. Sansen, "A 900mV
Modulator with 77dB Dyna
Technical Papers, pp. 68-69,[8] R. J. Baker, Li H. W.,
Design, Layout, and Simulati
IX BIOGRAPHY
RVNR S
Vijayawa
B.Tech
Communi
Vivekana
and tech A.P, Ind
EmbeddeCollege of Engineering and te
A.Shankar
district, A.
Associate
Communic
Geethanjali
Technology
Masters DeProcessing from JNTUH A.
Teaching Experience and hi
power VLSI Signal ProcessSpeech Processing.
) 2278-5841
2320-5156
Page 658
e simulation results indicate
gh speed with differential . This device is suitable for
LSI implementation. These
CADENCE mixed signal vironment IC (6.1.4/6.1.5)
Schmitt-Landsiedel, Roland
Successive Approximation
State Circuit, IEEE 2002.
Svensson, A 10-bit 5-MS/s DC Cell Used in a 70-MS/s
S, Ieee Journal Of Solid-
August 1994.
Martin ,Analog Integrated John Wiley & Sons(ASIA)
OS Analog Circuit Design
.2004)
Schmitt-Landsiedel, Roland
Successive Approximation
State Circuit, IEEE 2002. rticle ABCs of ADCs by
2003.
d, A. Marques, M. Steyaert,
40W Switched Opamp
ic Range", ISSCC Digest of
p. 414, 1998 . E. Boyce, CMOS Circuit
n (IEEE Press)
neel Krishna was born in
a, A.P, India. He received
in Electronics and
cation Engineering from
da Institute of Engineering
nology, Rangareddy Dist, ia. Perusing M.Tech in
Systems at Geethanjali chnology A.P, India.
was born in Warangal
P, India.and working as an
rofessor in Electronics and
tion Engineering in
College of Engineering &
, A.P, and India.he received
gree in Systems and Signal india. He has 10 years of
s interesting fields are low
ing, Image Processing and
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