A Transistor-Level Test Strategy for C2MOS...

YALE UNIVERSITY

A Transistor-Level Test Strategy for C2MOS MOUSETRAP Asynchronous Pipelines

Feng Shi & Yiorgos MakrisElectrical Engineering Department

Outline

• Background• Test requirements and previous work• Testing for stuck-at faults• Testing for transistor-level faults

– Motivation– Stuck-open faults– Stuck-short faults

• Conclusion

Background: C2MOS Logic

A General C2MOS Logic Gate

Background: Static MOUSETRAP

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Data in Data out

Stage NStage N-1 Stage N+1

En

LogicLogic LogicLogic

Data Latch

LogicLogic

Delay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Transition signaling for handshake signalsLevel signaling for latch control

Background: C2MOS MOUSETRAP

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Data in Data out

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

C2M

OS

C2M

OS

C2M

OS

Handshaking Logic

Processing Logic

Test Requirements

• Delay faults:– Degrade the performance– Violate the timing constraints

• Gate-level stuck-at faults:– Basic fault model – Gate remodeling enables the

use of static CMOS MOUSETRAP test methods• Transistor-level faults: (focus of this talk)

– Stuck-at fault model is not sufficient, especially for dynamic logic

– Some stuck-at faults in C2MOS are in fact transistor-level faults

Test for Stuck-at Faults

Test generation for I/O stuck-at faults through remodeling

Test for Stuck-at FaultsExploit test tools for static CMOS MOUSETRAP:• Testing the handshaking logic

– SPIN-SIM [ITC’04]: A logic and fault simulator for SI circuits, extended for DI, QDI circuits and for handling timing constraints

– SPIN-TEST [ICCAD’04]: A fault-simulation-based ATPG tool

– SPIN-PAC [ASP-DAC’05]: A test compaction tool that combines multiple SIC vectors into a single MIC vector

• Testing the processing logic– At initial state all latches are transparent– The processing logic can be treated as a whole

combinational block– Use any ATPG tool for combinational circuits

Transistor-Level Faults

Stuck-Open

Stuck-Short

Why Transistor-Level Faults

SA0

Stuck-Open

Testing Transistor-Level Faults

• Transistor stuck-open faults– Testing C2MOS logic gates– Testing handshaking logic– Testing processing logic

• Transistor stuck-short faults– Testing C2MOS logic gates– Testing handshaking logic– Testing processing logic

Stuck-Open Faults in C2MOS Gate

Stuck-Open

0

1

Test generation similar to CMOS gate

Stuck-Open Faults in C2MOS Gate

Stuck-Open

0 1

…

0

1

…

V1 V1: Set output to 1

…

0

1

…

V2

DD

V2: Test SA1 at output

Stuck-Open Faults in Handshake Logic

• Test pattern generation procedure:– Generate test patterns for the faulty gate– Select functional test patterns that exercise the

faulty gate– Append test patterns that propagate fault effect

to the primary outputs• Fault coverage:

– Detects faults in identity gates and XNOR gates– Cannot detect faults in keeper inverters

Stuck-Open Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck-Open

Stuck-Open Faults in Handshake Logic

Stuck-Open

V1: A = 1, En = 1

DD

V2: A = 0, En = 1

1

0

1

V1

1

0

0

1

V2

0

Stuck-Open Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck-Open

VALUE = 0VALUE = 1VALUE = DVALUE = Ď

Objective:Initial statev1: req=1, En=1

v2: req=0, En=1

Stuck-Open Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck Open

VALUE = 0VALUE = 1VALUE = DVALUE = Ď

v1: req=1, En=1v2: req=0, En=1

Objective:V1: reqN-1=1

Stuck-Open Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck-Open

VALUE = 0VALUE = 1VALUE = DVALUE = Ď

v1: req=1, En=1v2: req=0, En=1

Objective:V2: ackN+1=1

Stuck-Open Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck-Open

VALUE = 0VALUE = 1VALUE = DVALUE = Ď

v1: req=1, En=1v2: req=0, En=1

Objective:V3: reqN-1=0

Stuck-Open Faults in Processing Logic

Exploit tools for CMOS logic through remodeling(gates are enabled)• Faults in pull-up/pull-down networks can be

detected as in CMOS logic • Faults at the enable PMOS(NMOS)

– Step 1: set the gate output to 1(0)– Step 2: test for a stuck-at-1(0) fault at the gate

output

Stuck-Short Faults in C2MOS Gate

Test generation similar to CMOS gate: IDDQ tests

Stuck-Short

0

1

Stuck-Short Faults in C2MOS Gate

Stuck Short

0 1

…

0

1

…

V1

V1: Set output to 1

1

0

V2V2: Disable the gate

D D

…

1

0

…

V3: Set output to 0 ifgate was enabled

V3

Stuck-Short Faults in Handshake Logic

• Test pattern generation procedure:– Generate test patterns for the faulty gate– Select functional test patterns that exercise the

faulty gate– Append test patterns that propagate fault effect

to the primary outputs (Voltage tests only)• Fault coverage:

– All faults through IDDQ/voltage tests

Stuck-Short Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

Stuck-Short

Stuck-Short Faults in Handshake Logic

Stuck-Short

IDDQ test: A = 1, B = 1

1

0

1

V

1

Stuck-Short Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

VALUE = 0VALUE = 1

Objective:ack=0,done=1

Initial state

Stuck-Short

Stuck-Short Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

VALUE = 0VALUE = 1

Objective:ack=0,done=1

V1: reqN-1=1

Stuck-Short

Stuck-Short Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

VALUE = 0VALUE = 1

Objective:ack=0,done=1

V2: reqN-1=0

Stuck-Short

Stuck-Short Faults in Handshake Logic

reqN

ackN-1

reqN+1

ackNLatch Controller

doneN

Stage NStage N-1 Stage N+1

EnDelay Delay Delay

ackN-2reqN-1

ackN+1

reqN+2

Identity

VALUE = 0VALUE = 1

Objective:ack=0,done=1

V3: reqN-1=1, fault detected through IDDQ

Stuck-Short

Stuck-Short Faults in Processing Logic

Utilize tools for CMOS logic through remodeling• Faults in pull-up/pull-down networks can be

tested as in CMOS logic (gates are enabled)• Faults at the enable PMOS (NMOS)

– Step 1: test for a SA0(1) fault at the gate output– Step 2: disable the gate by applying a test

sequence to handshaking logic– Step 3: could set the gate output to 0(1)– Step 4: propagate the fault effect by applying a

test sequence to handshaking logic

Conclusion• Proposed method for SA faults makes use of tools

for CMOS pipelines through remodeling• Proposed method for transistor-level faults

– Based on testing a single C2MOS gate– Generates functional test patterns for testing

handshaking logic– Uses ATPG tools for CMOS circuits for testing

processing logic• Results

– Very high fault coverage for both SA and transistor-level SO, SS faults

– No performance/area overhead