Accelerating Innovation: Why Google’s TPU was just the start · 2020. 8. 13. · Accelerating...

Accelerating Innovation: Why Google’s TPU was just the start

RISC-V Summit, Santa Clara, Dec 05, 2018Michael Gielda, mgielda@antmicro.com

Machine Learning is exploding(capabilities and needs)

Machine Learning is exploding(capabilities and needs)

● Google: 2 years to go!

Keeping up with ML: TPU

● Google wanted to keep up with evolving software and compute needs

● without TPU, Google estimates it would not be able to provide level of service required by Duplex and other voice-related services

● only took 1.5 years to create and deploy - impressive!

● is that fast enough? - obviously not

Keeping up with ML: RISC-Vmaking ASICs more free - and faster

● open ISA allowing freedom for cores● companies like SiFive making ASIC design turnaround faster● but is this enough?

● open ISA allowing freedom for cores● companies like SiFive making ASIC design turnaround faster● but is this enough?● no!

○ non-CPU stuff still hard○ supply chain still a pain○ where are the Linux-enabled cores?○ where are (more) developers?○ we’re on a good path, but going too slow

Keeping up with ML: RISC-Vis this enough?

● if RISC-V is like Linux (as we keep saying)● we need the GNUs, Apaches, Kubernetes,

Dockers, Caffes, TensorFlows...

Keeping up with ML: RISC-VLinux analogy

● if RISC-V is like Linux (as we keep saying)● we need the GNUs, Apaches, Kubernetes,

Dockers, Caffes, TensorFlows... ● we have a “language” the computer speaks,

now we need to write our books and build our libraries

Keeping up with ML: RISC-VLinux analogy

Comparison: TensorFlow

● Google is a leader in ML space, but still needs help● Open-sourced TensorFlow (their ‘crown jewel’ of ML)● Building AIY kits for masses● Free courses, massive conferences● Calling community, demos, less obvious use cases

How can we be more like software,How do we get the community?

● increase turnaround - faster is not enough!○ we need instant!

● eliminate barriers of entry○ just cores are not enough○ making chips for $100000 is not enough○ > $1000 Linux devboards are not enough

Where can we get instantturnaround and accessibility?

FPGA!

● like a flexible chip● write code, deploy, test!● turnaround time? decent!● bugs? not a (big) problem● entry barriers: bearable!● fairly cheap hardware● SW people: hey, this is quite cool!

FPGA

SW ASICsFPGA

FPGA - not just a bridge

● flexible I/O for heterogeneous chips ● huge adaptability, very suitable for ML tasks requiring this● we believe their role as we go forward is grossly underestimated

Problems with FPGA

● quite niche● bearable… decent... fairly...● tools, methodologies

Problems with FPGA are solvable

● quite niche● bearable… decent... fairly…● tools, methodologies● all solvable problems!

○ popularize○ build out community○ improve and tend for the open source IP and tools ecosystem○ acknowledge the important role

● bridging HW and SW will allow us to tap incredible resources - developers, frameworks, methodologies...

Open source

● all this is only possible if we use open source● the collaboration, cross-development, spontaneous

innovation we need is only achievable if we share● only way for software people to care!

Building around the core

LiteX/VexRiscv 32-bit open Linux-enabled SoC

● Project by Antmicro and Western Digital to combine open source IP ecosystem with RISC-V

● enable powerful but low-cost development board with Microsemi PolarFire

● improve RISC-V Linux support for Soft CPUs

Thales Triple-Modular-Redundancy demonstrator

● Rapid development for Thales by Antmicro● Based fully on open source and released

last week● Enables Thales to turn RISC-V involvement

into a collaborative experience

New platforms, toolsand methodologies

PolarFire SoC: Enabling the Freedom to Innovate

PolarFire SoC: USD 3000 devkit

PolarFire SoC: Renode, a FOSS development platformwith PFSoC support in ver. 1.6

Renode - a new approach to complex embedded systems development

Continuous Integration workflow

TensorFlow Lite on RISC-V with Renode

Reaching out

Calling for a RISC-V SoftCPU Task Group

RISC-V SoftCPU contest - resolutionBear with us!

DATE OSDA workshop

EU SRA to include open hardware

● work by Antmicro, Thales and others to make open source hardware a strategic aim of the EU

● managed to get a lot of good feedback and content in

● document now in public review

”With this Open Source (RISC-V) ISA and its many implementations, Europe could emerge as a leader in the broadly understood open hardware movement given its rich tradition of open technologies, diverse ecosystem, and a strong industry like e.g. automotive which could be a major customer.”

Summary

Summary

● lot of work to be done to keep up with ML needs● FPGAs and open source are central● Antmicro, Google, Thales, Western Digital, SiFive, Microsemi, Lattice, SymbioticEDA and others

actively building out ecosystem○ reference designs and IP○ popularisation○ development platforms○ standardised tools○ new workflows

● collaborate with us on those goals - they are not just a niche activity, they’re essential to the future of Machine Learning

THANK YOUFOR YOUR ATTENTION!