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THE ENTANGLING INSTRUCTION PREFETCHER
Alberto Ros Alexandra Jimborean
University of Murcia, Spain
May 31, 2020
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 1 / 10
MOTIVATION: TIMELINESS
time
access
hitdone
access
miss
latency
filldone
⇒
prefetch
timely
fill
access
hitdone
Timely prefetchesfor all misses:
Coverage 100%
And only for misses:Accuracy 100%
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 2 / 10
MOTIVATION: TIMELINESS
time
access
hitdone
access
miss
latency
filldone
⇒
prefetch
timely
fill
access
hitdone
Timely prefetchesfor all misses:
Coverage 100%
And only for misses:Accuracy 100%
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 2 / 10
MOTIVATION: TIMELINESS
time
access
hitdone
access
miss
latency
filldone
⇒
prefetch
timely
fill
access
hitdone
Timely prefetchesfor all misses:
Coverage 100%
And only for misses:Accuracy 100%
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 2 / 10
MOTIVATION: TIMELINESS
time
access
hitdone
access
miss
latency
filldone
⇒
prefetch
timely
fill
access
hitdone
Timely prefetchesfor all misses:
Coverage 100%
And only for misses:Accuracy 100%
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 2 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch lprefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destination
Quantum entanglement(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
CONCEPT OF ENTANGLED ACCESSES
access l
miss
latency
filldone
late
ncy
prefetch l
prefetch l
fill
hitdone
access aaccess b
access c
access d
access e
enta
ngle
d
source
destinationQuantum entanglement
(Image: c© MARK GARLICK/SCIENCE
PHOTO LIBRARY/Getty)
THE ENTAGLING
PREFETCHER
FOR INSTRUCTIONS
—EPI—
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 3 / 10
ENTANGLING CACHE LINES HEAD OF BASIC BLOCKS
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e enta
ngle
d
source
destination
a
b c de
l
Cache line
{Basicblock
Heads of basic block
enta
ngle
d
source
destination
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 4 / 10
ENTANGLING CACHE LINES HEAD OF BASIC BLOCKS
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e enta
ngle
d
source
destination
a
b c de
l
Cache line
{Basicblock
Heads of basic block
enta
ngle
d
source
destination
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 4 / 10
ENTANGLING CACHE LINES HEAD OF BASIC BLOCKS
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e enta
ngle
d
source
destination
a
b c de
l
Cache line
{Basicblock
Heads of basic block
enta
ngle
d
source
destination
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 4 / 10
ENTANGLING CACHE LINES HEAD OF BASIC BLOCKS
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e enta
ngle
d
source
destination
a
b c de
l
Cache line
{Basicblock
Heads of basic block
enta
ngle
d
source
destination
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 4 / 10
WHAT TO PREFETCH ON AN ACCESS TO a?
a
b c de
{Basicblock
l
entangled
xentangled
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 5 / 10
WHAT TO PREFETCH ON AN ACCESS TO a?
a
b c de
{Basicblock
l
entangled
xentangled
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 5 / 10
WHAT TO PREFETCH ON AN ACCESS TO a?
a
b c de
{Basicblock
l
entangled
xentangled
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 5 / 10
DESIGN OF EPI
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FINDING BASIC BLOCKS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l
sameline+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FINDING BASIC BLOCKS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FINDING BASIC BLOCKS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l
sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FINDING BASIC BLOCKS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l
sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
- Tag- Timestamp
access l
miss
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
sa 2
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
late
ncy
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ENTANGLING CACHE LINES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
late
ncy
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ISSUING PREFETCHES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - ISSUING PREFETCHES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FIXING LATE PREFETCHES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - FIXING LATE PREFETCHES
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
- Tag- Timestamp
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - CONFIDENCE FOR ENTANGLED PAIRS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
2-bit saturatedcounter- New pair: 3- Late pref: --- Wrong pref: --- Hit pref: ++
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - CONFIDENCE FOR ENTANGLED PAIRS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
- Access bit- Entangled-source- Access bit- Entangled-source- Access bit- Entangled-source
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI - MERGING BASIC BLOCKS
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
DESIGN OF EPI
L1-I cacheway 0
...
way 1
... ...
way 7
...
L1-I access
Basic blockheadsize
bb?
0 a
1 b c d
2 e
0 l sameline
+1
new
Update basic block size (s)
EntangledTable
prefetch l
fill
access l
hitdone
access a
access b
access c
access d
access e
MSHR...
Miss
Next cache level (L2)
access l
miss
latency
filldone
access a
access b
access c
access d
access e
enta
ngle
d
Fill
Latency
History
...
Update history
Update entangled destination (dx )
s d1 d2a 2 l
l
Prefetches
XPQ...
PQ...
prefetch l
fill
access l
miss
done
access a
BB size
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 6 / 10
COMPRESSING DESTINATIONS
Mode 1
m
3
destination
58
conf
2
Mode 2
m
3
dst
28
conf
2
dst
28
conf
2
Mode 3
m
3
dst
18
conf
2
dst
18
conf
2
dst
18
conf
2
Mode 4
m
3
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
Mode 5
m
3
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
Mode 6
m
3
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 7 / 10
COMPRESSING DESTINATIONS
Mode 1
m
3
destination
58
conf
2
Mode 2
m
3
dst
28
conf
2
dst
28
conf
2
Mode 3
m
3
dst
18
conf
2
dst
18
conf
2
dst
18
conf
2
Mode 4
m
3
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
Mode 5
m
3
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
Mode 6
m
3
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 7 / 10
COMPRESSING DESTINATIONS
Mode 1
m
3
destination
58
conf
2
Mode 2
m
3
dst
28
conf
2
dst
28
conf
2
Mode 3
m
3
dst
18
conf
2
dst
18
conf
2
dst
18
conf
2
Mode 4
m
3
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
dst
13
conf
2
Mode 5
m
3
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
dst
10
c
2
Mode 6
m
3
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
dst
8
c
2
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 7 / 10
RESULTS
Prefetcher Size (KB) Norm. IPC Coverage Accuracy Misses (%)
No-IPref 0.00 1.000 0.000 0.000 23.055
NextLine 0.00 1.085 0.244 0.307 17.754EPI-4w 14.15 1.155 0.639 0.736 8.575EPI-8w 27.25 1.253 0.850 0.764 2.540EPI-12w 40.36 1.281 0.921 0.773 1.084EPI-16w 53.36 1.288 0.941 0.774 0.805EPI-20w 66.46 1.290 0.946 0.774 0.736EPI-24w 79.46 1.291 0.947 0.774 0.717EPI-28w 92.46 1.292 0.949 0.774 0.705EPI-32w 105.56 1.293 0.949 0.774 0.697EPI 127.98 1.295 0.956 0.770 0.623
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 8 / 10
RESULTS
Prefetcher Size (KB) Norm. IPC Coverage Accuracy Misses (%)
No-IPref 0.00 1.000 0.000 0.000 23.055NextLine 0.00 1.085 0.244 0.307 17.754
EPI-4w 14.15 1.155 0.639 0.736 8.575EPI-8w 27.25 1.253 0.850 0.764 2.540EPI-12w 40.36 1.281 0.921 0.773 1.084EPI-16w 53.36 1.288 0.941 0.774 0.805EPI-20w 66.46 1.290 0.946 0.774 0.736EPI-24w 79.46 1.291 0.947 0.774 0.717EPI-28w 92.46 1.292 0.949 0.774 0.705EPI-32w 105.56 1.293 0.949 0.774 0.697EPI 127.98 1.295 0.956 0.770 0.623
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 8 / 10
RESULTS
Prefetcher Size (KB) Norm. IPC Coverage Accuracy Misses (%)
No-IPref 0.00 1.000 0.000 0.000 23.055NextLine 0.00 1.085 0.244 0.307 17.754EPI-4w 14.15 1.155 0.639 0.736 8.575EPI-8w 27.25 1.253 0.850 0.764 2.540EPI-12w 40.36 1.281 0.921 0.773 1.084
EPI-16w 53.36 1.288 0.941 0.774 0.805EPI-20w 66.46 1.290 0.946 0.774 0.736EPI-24w 79.46 1.291 0.947 0.774 0.717EPI-28w 92.46 1.292 0.949 0.774 0.705EPI-32w 105.56 1.293 0.949 0.774 0.697EPI 127.98 1.295 0.956 0.770 0.623
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 8 / 10
RESULTS
Prefetcher Size (KB) Norm. IPC Coverage Accuracy Misses (%)
No-IPref 0.00 1.000 0.000 0.000 23.055NextLine 0.00 1.085 0.244 0.307 17.754EPI-4w 14.15 1.155 0.639 0.736 8.575EPI-8w 27.25 1.253 0.850 0.764 2.540EPI-12w 40.36 1.281 0.921 0.773 1.084EPI-16w 53.36 1.288 0.941 0.774 0.805EPI-20w 66.46 1.290 0.946 0.774 0.736EPI-24w 79.46 1.291 0.947 0.774 0.717EPI-28w 92.46 1.292 0.949 0.774 0.705EPI-32w 105.56 1.293 0.949 0.774 0.697EPI 127.98 1.295 0.956 0.770 0.623
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 8 / 10
CONCLUDING REMARKS
Timeliness as a key property
Entangles heads of basic blocks to trigger timelyprefetches
Good performance/area trade-off
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 9 / 10
THE ENTANGLING INSTRUCTION PREFETCHER
Alberto Ros Alexandra Jimborean
University of Murcia, Spain
May 31, 2020
ECHO, ERC Consolidator Grant (No 819134)
Alberto Ros, Alexandra Jimborean 1st Instruction Prefetching Championship May 31, 2020 10 / 10
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