AMNESIAC: Amnesic Automatic Computer€¦ · AMNESIAC: Amnesic Automatic Computer Trading...

AMNESIAC: Amnesic Automatic ComputerTrading Computation for Communication for Energy Efficiency

Ismail Akturk and Ulya R. KarpuzcuUniversity of Minnesota, Twin Cities

{aktur002, ukarpuzc}@umn.edu

Motivation

Energy of on chip communication normalized to computation

Technology Node 40nm

1.55x 5.77x

AMNESIAC: Amnesic Automatic Computer

Keckler, S. W., Dally, W. J., Khailany, B., Garland, M., and Glasco, D. “GPUs and the Future of Parallel Computing”, IEEE Micro 31, 5 (2011).

Motivation

(Re)computing becomes cheaper than memorizing and retrieving data

Keckler, S. W., Dally, W. J., Khailany, B., Garland, M., and Glasco, D. “GPUs and the Future of Parallel Computing”, IEEE Micro 31, 5 (2011).

Energy of on chip communication normalized to computation

Technology Node 40nm

1.55x 5.77x

Amnesic* Automatic Computer• Idea: Replace energy-hungry load with sequence of instructions

*amnesia: noun a partial or total loss of memory (origin late 18th cent.: from Greek amnēsia ‘forgetfulness’)

Amnesic* Automatic Computer• Idea: Replace energy-hungry load with sequence of instructions• Scope

• How to determine which data values to recompute• How to identify instructions to recompute data values• How to protect architectural state during recomputation• How to orchestrate recomputation at runtime

5AMNESIAC: Amnesic Automatic Computer

*amnesia: noun a partial or total loss of memory (origin late 18th cent.: from Greek amnēsia ‘forgetfulness’)

How to determine which data values to recompute

memory

load A

memory

load B

memory

load C

Eld,B ? Erc,B Eld,C ? Erc,CEld,A ? Erc,A

Recomputation Slice (RSlice)

Overview• Amnesic Compiler

• Identifies independent RSlices• Annotates RSlices: RCMP, REC, RTN

• Amnesic Scheduler• Decides when to recompute• Can use various policies

• Compiler• First-Level Cache Miss - FLC• Last-Level Cache Miss - LLC

• Amnesic Scheduler• Decides when to recompute• Can use various policies

• Compiler• First-Level Cache Miss - FLC• Last-Level Cache Miss - LLC

• Amnesic Microarchitecture• Prevents corruption of architectural state• Makes RSlice inputs available at the time of recomputation

Amnesic Microarchitecture

Source and Destination Registers

RegisterFile[#] -> SFile[#]

Renamer SFile

Leaf Address Non-Recomputable Inputs

Renamer SFile

RSlice Instructions

IBuff Hist

Renamer SFile

Putting It All Together: Default Execution

RSlice Instructions

IBuff Hist

Renamer SFile

MemoryorRegisterFile

Putting It All Together: Default Execution

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

Putting It All Together: During Recomputation

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

4Leaf Address Non-Recomputable Inputs

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

ExecutionUnits

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

ExecutionUnits

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

ExecutionUnits

RSlice Instructions

IBuff Hist

Renamer SFile

Fetch Logic

ExecutionUnits

Evaluation Setup

• Benchmarks: SPEC2006, NAS, Parsec, Rodinia• 33 benchmarks evaluated, 11 of them show > 10% EDP gain

• Amnesic compiler pass mimicked by binary generator Pintool• Microarchitecture and scheduler implemented in Snipersim

Energy-Delay Product

mcf sx cg is ca fs fe rt bp bfs sr

up to 87% (24.92% on average ) EDP gain obtained

Instruction Mix

Benchmark% increase in

instruction count% decrease in load

mcf 4.47 6.19

sx 4.55 6.68

cg 3.97 2.11

is 17.97 49.99

ca 7.38 7.95

fs 1.83 3.08

fe 3.55 1.75

rt 1.97 6.08

bp 31.89 55.55

bfs 1.20 60.93

sr 20.02 23.33

mcf 4.47 6.19

sx 4.55 6.68

cg 3.97 2.11

is 17.97 49.99

ca 7.38 7.95

fs 1.83 3.08

fe 3.55 1.75

rt 1.97 6.08

bp 31.89 55.55

bfs 1.20 60.93

sr 20.02 23.33

Instruction Mix

49.99% reduction in loads, at the expense of 17.97% more instructions

mcf 4.47 6.19

sx 4.55 6.68

cg 3.97 2.11

is 17.97 49.99

ca 7.38 7.95

fs 1.83 3.08

fe 3.55 1.75

rt 1.97 6.08

bp 31.89 55.55

bfs 1.20 60.93

sr 20.02 23.33

Instruction Mix

translates into 74.68% reduction in (load) energy

49.99% reduction in loads, at the expense of 17.97% more instructions

RSlice Length

sx bfs

RSlice Length

sx bfs

majority of RSlices (78.32%) have less than 10 instructions

Summary• Amnesic execution can minimize power and performance overhead of

• Data retrieval• Data communication

• Amnesic execution makes the workload more compute-intensive• Better use of classic architectures

• Up to 87% improvement in energy-delay product (avg. 24%)

Questions and Comments

Please send your questions and comments to

aktur002@umn.edu

AMNESIAC: Amnesic Automatic ComputerTrading Computation for Communication for Energy Efficiency

Ismail Akturk and Ulya R. KarpuzcuUniversity of Minnesota, Twin Cities

{aktur002, ukarpuzc}@umn.edu

AMNESIAC: Amnesic Automatic Computer€¦ · AMNESIAC: Amnesic Automatic Computer Trading...

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