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ATF15xx-DK3 Development Kit..............................................................................................
User Guide
ATF15xx-DK3 Development Kit User Guide i
3605B–PLD–05/06
Table of Contents
Section 1Introduction ........................................................................................... 1-1
1.1 CPLD Development/ Programmer Kit .......................................................1-11.2 Kit Contents ..............................................................................................1-11.3 Kit Features...............................................................................................1-1
1.3.1 CPLD Development/Programmer Board ............................................1-1
1.3.2 Logic Doubling CPLDs .......................................................................1-2
1.3.3 CPLD ISP Download Cable................................................................1-2
1.3.4 PLD Software CD-ROM......................................................................1-2
1.4 Device Support .........................................................................................1-21.5 System Requirements...............................................................................1-31.6 Ordering Information .................................................................................1-31.7 References................................................................................................1-4
1.7.1 ProChip Designer ...............................................................................1-4
1.7.2 Atmel-WinCUPL .................................................................................1-4
1.7.3 ATMISP ..............................................................................................1-4
1.7.4 POF2JED ...........................................................................................1-4
1.8 Technical Support .....................................................................................1-4
Section 2Hardware Description ........................................................................... 2-1
2.1 Atmel CPLD Development/ Programmer Board........................................2-1
2.1.1 7-segment Displays with Selectable Jumpers ....................................2-2
2.1.2 LEDs with Selectable Jumpers...........................................................2-5
2.1.3 Push-button Switches with Selectable Jumpers for I/O Pins..............2-6
2.1.4 Push-button Switches with Selectable Jumpers for GCLRand OE1 Pins .....................................................................................2-8
2.1.5 2 MHz Oscillator and Clock Selection Jumper ...................................2-9
2.1.6 VCCIO and VCCINT Voltage Selection Jumpers and LEDs ............2-10
2.1.7 ICCIO and ICCINT Jumpers.............................................................2-10
2.1.8 Voltage Regulators ...........................................................................2-10
2.1.9 Power Supply Switch and Power LED..............................................2-10
2.1.10 Power Supply Jack and Power Supply Header ................................2-10
2.1.11 JTAG ISP Connector and TDO Selection Jumper............................2-11
2.2 Socket Adapter Board.............................................................................2-122.3 Atmel CPLD ISP Download Cable ..........................................................2-13
Table of Contents
ii ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Section 3CPLD Design Flow Tutorial .................................................................. 3-1
3.1 Create a Project using the “New Project Wizard” .....................................3-13.2 Add a Design File......................................................................................3-73.3 Synthesize the VHDL Design....................................................................3-73.4 Fit the Synthesized Design File ................................................................3-83.5 Program and Verify Design.....................................................................3-10
Section 4Schematic Diagrams and VHDL File .................................................... 4-1
ATF15xx-DK3 Development Kit User Guide 1-1
3605B–PLD–05/06
Section 1
Introduction
1.1 CPLD Development/ Programmer Kit
The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK3) is a completedevelopment system and an In-System Programming (ISP) programmer for theATF15xx family of industry standard pin compatible Complex Programmable LogicDevices (CPLDs) with Logic Doubling® features. This kit provides designers a very quickand easy way to develop prototypes and evaluate new designs with an ATF15xx ISPCPLD. The ATF15xx family of ISP CPLDs includes the ATF15xxAS, ATF15xxASL,ATF15xxASV, ATF15xxASVL, and ATF15xxBE CPLDs. With the availability of the dif-ferent Socket Adapter Boards to support all the package types(1) offered in the ATF15xxfamily of ISP CPLDs, this CPLD Development/Programmer Board can be used as anISP programmer to program the ATF15xx ISP CPLDs in all the available packagetypes(1) through the industry standard JTAG interface (IEEE 1149.1).
1.2 Kit Contents CPLD Development/Programmer Board
44-pin TQFP Socket Adapter Board (P/N: ATF15xx-DK3-SAA44)(2)
Atmel CPLD ISP Multi-Volt (MV) Download Cable
Atmel PLD Software CDs (includes ProChip Designer®, Precision RTL Synthesis, ModelSim, latest ProChip patch, Atmel-WinCUPL™, and other EPLD software)
Two 44-pin TQFP Sample Devices (one ATF1502BE and one ATF1504ASV)
Notes: 1. Socket adapter board for 100-pin PQFP is not offered.2. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other Socket
Adapter Boards are sold separately. Please refer to Section 1.6 for ordering informa-tion of the Socket Adapter Boards.
1.3 Kit Features
1.3.1 CPLD Development/Programmer Board
10-pin JTAG-ISP port
Regulated power supply circuits for 9V DC power source
Selectable 5V, 3.3V, 2.5V, or 1.8V I/O voltage supply
Selectable 1.8V, 3.3V, or 5.0V core voltage supply
Introduction
1-2 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
44-pin TQFP Socket Adapter Board
Headers for I/O pins of the ATF15xx device
2 MHz Crystal Oscillator
Four 7-segment LED displays
Eight individual LEDs
Eight push-button switches
Global Clear and Output Enable push-button switches
Current measurement jumpers
1.3.2 Logic Doubling CPLDs
ATF1502BE 1.8V low-power 32-macrocell ISP CPLD with Logic Doubling architecture
ATF1504ASV 3.3V 64-macrocell ISP CPLD with Logic Doubling architecture
1.3.3 CPLD ISP Download Cable
5V/3.3V/2.5V/1.8V ISP Download Cable for PC Parallel Printer (LPT) Port
1.3.4 PLD Software CD-ROM
Free Atmel-WinCUPL Design Software
ProChip Designer v4.0
ProChip Designer v4.0 Patch
Precision RTL Synthesis
ModelSim
Atmel CPLD ISP Software (ATMISP)
POF2JED Conversion Utility
User Guides and Tutorials
1.4 Device Support The Atmel CPLD Development/Programmer Board supports the following devices in allspeed grades and packages (except 100-PQFP):
ATF1502BE ATF1508ASV/ASVL
ATF1502AS/ASL ATF1502ASV
ATF1504BE ATF1504ASV/ASVL
ATF1504AS/ASL ATF1508AS/ASL
Introduction
ATF15xx-DK3 Development Kit User Guide 1-3
3605B–PLD–05/06
1.5 System Requirements
The minimum hardware and software requirements to program an ATF15xx ISP CPLDdesigned using the ProChip Designer Software on the CPLD Development/ProgrammerBoard through the Atmel CPLD ISP Software (ATMISP) V6.0 or later are:
Pentium® or Pentium-compatible microprocessor-based computer
Windows XP®, Windows® 98, Windows NT® 4.0, or Windows 2000
64-MByte RAM
200-MByte free hard disk space
Windows-supported mouse
Available parallel printer (LPT) port
9V DC power supply with 500 mA of supply current
SVGA monitor (800 x 600 resolution)
1.6 Ordering Information
Other socket adapters to support other packages will be available in the near future.
Part Number Description
ATF15xx-DK3 Atmel CPLD Development/Programmer Kit(includes ATF15xxDK3-SAA44)
ATF15xxDK3-SAA100 100-pin TQFP Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ44 44-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAJ84 84-pin PLCC Socket Adapter Board for DK3 Board
ATF15xxDK3-SAA44 44-pin TQFP Socket Adapter Board for DK3 Board
Introduction
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1.7 References To help PLD designers use the different Atmel PLD software, documentation such ashelp files, tutorials, application notes/briefs, and user guides are available.
1.7.1 ProChip Designer
1.7.2 Atmel-WinCUPL
1.7.3 ATMISP
1.7.4 POF2JED
1.8 Technical Support
For technical support on any Atmel PLD related issues, please contact Atmel PLD Appli-cations Group at:
URL: www.atmel.com/dyn/products/support.asp
FAQ: www.atmel.com/dyn/products/tech_support.asp?faq=y
Hotline: 1-408-436-4333
Email : pld@atmel.com
ProChip Desinger Help Files
From the ProChip Designer main window, click on HELP and then select PROCHIP DESIGNER HELP.
Tutorials From the ProChip Designer main window, click on HELP and then select TUTORIALS.
Known Problems & Solutions
From the ProChip Designer main window, click on HELP and then select REVIEW KPS.
Help Files From the Atmel-WinCUPL main window, click on HELP and then select CONTENTS.
CUPL Programmers Reference Guide
From the Atmel-WinCUPL main window, click on HELP and then select CUPL PROGRAMMERS REFERENCE.
Tutorials From the Atmel-WinCUPL main window, click on HELP, select ATMEL INFO and then select TUTORIAL1.PDF.
Known Problems & Solutions
From the Atmel-WinCUPL main window, click on HELP, select ATMEL INFO and then select CUPL_BUG.PDF.
Help Files From the ATMISP main window, click on HELP and then select ISP HELP.
Tutorials From the ATMISP main window, click on HELP, and then select ATMISP TUTORIAL.
Known Problems & Solutions
Using Windows Explorer, go to the directory where ATMISP is installed and open the README.TXT file through any ASCII text editor.
ATF15xx Conversion Application Brief
from the POF2JED main window, click on HELP and then select CONVERSION OPTIONS.
ATF15xx-DK3 Development Kit User Guide 2-1
3605B–PLD–05/06
Section 2
Hardware Description
2.1 Atmel CPLD Development/ Programmer Board
Atmel CPLD Development/Programmer Board along with the Socket Adapter Board asshown in Figure 2-1 contains many features that designers will find very useful whendeveloping, prototyping, or evaluating their ATF15xx CPLD design. Features such aspush-button switches, LEDs, 7-segment displays, 2-MHz crystal oscil lator,5V/3.3V/2.5V/1.8V VCCI/O selector, 1.8V/3.3V/5.0V VCCINT selector, JTAG-ISP port,and socket adapters make this a very versatile starter/development kit and an ISP pro-grammer for the ATF15xx family of JTAG-ISP CPLDs.
Figure 2-1. CPLD Development/Programmer Board with 44-pin TQFP Socket Adapter Board
VoltageRegulators
GCLRSwitch
GOESwitch
VccIOSelector
VCCINT Selector
VccIO LED
VccINT LED
Power LEDClock Selector
Power Switch
Oscillator
Power Supply Jack
Power Supply Header
JTAG Cascade Jumper
JTAG ISP Header
7-SegmentDisplays
ATF15xxDK3-SAA44Socket Adapter Board
User I/OPin Headers
LEDs
Device Socket
Push-Button Switches
IccINT Jumper
IccIO Jumper
Hardware Description
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2.1.1 7-segment Displays with Selectable Jumpers
Atmel CPLD Development/Programmer Board contains four seven-segment displays toallow the designers to observe the outputs of the ATF15xx CPLD. These four displaysare labeled DSP1, DSP2, DSP3, and DSP4, and have common anode LEDs with thecommon anode lines connected to VCCIO (I/O supply voltage for the CPLD) throughseries resistors with selectable jumpers labeled JPDSP1, JPDSP2, JPDSP3, orJPDSP4. These jumpers can be removed to disable the displays by unconnecting theVCCIO to the displays. Individual cathode lines are connected to the I/O pins of theATF15xx CPLD on the CPLD Development/Programmer Board. To turn on a particularsegment including the DOT of a display, the corresponding ATF15xx I/O pin connectedto this LED segment must be in a logic low state with the corresponding selectablejumper set. Hence, the outputs of the ATF15xx need to be configured as active-low out-puts in the design file. These displays work best at 2.5V VCCIO or higher.
Each segment of each display is hard-wired to one specific I/O pin of the ATF15xx. Forthe higher pin count devices (100-pin and larger), all seven segments and the DOT seg-ments of the four displays are connected to the I/O pins of the ATF15xx. However, forthe lower pin count devices, only a subset of the displays (1st and 4th displays) are con-nected to the ATF15xx’s I/O pins. Tables 2-1, 2-2, 2-3, and 2-4 show the connections for7-segment displays to the ATF15xx in different package types. The circuit schematic ofthe displays and jumpers is shown in Figure 2-2.
Figure 2-2. Circuit Diagram of 7-segment Display and Jumpers
Hardware Description
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Table 2-1. Connections of ATF15xx 44-pin TQFP to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 27 3/A NC
1/B 33 3/B NC
1/C 30 3/C NC
1/D 21 3/D NC
1/E 18 3/E NC
1/F 23 3/F NC
1/G 20 3/G NC
1/DOT 31 3/DOT NC
2/A NC 4/A 3
2/B NC 4/B 10
2/C NC 4/C 6
2/D NC 4/D 43
2/E NC 4/E 35
2/F NC 4/F 42
2/G NC 4/G 34
2/DOT NC 4/DOT 11
Table 2-2. Connections of ATF15xx 44-pin PLCC to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 33 3/A NC
1/B 39 3/B NC
1/C 36 3/C NC
1/D 27 3/D NC
1/E 24 3/E NC
1/F 29 3/F NC
1/G 26 3/G NC
1/DOT 37 3/DOT NC
2/A NC 4/A 9
2/B NC 4/B 16
2/C NC 4/C 12
2/D NC 4/D 5
2/E NC 4/E 41
2/F NC 4/F 4
2/G NC 4/G 40
2/DOT NC 4/DOT 17
Hardware Description
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Table 2-3. Connections of ATF15xx 84-pin PLCC to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 68 3/A 22
1/B 74 3/B 28
1/C 70 3/C 25
1/D 63 3/D 21
1/E 58 3/E 16
1/F 65 3/F 17
1/G 61 3/G 12
1/DOT 73 3/DOT 29
2/A 52 4/A 5
2/B 57 4/B 10
2/C 55 4/C 8
2/D 48 4/D 79
2/E 41 4/E 76
2/F 50 4/F 77
2/G 45 4/G 75
2/DOT 50 4/DOT 11
Table 2-4. Connections of ATF15xx 100-pin TQFP to 7-segment Displays
DSP/Segment PLD Pin # DSP/Segment PLD Pin #
1/A 67 3/A 13
1/B 71 3/B 19
1/C 69 3/C 16
1/D 61 3/D 8
1/E 57 3/E 83
1/F 64 3/F 6
1/G 60 3/G 92
1/DOT 75 3/DOT 20
2/A 52 4/A 100
2/B 54 4/B 94
2/C 47 4/C 97
2/D 41 4/D 81
2/E 46 4/E 76
2/F 40 4/F 80
2/G 45 4/G 79
2/DOT 56 4/DOT 93
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-5
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2.1.2 LEDs with Selectable Jumpers
Atmel CPLD Development/Programmer Board has eight individual LEDs, which allowdesigners to display the output signals from the user I/Os of the ATF15xx CPLD. Theseeight LEDs are labeled LED1 to LED8 on the Atmel CPLD Development/ProgrammerBoard. The cathode of each LED is connected to ground through a series resistor whilethe anode of each LED is connected to a user I/O pin of the CPLD through theJPL1/JPL2/PL3/JPL4/JPL5/JPL6/JPL7/JPL8 selectable jumper. These jumpers can beremoved to disable the LEDs by unconnecting the anodes of the LEDs to the I/O pins ofthe CPLD. Figure 2-3 shows the circuit diagram of the LEDs with the selection jumpers.
To turn on a particular LED, the corresponding ATF15xx I/O pin connected to the LEDmust be in a logic high state with the corresponding jumper set. Hence, the outputs ofthe ATF15xx need to be configured as active-high outputs in the design files. TheseLEDs work best at 2.5V VCCIO or higher.
The lower pin-count devices (44-pin) only have four I/Os connected to LED1, LED2,LED3, and LED4. For the higher pin-count devices (100-pin and larger), all eight LEDsare connected to the I/Os of the device. Tables 2-5, 2-6, 2-7, and 2-8 show the connec-tions of the CPLD I/Os to the LEDs in the different package types.
Figure 2-3. Circuit Diagram of the LEDs and Jumpers
Table 2-5. Connections of ATF15xx 44-pin TQFP to LEDs
LED # PLD Pin #
LED1 28
LED2 25
LED3 22
LED4 19
Table 2-6. Connections of ATF15xx 44-pin PLCC to LEDs
LED # PLD Pin #
LED1 34
LED2 31
LED3 28
LED4 25
Hardware Description
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2.1.3 Push-button Switches with Selectable Jumpers for I/O Pins
Atmel CPLD Development/Programmer Board contains eight push-button switches,which are connected to the I/O pins of the CPLD. They allow designers to send inputlogic signals to the user I/O pins of the ATF15xx CPLD. These eight switches arelabeled SW1 to SW8 on the Atmel CPLD Development/Programmer Board. One end ofeach input push-button switch is connected to VCCIO while the other end of each push-button switch is connected to a pull-down resistor and then connected to the specific I/Opin of the CPLD through the JPS1/JPS2/JPS3/JPS4/JPS5/JPS6/JPS7/JPS8 selectablejumper.
If any one of these switches is pressed and the corresponding jumper is set, the specificI/O pin of the device will be driven to a logic high state by the output of switch circuit.Since each push-button switch is also connected to a pull-down resistor, the input willhave a logic low state if the switch is not pressed with the corresponding jumper set. Ifthe push-button jumper is not set, the corresponding pin will be treated as an uncon-nected pin. Figure 2-4 on page 2-7 is a circuit diagram of the push-button switch andselectable jumper. Tables 2-9, 2-10, 2-11, and 2-12 show the connections of these eightpush-button switches to the CPLD I/O pins in the different package types.
Table 2-7. Connections of ATF15xx 84-pin PLCC to LEDs
LED # PLD Pin #
LED1 69
LED2 67
LED3 64
LED4 60
LED5 27
LED6 24
LED7 18
LED8 15
Table 2-8. Connections of ATF15xx 100-pin TQFP to LEDs
LED # PLD Pin #
LED1 68
LED2 65
LED3 63
LED4 58
LED5 17
LED6 14
LED7 10
LED8 9
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-7
3605B–PLD–05/06
Figure 2-4. Circuit Diagram of the Push-button Switches and Jumpers for the I/O Pins
Table 2-9. Connections of ATF15xx 44-pin TQFP to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 15
SW2 14
SW3 13
SW4 12
SW5 8
SW6 5
SW7 2
SW8 44
Table 2-10. Connections of ATF15xx 44-pin PLCC to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 21
SW2 20
SW3 19
SW4 18
SW5 14
SW6 11
SW7 8
SW8 6
Hardware Description
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2.1.4 Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins
Atmel CPLD Development/Programmer Board also contains two push-button switchesfor the Global Clear (GCLR) and Output Enable (OE1) pins of the CPLD. They allow thedesigners to control the logic states of the OE1 and GCLR inputs of the ATF15xx CPLD.These two switches are labeled SW-GCLR and SW-GOE1 on the Atmel CPLD Develop-ment/Programmer Board. One end of the SW-GCLR input push-button switch isconnected to ground (GND). The other end of the push-button switch is connected to apull-up resistor to VCCIO, and then connected to the GCLR dedicated input pin of theATF15xx. It is intended to be used as an active-low reset signal to reset the registers inthe ATF15xx with the JPGCLR selectable jumper set. Similarly, one end of the SW-GOE1 input push-button switch is connected to ground (GND). The other end of thepush-button switch is connected to a pull-up resistor to VCCIO, and then connected tothe OE1 dedicated input pin of the ATF15xx. It is intended to be used as an active-lowoutput enable signal to control the enabling/disabling of the tri-state output buffers in theATF15xx with the JPGOE selectable jumper set. Figure 2-5 on page 2-9 is the circuitdiagram of these two push-button switches and the jumpers for the GCLR and OE1pins.
If any of these push-button switches is pressed and the corresponding jumper is set,then the specific I/O of the CPLD will be driven to a logic low state. Since each push-button is also connected to a pull-up resistor, the corresponding CPLD input will have alogic high state if the push-button switch is not pressed with the corresponding select-able jumper set. If the selectable jumper is not set, the corresponding dedicated inputpin of the CPLD can be considered a “no connect” (NC) pin. Table 2-13 on page 2-9
Table 2-11. Connections of ATF15xx 84-pin PLCC to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 54
SW2 51
SW3 49
SW4 44
SW5 9
SW6 6
SW7 4
SW8 80
Table 2-12. Connections of ATF15xx 100-pin TQFP to the Switches for I/O Pins
Push Button # PLD Pin #
SW1 48
SW2 36
SW3 44
SW4 37
SW5 96
SW6 98
SW7 84
SW8 99
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-9
3605B–PLD–05/06
shows the pin numbers of the GCLR and OE1 dedicated input pins of the ATF15xx in allthe different available package types.
Figure 2-5. Circuit Diagram of Push-button Switches and Selectable Jumpers forGCLR and OE1
2.1.5 2 MHz Oscillator and Clock Selection Jumper
The Clock Selection Jumper, labeled JP-GCLK, on the CPLD Development/Program-mer Board is a two-position jumper that allows the users to select which GCLKdedicated input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected tothe output of the 2 MHz oscillator. In addition, the jumper can be removed to allow anexternal clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx. Figure2-6 is the circuit diagram of the oscillator and selection jumper. Table 2-14 on page 2-10shows the pin numbers for the GCLK1 and GCLK2 dedicated input pins of the ATF15xxin all the different available package types.
Note: If GCLK1 jumper is set, the jumper will be located toward the side of the board. On the other hand, if GCLK2 jumper is set, the jumper will be located toward the middle of the board.
Figure 2-6. Circuit Diagram of Oscillator and Clock Selection Jumper
Table 2-13. Pin Numbers of GCLR and OE1
44-pinTQFP
44-pinPLCC
84-pinPLCC
100-pinTQFP
GCLR 39 1 1 89
OE1 38 44 84 88
Hardware Description
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2.1.6 VCCIO and VCCINT Voltage Selection Jumpers and LEDs
The VCCIO and VCCINT Voltage Selection Jumpers, labeled VCCIO Selector andVCCINT Selector respectively on ATF15xx-DK3 Development/Programming Board,allow the designers to select I/O supply voltage level (VCCIO) and core supply voltagelevel (VCCINT) that are used for the target CPLD on the board. Once these jumpers areset correctly, the LEDs (labeled VCCINT LED and VCCIO LED) will be turn on asexpected. However, at lower supply voltage levels (i.e. 2.5V or lower), the LEDs mightbe very dim.
For ATF15xxAS/ASL (5.0V) CPLDs, both the VCCIO Selector and VCCINT Selectorjumpers MUST BE set to 5.0V. For ATF15xxASV/ASVL (3.3V) CPLDs, both the VCCIOSelector and VCCINT Selector Jumpers MUST BE set to 3.3V only. For the ATF15xxBE(1.8V) CPLDs, designers MUST SET VCCINT Selector jumper to 1.8V for its core volt-age supply. However, designers can set the VCCIO Selector jumper to 3.3V, 2.5V, or1.8V (but not 5.0V) in order for the I/Os of the ATF15xxBE CPLD to interface with differ-ent voltage levels devices.
Note: The power of the CPLD Development/Programmer Board MUST BE turned OFF when changing the position of the VCCIO or VCCINT voltage selection jumper (VCCIO Selector or VCCINT Selector).
2.1.7 ICCIO and ICCINT Jumpers
The IccIO and IccINT jumpers can be removed and used as Icc measurement points.When the jumpers are removed, current meters can be connected to the posts to mea-sure the current consumption of the target CPLD. When users are not using thesejumpers to measure the current, these jumpers must be set in order for the board andCPLD to operate.
2.1.8 Voltage Regulators Two voltage regulators, labeled VR1 and VR2, are used to independently generate andregulate the VCCINT and VCCIO voltages from the 9V DC power supply. For details,please review the schematic of the ATF15xx-DK3 board.
2.1.9 Power Supply Switch and Power LED
The Power Supply Switch, labeled POWER SWITCH, can be switched to the ON orOFF position, which is used to turn on or off the power of the ATF15xx-DK3 boardrespectively. It allows the 9V DC voltage at the Power Supply Jack to pass to the volt-age regulators when it is in the ON position. When the Power Supply Switch is turnedON, the Power LED (labeled POWER LED) will light up to indicate that the ATF15xx-DK3 board is supplied with power.
2.1.10 Power Supply Jack and Power Supply Header
The Atmel ATF15xx-DK3 Development/Programmer Board contains two different typesof power supply connectors labeled JPower and JP Power. Either one of these powersupply connectors can be used to connect a 9V DC power source to the board. The firstpower connector, labeled JPower, is a barrel power jack with a 2.1mm diameter postand it mates to a 2.1mm (inner diameter) x 5.5mm (outer diameter) female plug. Thesecond is the power supply header, labeled JP Power, is a 4-pin male 0.1" header with0.025" square posts. The availability of these two types of power connectors allows theusers to choose the type of power supply equipment to use for ATF15xx-DK3 Develop-ment/Programmer Board. However, please note that only one of these two powersupply connectors should be powered with a 9V DC source but not both at the sametime.
Table 2-14. Pin Numbers of GCLK1 and GCLK2
44-pinTQFP
44-pinPLCC
84-pinPLCC
100-pinTQFP
GCLK1 37 43 83 87
GCLK2 40 2 2 90
Hardware Description
ATF15xx-DK3 Development Kit User Guide 2-11
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2.1.11 JTAG ISP Connector and TDO Selection Jumper
The JTAG ISP Connector, labeled JTAG-IN, is used to connect the ATF15xx’s JTAGport pins (TCK, TDI, TMS and TDO) through the ISP download cable to the parallelprinter (LPT) port of a PC for JTAG ISP programming of the ATF15xx. Polarized con-nectors are used on the ATF15xx-DK3 and ISP Download Cable (ATDH1150VPC) Rev6.0 or later to minimize connection problems. The PIN1 label at the bottom of the JTAGISP connector indicates the pin 1 position of the 10-pin header and further reduces thechance of connecting the ISP Download Cable incorrectly.
To the left of the JTAG-IN connector, there are two columns of vias and they are labeledJTAG-OUT. They are intended to allow the users to create a JTAG daisy chain to per-form JTAG operations to multiple devices. Users will need to solder the same type ofconnector as the one used for JTAG-IN into the JTAG-OUT position in order to utilizethis available feature.
To create a JTAG daisy chain using multiple ATF15xx-DK3 boards, the TDO SelectionJumper, labeled JP-TDO, must be set to the appropriate position. For all the devices inthe daisy chain except the last device, this jumper must be set to the “TO NEXTDEVICE” position. For the last device in the chain, this jumper must be set to the “TOISP CABLE” position. When this jumper is in the “TO NEXT DEVICE” position, the TDOof that particular JTAG device will be connected to the TDI of the next JTAG device inthe chain. When this jumper is in the “TO ISP CABLE” position, the TDO of that devicewill be connected to the TDO of the JTAG 10-pin connector, which will allow the TDOsignal of the that device in the chain to be transmitted back to the host PC with the ISPsoftware. Figure 2-7 below is a circuit diagram of the JTAG connectors and the JP-TDOjumper. Table 2-15 on page 2-12 lists the pin numbers of the four JTAG pins for theATF15xx in all the available packages.
For a single device setup, the position of the JP-TDO jumper must be set to “TO ISPCABLE”.
Figure 2-7. Circuit Diagram of the JTAG ISP Connectors and TDO Jumper
Hardware Description
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The ISP algorithm is controlled by the ATMISP software, which is running on the PC.The four JTAG signals are generated by the LPT port and they are buffered by the ISPdownload cable before going into the ATF15xx on the CPLD Development/ProgrammerBoard. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Pro-grammer Board is shown in Figure 2-8 and the dimensions of this 10-pin male JTAGheader are shown in Figure 2-9.
Figure 2-8. Pinout Diagram of 10-pin JTAG Port Header (Top-view)
Figure 2-9. 10-pin Male Header Dimensions
The pinout of this 10-pin JTAG Port Header is compatible with the Altera® ByteBlaster,ByteBlasterMV, and ByteBlaster II cables. In addition, the ATMISP software allowsusers to choose either the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlast-erMV/ByteBlaster II cable to implement ISP.
2.2 Socket Adapter Board
Atmel ATF15xx-DK3 CPLD Development/Programmer Socket Adapter Boards(ATF15xx-DK3-XXXXX) are circuit boards that interface with the Atmel ATF15xx-DK3CPLD Development/Programmer Board. They are used in conjunction with theATF15xx-DK3 CPLD Development/Programmer Board to evaluate/program AtmelATF15xx ISP CPLDs with different package types. At press time, there are four SocketAdapter Boards available for the ATF15xx-DK3 covering the 44-TQFP, 44-PLCC, 84-
Table 2-15. Pin Numbers of JTAG Port Signals
44-pinTQFP
44-pinPLCC
84-pinPLCC
100-pinTQFP
TDI 1 7 14 4
TDO 32 38 71 73
TMS 7 13 23 15
TCK 26 32 62 62
10
8 7
6
3
2 1
5
GND TDI
NC NC
NCTDOVCC
TMS
GND TCK
9
4
0.100 0.025 Sq.
0.235
Top View Side View
0.100
All dimensions are in inches
Hardware Description
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PLCC, and 100-TQFP package types in the ATF15xx family of CPLDs. Socket Adapterboards for other packages will become available in the near future.
Each socket adapter board contains a socket for the Atmel ATF15xx device and withmale headers on the bottom side, labeled JP1 and JP2. The headers on the bottom sidemate with the female headers on the ATF15xx-DK3 board, labeled JP4 and JP3. Thefour 7-segment displays, push-button switches, JTAG port signals, oscillator, VCCINT,VCCIO, and GND on the CPLD Development/Programmer Board are connected to theATF15xx device on the Socket Adapter Board through these two sets of connectors.
On the top of the 44-TQFP socket adapter, there are four 10-pin connectors with thesame dimensions as the JTAG ISP connector. The pins of these four connectors areconnected to the input and I/O pins (except the four JTAG pins) of the target CPLDdevice. They can be used to connect to an oscilloscope or logic analyzer to capture theactivities of the input and I/O pins of the CPLD. They also can be used to connect theinput and I/O pins of the CPLD to other external boards or devices for system level eval-uation or testing.
2.3 Atmel CPLD ISP Download Cable
The Atmel CPLD ISP Download Cable (P/N: ATDH1150VPC) connects the parallelprinter (LPT) port of your PC to the 10-pin JTAG header on the Atmel CPLD Develop-ment/Programmer Board or a custom circuit board. This is shown in Figure 2-10 onpage 2-14. This ISP cable acts as a buffer to buffer the JTAG signals between the PC’sLPT port and the ATF15xx on the circuit board. The Power-On LED on the back of the25-pin male connector housing indicates that the cable is connected properly. Makesure this LED is turned on before using the Atmel CPLD ISP Software (ATMISP).
This ISP cable consists of a 25-pin (DB25) male connector, which is connected to theLPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header onthe ISP circuit board. The red color stripe on the ribbon cable indicates the orientation ofPin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Pro-grammer Board is polarized to prevent users from inserting the female plug in the wrongorientation.
The Atmel CPLD Development/Programmer kits includes an Atmel ISP cable; however,other supported ISP cables can also be used. The use of the ISP cable on Atmel devel-opment kit is depending on the device that is selected.
The following shows the appropriate ISP cable that can be used for the different voltagefamilies of Atmel CPLDs.
1. Atmel-ISP Cable (Rev 4.0 or earlier) can be used for ATF15xxAS/ASL (5.0V) device only.
2. Atmel-ISP Cable (Rev 5.0) can be used for ATF15xxAS/ASL (5.0V) or ATF15xxASV/ASVL (3.3V) device only.
3. Atmel-ISP Cable (Rev 6.0), also known as the “Atmel CPLD-ISP MV Cable”, can be used for ATF15xxAS/ASL (5.0V) or ATF15xxASV/ASVL (3.3V) or ATF15xxBE (1.8V core) device.
4. ByteBlaster ISP Cable can be used for ATF15xxAS/ASL (5.0V) device only.
5. ByteBlasterMV ISP Cable can be used for ATF15xxAS/ASL (5.0V) or ATF15xxASV/ASVL (3.3V) device only.
6. ByteBlaster II ISP Cable can be used for ATF15xxAS/ASL (5.0V) or ATF15xxASV/ASVL (3.3V) or ATF15xxBE (1.8V core) device.
Hardware Description
2-14 ATF15xx-DK3 Development Kit User Guide
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Figure 2-10. Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board
Figure 2-11 shows the pinout for the 10-pin female header on the Atmel ISP cable. Thepinout on the 10-pin male header on the PC board (if used for ISP) must match thispinout.
Figure 2-11. Atmel ISP Download Cable 10-pin Female Header Pinout
Note: Your circuit board must supply Vcc and GND to the Atmel CPLD ISP Cable through the 10-pin male header. When programming ATF15xxBE device, VCCIO must be used for the ISP Cable.
ISP
DOWNLOAD
CABLE
Pin 1
LED
Color Stripe
1 3 5 7 9
2 4 6 8 10
1 3 5 7 9
2 4 6 8 10
Color Stripe
ATF15xx-DK3 Development Kit User Guide 3-1
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Section 3
CPLD Design Flow Tutorial
This tutorial will guide you through a complete VHDL design cycle for the AtmelATF15xx CPLD. It provides step-by-step procedure to go through each phase of thedesign cycle from design entry, logic synthesis, device fitting, in-system programming,and finally verifying the design on the Atmel ATF15xx-DK3 CPLD Development/Pro-gramming Board.
Note: To complete this tutorial, ProChip Designer V4.0 with Level 2 Update and Atmel-ISP Software (ATMISP) V6.1 are required.
3.1 Create a Project using the “New Project Wizard”
Before starting the design process, a Project File must be created within ProChipDesigner. ProChip Designer’s New Project Wizard provides a very easy way to create anew project file.
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1. Click on the Start > Programs > ProChip icon to launch ProChip Designer. Or double-click on the ProChip icon on the desktop.
2. Click on Project > New or double-click on the New Project shortcut button to launch the New Project Wizard.
3. Click on the Next button to start the project file creation process.
4. Click on the Browse button to open the browser window.
(1) Click to launch ProChip Designer
(2) Click to create new project
(3) Click Next to start
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5. Use C:\PROCHIP\DESIGNS\VHDL as the directory of the project.
6. Enter DEV_KIT.APJ as the project filename. The extension of a project file must be .APJ.
Note: The name and directory of the design project is specified in this window. All design, simulation, and other project files must be placed in this project direc-tory.
7. Choose ATF1502BE-7AU44 as the target device type for the project. Also review the filters that allow for selection of a specific speed grade or package type.
(4) Click to Browse
(5) Select the project directory
(6) Enter the project filename
(7) Select the device type
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8. Select VHDL - Mentor Graphics as the software tool for this design flow.
ProChip Designer V4.0 with software patch level 1 and later version supports the follow-ing design flows:
9. Select Done with parts so that there will be only one device in this project.
Design Flow Design Flow Type
CUPL – Altium CUPL design compiled through Altium Protel 99SE
Verilog – Mentor Graphics Verilog design synthesized through Mentor Graphics Precision
VHDL – Altium VHDL design synthesized through the Altium PeakFPGA
VHDL – Mentor Graphics VHDL design synthesized through Mentor Graphics Precision
Schematic – Altium Schematic design compiled through Altium Protel 99SE
(8) Select the design flow
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On the other hand, users can select Add more parts to include more parts to the cur-rent project directory.
10. Click the Finish button to finish the New Project Wizard and the project creation process.
This closes the New Project Wizard and opens the ProChip Designer window. Thesources in the project are shown in the left window.
(9) Select Done with parts
(10) Select Finish to end the New Project Wizard
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11. Click on the ATF1502BE-7AU44 device icon to view the Design Flow window.
(11) Click on the device iconMessage window
Project Sources window Information dialog box
Project File window Design Flow window
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3.2 Add a Design File
Once the project file is created, the next step is to add the design source file(s) into yourproject. For this tutorial, a single VHDL design file will be added into the project.
1. Click on the Add/Edit button from Source Manager to open the Source Manager window. You can view the Source Manager help file by clicking on the Help but-ton within the Source Manager window to view the description for the different processes.
2. In the Source Manager window, click on the Add button to add a VHDL design file to the project.
3. In the File Manager window, select .VHD from the C:\PRO-CHIP\DESIGNS\VHDL directory as the source design file for this project.
This VHDL design is available at the end of this document.
The F02_44TQFP.VHD file is a VHDL design that uses two 7-segment displays and thebuilt-in oscillator on the Atmel ATF15xx-DK3 CPLD Development/Programmer Board togenerate two scrolling “0” characters. This design will also pass the states of the I/Opush-button switches (SW1-SW4) to the LEDs at LED1-LED4 on the ATF15xx-DK3CPLD Development/Programmer Board. For details, please review the VHDL code.
3.3 Synthesize the VHDL Design
In this part of the tutorial, the VHDL design code will be synthesized through the MentorGraphics Precision Synthesis process into an EDIF netlist (*.EDF), which contains a setof optimized/minimized logic equations for the specified CPLD.
(1) Click Add/Edit to open Source Manager window
(2) Select VHDL source file
(3) Click Add to add design file
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1. Click on the VHDL - Precision button in the Design Flow window to open the Logic Synthesis window.
2. In the Logic Synthesis window, check both options to Update Pin Assignments after each Compilation and also Run Precision in shell mode:
3. Click on the Compile button to start the compile process. Close the log file when the synthesis is done successfully.
Note: If you have encountered any syntax error during synthesis, the report file will pop up to indicate which line of the code contains problem. In such case, you must correct the syntax problem and save the file before synthesize the code again before proceeding to the next step.
3.4 Fit the Synthesized Design File
In Section 3.3, the logic synthesis portion of the CPLD design flow was completed. Onsuccessful compilation, the Precision tool will produce an EDIF output file (with .EDFextension). An EDIF file contains the netlist of the optimized and minimized logic equa-tions. We now need to map this netlist into a specific Atmel CPLD architecture using theAtmel Fitter.
(1) Open the Logic Synthesis window
(2) Check both options here
CPLD Design Flow Tutorial
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1. You can now proceed to the device fitter portion of the design flow by clicking on the Atmel Fitter button.
You can either use the default options or specify fitter properties. ProChip Designer willautomatically select the EDIF file (*.EDF) associated to the current design project andthe tool type. In this example, since our target device is an ATF1502BE, we will selectthe FIT1502.EXE device fitter.
The fitter creates the important JEDEC and Fit Report output files. They contain the datafor programming the device (using in-system programming or on a third-party deviceprogrammer) and the pin assignments required for board layout respectively.
Please review the Global Device Parameters and Pin/Node Options as well. The helpfiles also show the Device Pin_Node lists for each of the Atmel CPLDs.
2. Make sure the JTAG box is checked. This enables the JTAG port for ISP programming.
3. Make sure the Pin Fit Control setting is set to Keep. This will ensure that the pin assignments in the PLD file will be kept during the place-and-route process.
4. Make sure the Logic Double setting is set to if necessary.
5. When all the fitter options are set, click on the Run Fitter button to fit the design.
(1) Open the Atmel Fitter window
(2) Check the JTAG box
(3) Set the Pin Fit Control setting to Keep
(4) Set Logic Double to if necessary
(5) Start the fitting process
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The above message will be displayed after the design is successfully fit the selecteddevice.
If there are any error messages, you can review the exported *.FIT file or you can copyyour *.EDF file to the C:\PROCHIP\PLDFIT\ directory, open the DOS command prompt,and then type the fit command that is starting from the second line of the *.FIT file to seemore details about the fitter errors.
Parts of the fitter report (.FIT) file generated for this design is shown below.
Total dedicated input used: 3/4 (75%)
Total I/O pins used 24/32 (75%)
Total Macro cells used 35/32 (109%)
Total Flip-Flop used 28/32 (87%)
Total Foldback logic used 15/32 (46%)
Total Nodes+FB/MCells 50/32 (156%)
Total cascade used 0
Total input pins 10
Total output pins 17
Total Pts 93
Creating pla file c:\Prochip\designs\vhdl\f02_44TQFP.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...
---------------- End fitter, Design FITS
$Device TQFP44 fits
FIT1502 completed in 0.00 seconds
3.5 Program and Verify Design
In this step of the tutorial, you will program an ATF1502BE 44-pin TQFP device on theAtmel ATF15xx-DK3 CPLD Development/Programmer Board through ISP. Then you willbe able to verify the design by observing the four 7-segment displays and four LEDs onthe CPLD Development/Programmer Board.
You will need to follow the steps below to setup the ATMISP software (V6.0 or latestversion) in order to program the ATF1502BE 44-pin TQFP on the ATF15xx-DK3 CPLDDevelopment/Programmer Board.
CPLD Design Flow Tutorial
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1. To create a new chain file, the ATMISP Software first needs to be launched either through the Program Chip button in the ProChip Designer window, the ATMISP desktop icon or the Start > Programs > Atmel-ISP menu.
Note: If ATMISP is launched through ProChip Designer, then the appropriate chain (.CHN) file will be automatically created by ProChip Designer. Therefore, steps 2 through 6 can be skipped.
2. To create a new chain file, select the New command under the File menu or click on the New shortcut button.
3. The first piece of information that the software asks for when creating a new chain is the number of devices in the JTAG chain. Therefore, enter “1” and then click OK since you will be programming a single-device JTAG chain.
4. Next you will need to specify the properties of each JTAG device in the Device Properties window. First, you will need to select the target device type of the first device in the JTAG chain. For this tutorial, please select ATF1502BE as the tar-get device type.
5. In the JTAG Instruction field, you can specify which JTAG instruction to be exe-cuted on this device in the chain. Please select Program/Verify to program and verify the ATF1502BE.
6. The next step is to specify the JEDEC file to be programmed into the target device in the JEDEC File field. Click on the Browse button, change the directory to ..\PROCHIP\DESIGNS\VHDL and then select F02_44TQFP.JED as the
(1) Launch ATMISP
(2) Create new chain file
(3) Enter the number of devices
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JEDEC file. Click OK to close the JTAG Device Properties window when all prop-erties are specified.
The next step requires you to setup the Atmel ATF15xx-DK3 CPLD Development/Pro-grammer Board to program the ATF1502BE-7AU44 through the CPLD ISP cable.
7. Connect the DB25 side of the Atmel CPLD ISP MV cable (Revision 6) to the PC’s parallel port and the 10-pin header side of the cable to the Atmel ATF15xx-DK3 CPLD Development Board as shown Figure 2-10 on page 2-14.
8. Connect a 9V AC/DC power supply to the power connector (JPower) of the Atmel ATF15xx-DK3 CPLD Development/Programmer Board.
9. Set the VCCIO Selector jumper to the 1.8V(BE) position for supplying the core voltage of the ATF1502BE device at 1.8V, then set the VCCINT Selector jumper to the 1.8V(BE) position for supplying the I/O pad voltage of the ATF1502BE device at 1.8V.
Note: Make sure the ICCINT and ICCIO jumpers are in their default positions. These two jumpers are only removed when you are connecting them from two poles of the digital multimeter to perform current measurement.
10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will go to pin 37 (GCLK1) of the ATF1502BE. For this design, you can also set the JPCLK jumper to GCLK2 so that the output of the crystal oscillator will go to pin 40 (GCLK2) of the ATF1502BE for selecting another global clock source.
11. Set the JPJTAG Jumper ISP Cable position, which is toward the middle of the board.
12. Connect the 44-pin TQFP Socket Adapter Board onto the main develop-ment/programmer board.
Note: If a device in a different package type is to be programmed, then the appropri-ate Socket Adapter Board must be used.
13. Select which LPT port is being used for Atmel CPLD ISP cable in the Port Setting field. LPT1 is the default port and it represents address 0x378.
14. Select the ISP download cable type in the Cable Type field. The default cable type is the “Atmel CPLD-ISP MV”, which represents the Atmel CPLD ISP Cable Rev 6.0, but it can be changed to other cables that can be used for other devices.
Note: The “Atmel CPLD-ISP” cable type represents the Atmel CPLD ISP Cable Rev 5.0 or older.
15. Switch the power switch to the ON position.
(4) Specify target device type
(5) Specify JTAG instruction
(6) Select JEDEC file
CPLD Design Flow Tutorial
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Now both your software and hardware are setup for ISP programming and you can exe-cute the Program/Verify instruction to program the ATF1502BE on the Atmel ATF15xx-DK3 CPLD Development/Programmer Board.
16. Click on the Run button in the ATMISP main window to execute the JTAG instruction to program the ATF1502BE on ATF15xx-DK3 CPLD Develop-ment/Programmer Board.
If you do not see above message after programming of the device, please review thetroubleshooting guide and FAQs from the Atmel-ISP software to debug the problem.
After successfully programming the ATF1502BE with the F02_144TQFP.JED file, thefirst and fourth 7-segment LED displays should show two rotating “0” characters. Inaddition, with the setting of the LED jumpers (JPL1, JPL2, JPL3, and JPL4) and push-button jumpers (JPS8, JPS7, JPS6, and JPS5), you can press SW8, SW7, SW6, orSW5 to light up LEDs 1-4.
If the result is displayed correctly on the ATF15xx-DK3 CPLD Development/Program-mer Board, then you have successfully completed this tutorial.
(13) Select the LPT port number
(14) Select the cable type
(16) Click on the Run button
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Section 4
Schematic Diagrams and VHDL File
Schematic Diagrams and VHDL File
4-2 ATF15xx-DK3 Development Kit User Guide
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Figure 4-1. ATF15xx-D3 Development/Programmer Board Schematic Diagram
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LED7
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LED3
LED4
LED5
LED6
LED7
LED8
LED
4G
REEN
LED
3G
REEN
LED
2G
REEN
LED
1G
REEN
JPL4
SIP2
JPL3
SIP2
JPL2
SIP2
JPL1
SIP2
RL4
220
RL3
220
RL2
220
RL1
220
R19
1K
SW1 V
CCIO
C13
0.00
1uF
JPS1
SIP2
R21
1K
SW2 V
CCIO
C15
0.00
1uF
JPS2
SIP2
R23
1K
SW3 V
CCIO
C17
0.00
1uF
JPS3
SIP2
R25
1K
SW4 V
CCIO
C19
0.00
1uF
JPS4
SIP2
R20
1K
SW5
VCC
IO
C14
0.00
1uF
JPS5
SIP2
R22
1K
SW6 V
CCIO
C16
0.00
1uF
JPS6
SIP2
R24
1K
SW7 V
CCIO
C18
0.00
1uF
JPS7
SIP2
R26
1K
SW8 V
CCIO
C20
0.00
1uF
JPS8
SIP2
SW1
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW-G
CLR
SW-G
CLR
SW-G
OE
SW-G
OE
VCC
IN
D3 R27
1K
D4 R28
1K
C21
0.1u
F
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP3 1
23
45
67
89
1011
1213
1415
1617
1819
2021
2223
2425
2627
2829
3031
3233
3435
3637
3839
40
JP4
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
R37
2.2K
R38
2.2K
R39
100
R29
4.7K
SW5
R30
4.7K
SW6
R32
4.7K
SW2
R31
4.7K
SW3
R33
4.7K
SW7
R34
4.7K
SW4
R35
4.7K
SW8
R36
4.7K
1234
JP JP P
ower
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-3
3605B–PLD–05/06
Figure 4-2. 44-pin TQFP Socket Adapter Board Schematic Diagram
c1 0.1u
Fc2 0.
1uF
c3 0.1u
Fc4 0.
1uF
VCC
INT
TDI
TMS
VCC
IO
VCCINT
VCC
IO
TDO
TCK
VCCINT
GN
D
GND
GN
D
GND
VCC
IOG
ND
GCL
K1
TCK
VCC
INT
GN
D
GCL
K2
TDO
VCC
IOG
ND
GCL
R
TDI
VCC
INT
GN
D
GO
E
TMS
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
DOT1
DOT2
LED1
LED2
D4A
D4B
D4C
D4D
D4E
D4F
D4G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP1
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
PIN
38PI
N39
PIN
37PI
N40
12
34
56
78
910
JL1
23
45
67
89
10
JR
12
34
56
78
910
JB
12
34
56
78
910
JT ATM
EL T
QFP
44
TDI
1I/O
2I/O
3G
ND
4I/O
5
TMS
7I/O
8V
CC9
I/O10
I/O11
I/O6
I/O 12
I/O 13
I/O 14
I/O 15
GND 16
VCC 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O23
GN
D24
I/O25
TCK
26
I/O27
I/O28
VCC
29
I/O30
I/O31
TDO
32
I/O33
I/O34 GCLK335 GND36 GCLK137 OE138 GCLR39 I/OE2/GCLK240 VCC41 I/O42 I/O43 I/O44
U1
TQFP
44
PIN
2PI
N3
PIN
5PI
N6
PIN
8
PIN
10PI
N11
PIN12PIN13PIN14PIN15
PIN18PIN19PIN20PIN21PIN22
PIN
23
PIN
25
PIN
27PI
N28
PIN
30PI
N31
PIN
33
PIN34PIN35
PIN37PIN38PIN39PIN40
PIN42PIN43PIN44
PIN
34PI
N35
PIN
42PI
N43
PIN
2PI
N3
PIN
5PI
N6
PIN
8PI
N10
PIN
11
PIN
44
PIN
34PI
N35
PIN
37PI
N38
PIN
39PI
N40
PIN
42PI
N43
PIN
44
PIN
2PI
N3
PIN
5PI
N6
PIN
8PI
N10
PIN
11
PIN
12PI
N13
PIN
14PI
N15
PIN
18PI
N19
PIN
20PI
N21
PIN
22
PIN
23PI
N25
PIN
27PI
N28
PIN
30PI
N31
PIN
33
PIN
23PI
N25
PIN
27PI
N28
PIN
30PI
N31
PIN
33
PIN
18PI
N19
PIN
20PI
N21
PIN
22
BIG
ATM
EL
MA
RK
ATM
EL
PIN
12PI
N13
PIN
14PI
N15
VCC
IO
Schematic Diagrams and VHDL File
4-4 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 4-3. 44-pin PLCC Socket Adapter Board Schematic Diagram
ATM
EL P
LCC4
4
TDI
7I/O
8I/O
9G
ND
10I/O
11
TMS
13I/O
14V
CC15
I/O16
I/O17
I/O12
I/O 18
I/O 19
I/O 20
I/O 21
GND 22
VCC 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O29
GN
D30
I/O31
TCK
32
I/O33
I/O34
VCC
35
I/O36
I/O37
TDO
38
I/O39
I/O40 GCLK341 GND42 GCLK143 OE144 GCLR1 I/OE2/GCLK22 VCC3 I/O4 I/O5 I/O6
U1
PLCC
44
PIN1PIN2
VCCINTPIN4PIN5PIN6
TDI
PIN
8PI
N9
GN
DPI
N11
PIN
12TM
SPI
N14
VCC
IO PIN
16PI
N17
PIN18PIN19PIN20PIN21
GNDVCCINT
PIN24PIN25PIN26PIN27PIN28
PIN
29G
ND
PIN
31TC
KPI
N33
PIN
34V
CCIO
PIN
36PI
N37
TDO
PIN
39
PIN40PIN41
GNDPIN43PIN44
VCC
IOG
ND
GCL
K1
TCK
VCC
INT
GN
D
GCL
K2
TDO
VCC
IOG
ND
GCL
R
TDI
VCC
INT
GN
D
GO
E
TMS
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
DOT1
DOT2
LED1
LED2
D4A
D4B
D4C
D4D
D4E
D4F
D4G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP1
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
PIN
44PI
N1
PIN
43PI
N2
PIN
40PI
N41
PIN
4PI
N5
PIN
8PI
N9
PIN
11PI
N12
PIN
14PI
N16
PIN
17
PIN
6PI
N29
PIN
31PI
N33
PIN
34PI
N36
PIN
37PI
N39
PIN
24PI
N25
PIN
26PI
N27
PIN
28 PIN
18PI
N19
PIN
20PI
N21
12
34
56
78
910
JL
12
34
56
78
910
JB
12
34
56
78
910
JR
12
34
56
78
910
JT
PIN
8PI
N9
PIN
11PI
N12
PIN
14PI
N16
PIN
17
PIN
18PI
N19
PIN
20PI
N21
PIN
24PI
N25
PIN
26PI
N27
PIN
28
PIN
29PI
N31
PIN
33PI
N34
PIN
36PI
N37
PIN
39
PIN
40PI
N41
PIN
43PI
N44
PIN
1PI
N2
PIN
4PI
N5
PIN
6
c1 0.1u
Fc2 0.
1uF
c3 0.1u
Fc4 0.
1uF
VCC
INT
VCC
IO
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-5
3605B–PLD–05/06
Figure 4-4. 84-pin PLCC Socket Adapter Board Schematic Diagram
INPUT/GCLRn1 INPUT/OE2/GCLK22 VCC_INT3 I/O4 I/O5 I/O6 GND7 I/O8 I/O9 I/O10 I/O11
I/O12
VCC
_IO
13I/O
/ TD
I14
I/O15
I/O16
I/O17
I/O18
GN
D19
I/O20
I/O21
I/O22
I/O /
TMS
23I/O
24I/O
25V
CC_I
O26
I/O27
I/O28
I/O29
I/O30
I/O31
GN
D32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
VCC_IO 38
I/O 39
I/O 40
I/O 41
GND 42
VCC_INT 43
I/O 44
I/O 45
I/O 46
GND 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
VCC_IO 53
I/O54
I/O55
I/O56
I/O57
I/O58
GN
D59
I/O60
I/O61
I/O /
TCK
62
I/O63
I/O64
I/O65
VCC
_IO
66
I/O67
I/O68
I/O69
I/O70
I/O /
TDO
71
GN
D72
I/O73
I/O74
I/O75 I/O76 I/O77 VCC_IO78 I/O79 I/O80 I/O81 GND82 INPUT/GCLK183 INPUT/OE184
ATM
EL
ATF
1508
AS-
15JC
84
U1
PIN1
GN
D
GN
D
GND
GND
GN
D
GN
D
GND
GNDVCCINT
VCCIO
VCC
IO
VCC
IO
VCC
IO
VCCIO
VCCIO
VCCINTPIN84PIN83
PIN2
TDI
TMS
TDO
TCK
C1 0.1u
FC2 0.
1uF
C3 0.1u
FC5 0.
1uF
VCC
IO
SMA
LLA
TMEL
MA
RK1
PIN4PIN5PIN6
PIN8PIN9PIN10PIN11
PIN
12
PIN
15PI
N16
PIN
17PI
N18
PIN
20PI
N21
PIN
22
PIN
24PI
N25
PIN
27PI
N28
PIN
29PI
N30
PIN
31
PIN33PIN34PIN35PIN36PIN37
PIN39PIN40PIN41
PIN44PIN45PIN46
PIN48PIN49PIN50PIN51PIN52
PIN
54PI
N55
PIN
56PI
N57
PIN
58
PIN
60PI
N61
PIN
63PI
N64
PIN
65
PIN
67PI
N68
PIN
69PI
N70
PIN
73PI
N74
PIN75PIN76PIN77
PIN79PIN80PIN81
PIN
1PI
N84
PIN
83
PIN
2PI
N4
PIN
5PI
N6
PIN
8PI
N9
PIN
10PI
N11
PIN
75PI
N76
PIN
77PI
N79
PIN
80PI
N81
12
34
56
78
910
1112
1314
1516
1718
JP3
JPTO
P
12
34
56
78
910
1112
1314
1516
1718
JP4
JPLE
FT
PIN
12PI
N15
PIN
16PI
N17
PIN
18
PIN
20
PIN
21PI
N22
PIN
24
PIN
25PI
N27
PIN
28PI
N29
PIN
30PI
N31
12
34
56
78
910
1112
1314
1516
1718
JP6
JPBO
TTO
M
PIN
33PI
N34
PIN
35PI
N36
PIN
37PI
N39
PIN
40PI
N41
PIN
44PI
N45
PIN
46PI
N48
PIN
49PI
N50
PIN
51PI
N52
VCC
IOG
ND
GCL
K1
TCK
VCC
INT
GN
D
GCL
K2
TDO
VCC
IOG
ND
GCL
R
TDI
VCC
INT
GN
D
GO
E
TMS
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
DOT1
DOT2
LED1
LED2
D4A
D4B
D4C
D4D
D4E
D4F
D4G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
DOT3
DOT4
LED3
LED4
LED5
LED6
LED7
LED8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP2
IDC4
0
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP1
IDC4
0
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
12
34
56
78
910
1112
1314
1516
1718
JP5
JPBO
TTO
M
PIN
1PI
N2
PIN
83
PIN
84
PIN
5PI
N6
PIN
8PI
N9
PIN
12PI
N15
PIN
18PI
N16
PIN
21PI
N17
PIN
24
PIN
25PI
N22
PIN
29PI
N28
PIN
37PI
N39
PIN
40PI
N41
PIN
44PI
N45
PIN
46PI
N48
PIN
49PI
N50
PIN
51PI
N52
PIN
58PI
N60
PIN
61PI
N63
PIN
64PI
N65
PIN
67PI
N68
PIN
69PI
N70
PIN
73PI
N74
PIN
54PI
N55
PIN
56PI
N57
PIN
58PI
N60
PIN
61PI
N63
PIN
64PI
N65
PIN
67PI
N68
PIN
69PI
N70
PIN
73PI
N74
C7 0.1u
FC8 0.
1uF
C4 0.1u
FC6 0.
1uF
VCC
INT
PIN
11PI
N10
PIN
4PI
N80
PIN
79
PIN
75
PIN
77
PIN
57
PIN
55
PIN
48
PIN
41
PIN
50
PIN
45
PIN
56PI
N54
PIN
51PI
N49
PIN
44PI
N27
PIN
76
Schematic Diagrams and VHDL File
4-6 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
Figure 4-5. 100-pin TQFP Socket Adapter Board Schematic Diagram
I/O
n1
I/O
n2
VC
CIO
3T
DI
4I/
On
5I/
O6
I/O
n7
I/O
8I/
O9
I/O
10G
ND
11I/
O12
I/O
13I/
O14
TM
S15
I/O
16I/
O17
VC
CIO
18I/
O19
I/O
20I/
O21
I/O
n22
I/O
23I/
On
24I/
O25
GND 26
I/On 27
I/On 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
VCCIO 34
I/O 35
I/O 36
I/O 37
GND 38
VCCINT 39
I/O 40
I/O 41
I/O 42
GND 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/On 49
I/On 50VC
CIO
51
I/O
52
I/O
n53
I/O
54
I/O
n55
I/O
56
I/O
57
I/O
58
GN
D59
I/O
60
I/O
61
TC
K62
I/O
63
I/O
64
I/O
65
VC
CIO
66
I/O
67
I/O
68
I/O
69
I/O
n70
I/O
71
I/O
n72
TD
O73
GN
D74
I/O
75
AT
ME
L T
QFP
100
I/O76 I/On77 I/O78 I/On79 I/O80 I/O81 VCCIO82 I/O83 I/O84 I/O GCLK385 GND86 GCLK187 OE188 GCLR89 GCLK290 VCCINT91 I/O92 I/O93 I/O94 GND95 I/O96 I/O97 I/O98 I/O99 I/O100
U1
TQ
FP10
0
PIN
1P
IN2
VC
CIO
TD
I PIN
5P
IN6
PIN
7P
IN8
PIN
9P
IN10
GN
D PIN
12P
IN13
PIN
14T
MS PIN
16P
IN17
VC
CIO
PIN
19P
IN20
PIN
21P
IN22
PIN
23P
IN24
PIN
25
GNDPIN27PIN28PIN29PIN30PIN31PIN32PIN33
VCCIOPIN35PIN36PIN37GND
VCCINTPIN40PIN41PIN42GNDPIN44PIN45PIN46PIN47PIN48PIN49PIN50
VC
CIO
PIN
52P
IN53
PIN
54P
IN55
PIN
56P
IN57
PIN
58GN
DP
IN60
PIN
61TC
KP
IN63
PIN
64P
IN65VC
CIO
PIN
67P
IN68
PIN
69P
IN70
PIN
71P
IN72TD
OG
ND
PIN
75
PIN76PIN77PIN78PIN79PIN80PIN81VCCIOPIN83PIN84PIN85GNDPIN87PIN88PIN89PIN90VCCINTPIN92PIN93PIN94GNDPIN96PIN97PIN98PIN99PIN100
C1
0.1u
FC
20.
1uF
C3
0.1u
FC
40.
1uF
VC
CIO
C5
0.1u
FC
60.
1uF
VC
CIN
T
VC
CIO
GN
D
GC
LK
1
TC
K
VC
CIN
TG
ND
GC
LK
2
TD
O
VC
CIO
GN
D
GC
LR
TD
I
VC
CIN
TG
ND
GO
E
TM
S
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
DO
T1
DO
T2
LE
D1
LE
D2
D4A
D4B
D4C
D4D
D4E
D4F
D4G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
DO
T3
DO
T4
LE
D3
LE
D4
LE
D5
LE
D6
LE
D7
LE
D8
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
JP1
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
PIN
88P
IN89
PIN
87P
IN90
PIN
76P
IN79
PIN
80P
IN81
PIN
84
PIN
92P
IN93
PIN
94P
IN96
PIN
97P
IN98
PIN
83
PIN
64P
IN65
PIN
67P
IN68
PIN
69P
IN71
PIN
75
PIN
57P
IN58
PIN
60P
IN61
PIN
63 PIN
37P
IN44
PIN
46
PIN
48P
IN9
PIN
10P
IN14
PIN
17
PIN
20
PIN
13
PIN
19P
IN16
PIN
8
PIN
100
PIN
6
PIN
99
PIN
56P
IN47
PIN
52
PIN
45P
IN41
PIN
40P
IN36
PIN
54
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JL HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JT HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JR HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JB HE
AD
ER
11X
2
PIN
1P
IN2
PIN
5
PIN
6
PIN
7
PIN
8
PIN
9
PIN
10P
IN12
PIN
13
PIN
14
PIN
16
PIN
17
PIN
19
PIN
20
PIN
21
PIN
22P
IN23
PIN
24P
IN25
PIN
27P
IN28
PIN
29P
IN30
PIN
31
PIN
32P
IN33
PIN
35P
IN36
PIN
37P
IN40
PIN
41P
IN42
PIN
44P
IN45
PIN
46
PIN
47P
IN48
PIN
49P
IN50
PIN
52P
IN53
PIN
54P
IN55
PIN
56P
IN57
PIN
58P
IN60
PIN
61P
IN63
PIN
64P
IN65
PIN
67P
IN68
PIN
69P
IN70
PIN
71P
IN72
PIN
75
PIN
76P
IN77
PIN
78
PIN
79P
IN80
PIN
81P
IN83
PIN
84P
IN85
PIN
87P
IN88
PIN
89P
IN90
PIN
92P
IN93
PIN
94P
IN96
PIN
97P
IN98
PIN
99P
IN10
0
C7
0.1u
FC
80.
1uF
C9
0.1u
FC
100.
1uF
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-7
3605B–PLD–05/06
------------------------------------------------------------------------------------
-- Library Declaration
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;
------------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------------
entity f02_44TQFP is
port
(
GCLK1 : in std_logic; -- 2MHz clock (positive edge)
GCLK2 : in std_logic; -- 2MHz clock (negative edge)
GCLR : in std_logic; -- Register reset
SW : in std_logic_vector(8 downto 5);-- Switches
DSP1 : inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
DSP4 : inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
LED : out std_logic_vector(4 downto 1)-- LEDs
);
------------------------------------------------------------------------------------
-- Pin Assignment
------------------------------------------------------------------------------------
attribute pinnum: string;
attribute pinnum of GCLK1: signal is"37";
attribute pinnum of GCLK2: signal is"40";
attribute pinnum of GCLR: signal is"39";
attribute pinnum of SW: signal is"12,13,14,15";
attribute pinnum of DSP1: signal is"23,18,21,30,33,27";
attribute pinnum of DSP4: signal is"42,35,43,6,10,3";
attribute pinnum of LED: signal is"19,22,25,28";
end entity f02_44TQFP;
------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------
architecture LOGIC of f02_44TQFP is
------------------------------------------------------------------------------------
-- Internal Signal Declaration
------------------------------------------------------------------------------------
signal CNT1: unsigned(15 downto 0);
signal iCLK : std_logic;
Schematic Diagrams and VHDL File
4-8 ATF15xx-DK3 Development Kit User Guide
3605B–PLD–05/06
begin
iCLK <= GCLK1 or GCLK2;
------------------------------------------------------------------------------------
-- Frequency Divider
------------------------------------------------------------------------------------
FREQ_DIV1 : process (iCLK,GCLR)
begin
if (GCLR = '0') then
CNT1 <= (others => '0');
elsif (rising_edge(iCLK)) then
CNT1 <= CNT1 + 1;
end if;
end process;
------------------------------------------------------------------------------------
-- LED Control
------------------------------------------------------------------------------------
LED_CTL : process (SW)
begin
LED(1) <= SW(5);
LED(2) <= SW(6);
LED(3) <= SW(7);
LED(4) <= SW(8);
end process;
------------------------------------------------------------------------------------
-- DSP Control
------------------------------------------------------------------------------------
DSP_CTL : process (CNT1(15), GCLR)
begin
if (GCLR = '0') then
DSP1 <= (others => '0');
DSP4 <= (others => '0');
elsif rising_edge(CNT1(15)) then
DSP1(0) <= not DSP1(5);
DSP1(1) <= DSP1(0);
DSP1(2) <= DSP1(1);
DSP1(3) <= DSP1(2);
DSP1(4) <= DSP1(3);
DSP1(5) <= DSP1(4);
DSP4(0) <= not DSP4(5);
Schematic Diagrams and VHDL File
ATF15xx-DK3 Development Kit User Guide 4-9
3605B–PLD–05/06
DSP4(1) <= DSP4(0);
DSP4(2) <= DSP4(1);
DSP4(3) <= DSP4(2);
DSP4(4) <= DSP4(3);
DSP4(5) <= DSP4(4);
end if;
end process;
end architecture LOGIC;
3605B–PLD–05/06
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