B.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV ·  ·...

B.Tech – CSE – Sem. 315CS202 – DIGITAL SYSTEM DESIGN

(Regulations 2015)

UNIT -IV

SYNCHRONOUS SEQUENTIAL CIRCUITS

OUTLINE

• FlipFlops SR,D,JK,T

• Analysis of Synchronous Sequential Circuit

• State Reduction and Assignment

• Design-Sequence Detector

• BCD Counter

• Registers-Shift Register

• Analysis

3

Sequential Circuits

Every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require that the system be described in term of sequential logic.

4

Synchronous Clocked Sequential Circuit

A sequential circuit may use many flip-flops to store as many bits as necessary. The outputs can come either from the combinational circuit or from the flip-flops or both.

5

Latches --SR Latch

The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. It has two inputs labeled S for set and R for reset.

6

SR Latch with NAND Gates

7

SR Latch with Control Input

The operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. In Fig. 5-5, it consists of the basic SR latch and two additional NAND gates.

8

D Latch

One way to eliminate the undesirable condition of the indeterminate state in SR latch is to ensure that inputs S and R are never equal to 1 at the same time in Fig 5-5. This is done in the D latch.

9

Graphic Symbols for latches

A latch is designated by a rectangular block with inputs on the left and outputs on the right. One output designates the normal output, and the other designates the complement output.

10

Flip-Flops

The state of a latch or flip-flop is switched by a change in

the control input. This momentary change is called a trigger

and the transition it cause is said to trigger the flip-flop. TheD latch with pulses in its control input is essentially a flip-flopthat is triggered every time the pulse goes to the logic 1level. As long as the pulse input remains in the level, anychanges in the data input will change the output and thestate of the latch.

11

Clock Response in Latch

In Fig (a) a positive level response in the control input allows changes, in the output when the D input changes while the clock pulse stays at logic 1.

12

Clock Response in Flip-Flop

13

Edge-Triggered D Flip-Flop

The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock.

CLK

D 1 1 0 0 1 1 …Y 1 1 0 0 1 1 … Q ? 1 1 0 0 1 ….

14

D-Type Positive-Edge-Triggered Flip-Flop

Another more efficient construction of an edge-triggered Dflip-flop uses three SR latches. Two latches respond to theexternal D(data) and CLK(clock) inputs. The third latchprovides the outputs for the flip-flop.

15

Graphic Symbol for Edge-Triggered D Flip-Flop

16

Other Flip-Flops -JK Flip-Flop

There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output. The JK flip-flop performs all three operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates.

17

JK Flip-Flop

The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. This can be verified by investigating the circuit applied to the D input:

D = J Q` + K` Q

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T Flip-FlopThe T(toggle) flip-flop is a complementing flip-flop and

can be obtained from a JK flip-flop when inputs J and K are tied together.

19

T Flip-Flop

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gates as shown in Fig. (b). The expression for the D input is

D = T Q = TQ` + T`Q

20

Characteristic Equations

D flip-flop Characteristic Equations

Q(t + 1) = D

JK flip-flop Characteristic Equations

T flip-flop Characteristic Equations

Q(t + 1) = JQ` + K`Q

Q(t + 1) = T Q = TQ` + T`Q

21

Direct Inputs

Some flip-flops have asynchronous inputs that are used toforce the flip-flop to a particular state independent of the clock.The input that sets the flip-flop to 1 is called present or directset. The input that clears the flip-flop to 0 is called clear ordirect reset. When power is turned on a digital system, the stateof the flip-flops is unknown. The direct inputs are useful forbringing all flip-flops in the system to a known starting stateprior to the clocked operation.

22

D Flip-Flop with Asynchronous Reset

A positive-edge-triggered D flip-flop with asynchronous reset is shown in Fig(a).

23

D Flip-Flop with Asynchronous Reset

24

Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of obtaining atable or a diagram for the time sequence of inputs, outputs,and internal states. It is also possible to write Booleanexpressions that describe the behavior of the sequentialcircuit. These expressions must include the necessary timesequence, either directly or indirectly.

25

Example of Sequential Circuit

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State Equation

A(t+1) = A(t) x(t) + B(t) x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that specifiesthe condition for a flip-flop state transition. The left side ofthe equation with (t+1) denotes the next state of the flip-flop one clock edge later. The right side of the equation isBoolean expression that specifies the present state andinput conditions that make the next state equal to 1.

Y(t) = (A(t) + B(t)) x(t)`

27

State Equations

The behavior of a clocked sequential circuit can bedescribed algebraically by means of state equations. A stateequation specifies the next state as a function of the presentstate and inputs. Consider the sequential circuit shown in Fig.5-15. It consists of two D flip-flops A and B, an input x andan output y.

28

State Table

The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called transition table).

29

State Diagram

The information available in a state table can be represented graphically in the form of a state diagram. In this type of diagram, a state is represented by a circle, and the transitions between states are indicated by directed lines connecting the circles.

1/0 : means input =1output=0

30

Flip-Flop Input Equations

The part of the combinational circuit that generatesexternal outputs is descirbed algebraically by a set ofBoolean functions called output equations. The part of thecircuit that generates the inputs to flip-flops is describedalgebraically by a set of Boolean functions called flip-flopinput equations. The sequential circuit of Fig. 5-15 consistsof two D flip-flops A and B, an input x, and an output y. Thelogic diagram of the circuit can be expressed algebraicallywith two flip-flop input equations and an output equation:

DA = Ax + BxDB = A`xy = (A + B)x`

31

Analysis with D Flip-Flop

The circuit we want to analyze is described by the input equation DA = A x y

The DA symbol implies a D flip-flop with output A. The x and y variables are the inputs to the circuit. No output equations are given, so the output is implied to come from the output of the flip-flop.

32

Analysis with D Flip-Flop

The binary numbers under Axy are listed from 000 through 111 as shown in Fig. 5-17(b). The next state values are obtained from the state equation A(t+1) = A x y

The state diagram consists of two circles-one for each state as shown in Fig. 5-17(c)

33

Analysis with JK Flip-Flops

34

Analysis with JK Flip-Flop

The circuit can be specified by the flip-flop input equations

JA = B KA = Bx`JB = x` KB = A`x + Ax` = A x

35

Analysis with JK Flip-Flops

A(t + 1) = JA` + K`AB(t + 1) = JB` + K`B

Substituting the values of JA and KA from the input equations, we obtain the state equation for A:

A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax

The state equation provides the bit values for the column under next state of A in the state table. Similarly, the state equation for flip-flop B can be derived from the characteristic equation by substituting the values of JB and KB:

B(t + 1) = x`B` + (A x)`B = B`x` + ABx + A`Bx`

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Analysis with JK Flip-Flops

The state diagram of the sequential circuit is shown in Fig

37

Analysis With T Flip-Flops

Characteristic equationQ(t + 1) = T Q = T`Q + TQ`

00/0 : meansstate is 00output is 0

38

Analysis With T Flip-Flops

Consider the sequential circuit shown in Fig. 5-20. It has two flip-flops A and B, one input x, and one output y. It can be described algebraically by two input equations and an output equation:

TA = BxTB = xy = AB

A(t+1)=(Bx)’A+(Bx)A’=AB’+Ax’+A’Bx

B(t+1)=xB

Use present stateas inputs

39

Synthesis Using T Flip-Flops

State Reduction and Assignment

State Reduction and Assignment (Contd.)

State Reduction and Assignment (Contd.)

State Reduction and Assignment (Contd.)

State Assignment

Stateabcde

Binary000001010011100

Gray Code000001011010110

One-Hot0000100010001000100010000

State Reduction and Assignment (Contd.)

Reduced State Table:Binary State Assignment

State

001

010

011

100

101

Next Statex=0 x=1

000 001

010 011

000 011

100 011

000 011

Outputx=0 x=1

0 0

0 0

0 0

0 1

0 1

State Reduction and Assignment (Contd.)

Reduced State Table:Binary State Assignment

State

001

010

011

100

101

Next Statex=0 x=1

000 001

010 011

000 011

100 011

000 011

Outputx=0 x=1

0 0

0 0

0 0

0 1

0 1

State Reduction and Assignment (Contd.)

Design Procedure

• Develop State Diagram From Specs

• Reduce States

• Assign Binary values to States

• Write Binary-coded State Table

• Choose Flip-Flops

• Derive Input and Output Equations

• Draw the Logic Diagram

Develop State Diagram:Sequence Detector

• Detect 3 or more 1s in sequence (a Moore Model)

D Flip-Flop Input Equations

A(t+1) = DA(A,B,x) = (3,5,7)B(t+1) = DB(A,B,x) = (1,5,7)

y(A,B,x) = (6,7)

StateA B

0 00 00 10 11 01 01 11 1

Next StateA B

0 00 10 01 00 01 10 01 1

Outputy

00000011

Inputx

01010101

Input equations come directly from the next state in D Flip-Flop design

Simplified Boolean Equations

Sequence Detector: D Flip-Flops

Using JK or T Flip-Flops

1. Develop Excitation Table Using Excitation Tables

K

XX10

J

01XX

Q(t+1)

01 0 1

JK Flip-Flop

Q(t)

00 1 1

T

0110

T Flip-Flop

Q(t+1)

01 0 1

Q(t)

00 1 1

State Table: JK Flip-Flop Inputs

B

00110011

A

00001111

PresentState

x

00001111

Input

B

01010110

A

00101110

NextState

KA

01010110

JA

00101110

KB

01010110

JB

00101110

Flip-Flop Inputs

Maps for J and K Input Equations

JK Flip-Flop Sequence Detector

56

Registers and Counter

• The filp-flops are essential component in clocked sequential circuits.

• Circuits that include filp-flops are usually classified by the function they perform. Two such circuits are registers and counters.

• An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information.

UP-DOWN COUNTER

58

BCD Counter

• Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight binary count.

• To derive the circuit of a BCD synchronous counter, it is necessary to go through a sequential circuit design procedure.

59

BCD Counter

State Table for BCD Counter

Present State Next State Output Flip-Flop inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 1 0 0 1 0 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 0 1

0 0 1 1 0 1 0 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 0 1

0 1 0 1 0 1 1 0 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 0 1

0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 0 1

BCD COUNTER

61

BCD Counter

• The flip flop input equations can be simplified by means of maps. The simplified functions are– TQ1=1– TQ2=Q8’Q1

– TQ4=Q2Q1

– TQ8=Q8Q1+Q4Q2Q1

– y=Q8Q1

• The circuit can be easily drawn with four T flip-flops, five AND gates, and one OR gate.

An Example of Counter

63

Registers

• In its broadest definition, a register consists a group of flip-flops and gates that effect their transition.– The flip-flops hold the binary information.

– The gates determine how the information is transferred into the register.

• Counters are a special type of register.

• A counter goes through a predetermined sequence of states.

64

Registers

• Fig 6-1 shows a register constructed with four D-type filpflops.

• “Clock” triggers all flip-folps on the positive edge of each pulse.

• “Clear” is useful for clearing the register to all 0’s prior to its clocked operation.

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Shift Registers

66

Shift Registers

• A register capable of shifting its binary information in one or both direction is called a shift register.

• All flip-flops receive common clock pulses, which activate the shift from one stage to the next.

• The simplest possible shift register is one that uses only flip-flops, as shown in Fig. 6-3.

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