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EPCOS AG A TDK Group Company
Piezo and Protection Devices Business Group Munich, Germany September, 2016
CeraLink™ Capacitors The revolution for fast switching inverters
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 2
Nominal capacitance / rated voltage
Designed for 650V semiconductors
Designed for 900V semiconductors
Designed for 1300V semiconductors
Low Profile series LP (L leads) ESL = 2.5 nH
1µF / 500V 0.5µF / 700V 0.25µF / 900V
Low profile series LP (J leads) ESL = 2.5 nH
1µF / 500V 0,5µF / 700V 0.25µF / 900V
Solder Pin series SP ESL = 3.5 nH
20µF / 500V 10µF / 700V 5µF / 900V
CeraLink™: Device Portfolio
All products shown share the same ceramic material. Different voltage performance is adjusted by internal layer thickness.
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 3
Key benefits • High capacitance density
• Supports further miniaturization of power electronics on the system level
• Low ESL
• Supports fast-switching semiconductors and high switching frequencies
• Low losses at high frequencies and high temperatures
• Low ESR
• High current rating
• High operating temperature (150°C)
• MLSC Design, no metalization cap
CeraLink – The next generation of capacitor technologies
High Temperature
High Frequency
Low Volume
High Reliability
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 4
Where to use CeraLink?
DC-link capacitor or Snubber capacitor For Industry and for Automotive
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 5
VR >400 V
Patented product solution for high DC voltage applications in power electronics based on multilayer components with • Anti-ferroelectric ceramics
¬ Modified Pb La (Zr, Ti) O3
• Copper inner electrodes • High-temperature stable ceramic-
metal interconnects based on sintered silver to realize capacitance values up to 100 µF
A new approach to ceramic power capacitors
Comparison @ 25 °C, 1 kHz, 1 V RMS
Electric field [V/µm]
Die
lect
ric c
onst
ant
LP-L LP-J SP
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 6
Highest current ratings Device under test: CeraLink LP 1 µF, 500 V
0
2
4
6
8
10
12
14
10 30 50 70 90pe
rmis
sibl
e cu
rren
t [Ar
ms]
Frequency [kHz]
heatsink and forced air flowno heatsink and no forced air flow
Measurement performed at +85 °C ambient temperature
Increase by 25%
𝐼𝐼𝐶𝐶,𝑅𝑅𝑅𝑅𝑅𝑅 =1ℎ
2 ∙ 𝜆𝜆𝑡𝑡𝑡 ∙ ∆𝑇𝑇 ∙ 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸
𝑃𝑃𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 = 𝑃𝑃𝑡𝑡𝑡
𝐼𝐼𝐶𝐶 ,𝑅𝑅𝑅𝑅𝑅𝑅2 ∙ 𝐸𝐸𝐸𝐸𝐸𝐸 =
2 ∙ 𝜆𝜆𝑡𝑡𝑡 ∙ ∆𝑇𝑇ℎ2
∙ 𝑉𝑉
CeraLink technology offers key benefits regarding the power losses in a capacitor: Low profile with short thermal path (h) High thermal conductivity (𝜆𝜆𝑡𝑡𝑡) High permissible temperature
increase (∆𝑇𝑇) Low ESR
For CeraLink capacitors, the maximum temperature increase (ΔT) is only limited by the device temperature.
For typical BTO MLCC ceramic capacitors, self-heating (ΔT) is limited to 20 K. Typical permissible current of 1 µF BTO MLCC: 1…2 A RMS.
Perm
issi
ble
curr
ent [
Arm
s]
Heatsink and forced air flow
No heatsink and no forced air flow
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 7
Insulation properties at high temperatures
1
10
100
1.000
10.000
100.000
1.000.000
10.000.000
100.000.000
20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
tau
[Ohm
F]
temperature [°C]
CeraLink
class 2 125°C rated MLCC
film capacitor
aluminum capacitor
Comparison between capacitors of nominal capacitance values and voltage ratings matching to the CeraLink capacitors series.
For CeraLink capacitors, the loss of insulation resistance at high temperatures is much lower than with other capacitors.
A low time constant results in a high leakage current which heats up the device additionally. The risk of irreversible damage or even thermal runaway increases with falling time constant. Therefore CeraLink capacitors are an optimal solution for high temperature applications. For CeraLink high current ratings and a high self-heating due to applied current are permissible.
For CeraLink capacitors the discharging time constant
𝜏𝜏 = 𝐸𝐸𝑖𝑖𝑖𝑖𝑙𝑙 ∙ 𝐶𝐶(𝑇𝑇) remains at high values even at high temperatures.
CeraLink
Class 2 125 °C rated MLCC
Film capacitor
Aluminum capacitor
Temperature [°C]
τ [Ω
F]
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 8
Overcurrent robustness of parallel capacitors
The capacitance characteristic of CeraLink capacitors avoids thermal runaway Higher temperature leads to Lower capacitance Higher impedance Lowest current through
the hottest capacitor
2 CeraLink capacitors connected in parallel were tested at twice the specified ripple current. One capacitor was cooled, the other was uncooled.
12.5 A RMS (@100 kHz, 105 °C ambient temperature) per 1 µF, 500 V capacitor.
105
125
145
165
0 10 20 30 40 50 60 70devi
ce te
mpe
ratu
re
[°C]
time [min]
Cooled capacitor Uncooled capacitor
In = Itot Z / Zn 1/Z = Σn(1/Zn)
Itot
Z4
I4
Z1
I1
Z2
I2
Z3
I3
+ -
Cooled side
Uncooled side
150100500-50
110
100
90
80
70
60
50
40
30
Temperature [°C]
Capa
cita
nce
[%]
CeraLink large signalCeralink small signal
C1
Time [min] Dev
ice
tem
pera
ture
[°C]
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 9
Improved robustness feature
Multilayer serial capacitor design Serial connection of two MLCC geometries
TWO failures must occur in the same layer
of the chip to produce a short circuit
Single localized failures do not immediately cause a short circuit of the device, because the breakdown voltage is >2 times higher than the operating voltage
Additionally, the lead frames of CeraLink capacitors minimize the mechanical stress to the chip and avoid cracks from occuring in the ceramics at all
Arbitrary failure
Crack
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 10
Benefits of the new technology on a system level Device characteristics lead to a low inductive commutation loop Low self inductance (ESL) 2.5 to 4 nH High capacitance density 2 to 5.5 µF/cm³ High thermal robustness allows CeraLink
capacitors to be placed very close to the semiconductor: operation up to +150 °C permissible
System enabled benefits lead to a miniaturization Lower voltage overshoot during
semiconductor switching Faster switching with higher di/dt and dv/dt
values decrease the switching losses ¬ Higher switching frequencies are achievable ¬ Low losses and high thermal robustness of the DC link capacitor allows reduction of cooling
Less ringing at the DC link improves EMI
<<ESL
<<Lσ
0
10
20
30
40
50
60
70
80
90
100
0
100
200
300
400
500
600
0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
Sem
icon
Col
lect
or C
urre
nt in
A
Sem
icon
duct
or S
witc
hing
Vol
tage
in V
Time [ns]
Principle Semiconductor Overshoot
CeraLink
Sem
icon
col
lect
or c
urre
nt [A
]
Sem
icon
sw
itchi
ng v
olta
ge [V
]
Principle semiconductor overshoot
CeraLink™ Capacitors • The revolution for fast switching inverters
© EPCOS AG 2015 A TDK Group Company
CC • 2/15 • 11
New demands on DC link capacitors
CeraLink capacitors represent a major advance in technology • Reduction of DC link capacitor size. • Low-profile design (<10 mm) available. • Support of distributed DC link capacitor topologies with low inductance
components. • High cooling efficiency due to high thermal conductivity . • Support of different connection techniques
¬ SMD, welding, silver sintering, ¬ Through-hole technology, press fit technology, ¬ Screwing.
“Today the package of a motor inverter is mainly driven by the size of the capacitor, the busbars, the terminal box and the filter components.” Plikat, Mertens, Koch, Volkswagen AG, Corporate Research, 2013
www.global.tdk.com • www.epcos.com
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