Ch4.2 Threshold Voltage

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Fundamentals of Modern VLSI Devices 2nd EditionYuan Taur and Tak H.Ning

Ch4.2 Threshold Voltage

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Off-current and Standby Power

(4.12)

(4.13)

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On-current and MOSFET Performance

(4.14) (4.15)

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CMOS Design Considerations

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CMOS Design Considerations

(4.16)

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Trends of Power Supply Voltage and Threshold Voltage

(4.17)

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Trends of Power Supply Voltage and Threshold Voltage

(4.18)

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Effect of Gate Work Function

(4.19)

(4.20)

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Effect of Gate Work Function

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Channel Profile Requirement and Trends

(4.21)

(4.22)

(4.23)

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Integral Solution to Poisson’s Equation

(4.24) (4.25)

(4.26)

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A High-Low Step Profile

(4.27)

(4.28)

(4.29)

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A High-Low Step Profile

(4.30)

(4.31)

(4.32)

(4.33)

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9.3.2 Threshold Voltage

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A High-Low Step Profile

(4.34)

(4.35)

(4.36)

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Generalization to a Gaussian Profile

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Generalization to a Gaussian Profile

(4.37)

(4.38)

(4.39)

(4.40)

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Retrograde (Low-High) Channel Profile

(4.41)

(4.42)

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Extreme Retrograde Profile and Ground-Plance MOSFET

(4.43)

(4.44)

(4.45)

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Extreme Retrograde Profile and Ground-Plance MOSFET

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Extreme Retrograde Profile and Ground-Plance MOSFET

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9.3.2 Threshold Voltage

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Counter-Doped Channel

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Counter-Doped Channel

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Laterally Nonuniform Channel Doping

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9.2 Ion Implantation and Substrate Nonuniformity

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Future Transistors

2010

2015

2020

2025

1971

Com

plex

-ity

≈

Evolu-tionary

Revolu-tionary

2014 Short Course

Greg Yeric

11

Advance Nano Device Lab.

2014 Short Course

Greg Yeric

73

Need to increase current density as the FETs scale

Ge PMOS

III-V NMOS Ge

, In-

GaAs

• m vs. density of states

• Bandgap: BTBT, GIDL

• Oxides• Quantum wells

See Session25

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72 2014 Short Course Greg Yeric

72

2014 Short Course

Greg Yeric

Your Device

IMEC. VLSI 2014 “7nm FinFETs”

Technology 14nm 10nm 7nm 5nmVDD V 0.8 0.7 0.65 0.6Gate Pitch nm 80 64 48 34Metal Pitch nm 64 48 36 25Channel Length

nm 24 20 14 10

EOT + dark space

nm 1.2 1.1 1.1 1.0

Fin pitch nm 48 36 27 19Max. fins per FET

4 4 4 4

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No two identically designed transistors are alike anymore!

Asenov et al, IEDM 2008

VT ~ 1/(WL)1/2

100

The established simulation par-

adigmPhysical gate length 22nm

atomsFailures shift from catastrophic to time-depen-dent variabilityThis needs adaptations in circuit design to account for statistical spread in device parameters

Physical gate length 9nm = 30x30x30

8Challenges of 7nm CMOS Technology

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Deeply-scaled Device operation becomes more

and more affected by Individual defectsIn deeply-downscaled technologies, only a handful of ran-dom defects will be present in each device

72Challenges of 7nm CMOS Technology

Not = 1012 cm-2 NT ~ 10 if device area = 10 x 100 nm2 Number of charged defects will be increasing with operating time

time-dependent variability in addition to time-0 variability

Courtesy of M. Bina, TUWien

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Quantum Effect on Threshold Voltage

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Quantum Effect on Threshold Voltage

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Triangular Potential Approximation for the Subthreshold Region

(4.46)

(4.47)

(4.48)

(4.49)

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Triangular Potential Approximation for the Subthreshold Region

(4.50)

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Threshold-Voltage Shift Due to Quantum Effect

(4.51)

(4.52)

(4.53)

(4.54)

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Quantum Effect on Inversion-Layer Depth

(4.55)

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A Simple First-Order Model

(4.56)

(4.57)

(4.58)

(4.59)

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Discrete Dopant Effects in a Retrograde-Doped Channel

(4.60)