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Chapter 3Gate-Level Minimization
3.1 Introduction
• The purposes of this chapter– To understand the underlying mathematical
description and solution of the problem– To enable you to execute a manual design
of simple circuits– To prepare you for skillful use of modern
design tools– Introduce a HDL that is used by modern
design tools
3.2 The Map Method
• Karnaugh map (K-map)– Pictorial form of a truth table– To present a visual diagram of a function ex
pressed in standard form
Two-variable Map
Example: f(x,y) = m1+m2+m3 = x’y+xy’+xy = x + y
Three-variable Map
Example 3-1
Example 3-2
Example 3-3
Example 3-4
3.3 Four-Variable Map
The Adjacent Squares of Four-Variable Map
• One square: one minterm, a term of four literals
• Two adjacent squares: a term of three literals• Four adjacent squares: a term of two literals• Eight adjacent squares: a term of one literal• Sixteen adjacent squares: 1
Example 3-5
Example 3-6
PI and EPI
• A prime implicant(PI)– a product term obtained by combining the
maximum possible number of adjacent sqaures in the K-map
• An essential PI (EPI)– If a minterm in a square is covered by only
one PI.
Example F(A,B,C,D) =(0,2,3,5,7,8,9,10,13,15)
3.4 Five-Variable Map
Relationship between Squares and Literals
Example 3-7
3.5 Product of Sums Simplification
• Get F’ by 0’s• Apply DeMorgan’s theorem to F’
Example 3-8 Simplify the following Function into SOP
and POSF(A,B,C,D)= (0,1,2,5,8,9,10)
Example 3-8 (con’t)
• F = B’D’+B’C’+A’C’D’• F’ = AB + CD + BD’ F = (AB + CD + BD’)’ = (AB)’(CD)’(BD’)’ = (A’+B’)(C’+D’)(B’+D)
Implementation of Example 3-8
How to express the Table 3-2
How to express the Table 3-2 (con’t)
• F(x,y,z) = ∑ (1,3,4,6)• F(x,y,z) = ∏ (0,2,5,7)
Map for the Function of Table 3-2
• F= x’z+xz’
• F’=xz+x’z’ F=(x’+z’)(x+z)
3.6 Don’t Care Conditions
• A don’t care minterm is a combination of variables whose logical value is not specified.
• The don’t care minterms may be assumed to be either 0 or 1.
• An X is used for representing the don’t care minterm.
Example 3-9
3.7 NAND and NOR Implementation
• The NAND or the NOR gate – Universal gate– Basic gates of used in all IC digital
families
Why is the NAND Gate Universal?
Two Graphic Symbols for NAND Gate
Two-Level Implementation
Example 3-10
Multilevel NAND Circuits
Implementation of F=(AB’+A’B)(C+D’)
Why is the NOR Gate Universal?
Two Graphic Symbols for NOR Gate
3.8 Other Two-Level Implementation
• Wired-AND logic• Wired-OR logic
AND-OR-INVERT
OR-AND-INVERT
Tabular Summary
Example 3-11
3.9 Exclusive-OR Function
• x y = xy’+x’y• (x y)’ =xy+x’y’• x 0 = x x 1 = x’• x x = 0 x x’ = 1• x y’ = x’ y = (x y)’ • A B = B A• (A B) C = A (B C) = A B C
XOR Implementation
Map for a 3-Input Odd function and Even function
3-Input Odd and Even Functions
Map for a 4-Input Odd function and Even function
Even Parity Generator
Even Parity Checker
Logic Diagram of a Parity Generator and Checker
3.10 Hardware Description Language (HDL)
• HDL : a documentation language• Logic simulator: representation of the
structure and the behavior of a digital logic systems through a computer
• Logic synthesis: the process of driving a list of components and their connections from the model of a digital system described in HDL
Two Standard HDLs Supported by IEEE
• VHDL• Verilog HDL : is chosen for this book
Verilog HDL
• module endmodule• // : comment notation• input output• wire• and or not • # time unit• `timescale: compiler directive
HDL Example 3.2
module circuit_with_delay (A,B,C,x,y); input A,B,C output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule
HDL Example 3-3
module simcrct; reg A, B, C; wire x, y; circuit_with_delay (A,B,C,x,y); initial begin A = 1 `b0; B = 1`b0; C=1`b0; #100 A = 1 `b1; B = 1`b1; C=1`b1; #100 $finish end endmodule
User-Defined Primitives
• primitive endprimitive• table endtable• HDL Example 3-5
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