View
8
Download
0
Category
Preview:
Citation preview
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-1
COMBINATIONAL LOGIC
•CHAPTER VI
CHAPTER VI
COMBINATIONAL LOGIC BUILDING BLOCKS
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-2
COMBINAT. LOGICINTRODUCTION
COMBINATIONAL LOGIC
•COMBINATIONAL LOGIC-INTRODUCTION
• Combinational logic
• Output at any time is determined completely by the current input.
• We will later consider circuits where the output is determined by the
input and the current state (memory) of the system.
• In this chapter we will consider some useful building blocks that can be
pieced together and used in larger designs. This will include:
• Multiplexers (selectors) and demultiplexers (distributors)
• Encoders, priority encoders, decoders
• Adders (full and half)
• Parity generators and parity checkers
• Shifters and rotators
• Comparators
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-3
DECODERSBASIC DECODER
COMBINATIONAL LOGIC
•COMBINATIONAL LOGIC-INTRODUCTION
• Standard decoder is an -to- -line decoder, where .
• Example: 3-to-8-line decoder
• All outputs are low except for the one corresponding to the binary
value of the input .
n m m 2n≤
3-to
-8D
ecod
er01234567
20
21
22
A0
A1
A2
D0D1D2D3D4D5D6D7
3-to
-8D
ecod
er
01234567
20
21
22
0
1
1
00000010
Example:Input of 110
Dm
An…A1A0
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-4
DECODERSDECODERS WITH ENABLE
COMBINATIONAL LOGIC
•COMBINATIONAL LOGIC•DECODERS
-BASIC DECODER
• Often, combinational logic building blocks will also have an enable line that
turns on outputs or leaves them off.
3-to
-8D
ecod
er
01234567
20
21
22
A0
A1
A2
D0D1D2D3D4D5D6D7
3-to-8 Decoderwith Enable
Module Enable E
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-5
DECODERSTRUTH TABLES
COMBINATIONAL LOGIC
•COMBINATIONAL LOGIC•DECODERS
-BASIC DECODER-WITH ENABLE
• Truth table for a 3-to-8-line decoder:
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D2D3D4 D1 D0D5D6D7
OutputsInputs
A0A1A2
1
1
1
1
1
1
1
1
E
00000000X X X 0
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-6
DECODERSIMPLEMENTATION
COMBINATIONAL LOGIC
•DECODERS-BASIC DECODER-WITH ENABLE-TRUTH TABLES
• How can a decoder be implemented? Fill in the circuit!
D0
A2A1A0
D1
A2A1A0
D2
A2A1A0
D3
A2A1A0
D4
A2A1A0
D5
A2A1A0
D6
A2A1A0
D7
A2A1A0
A0A1A2
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-7
DECODERSDESIGNING WITH DECODERS
COMBINATIONAL LOGIC
•DECODERS-WITH ENABLE-TRUTH TABLES-IMPLEMENTATION
• Any Boolean function can implemented using a decoder and OR gates by
ORing together the function’s minterms.
0
1
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F2F1
OutputsInputsA0A1A2
3-to
-8D
ecod
er
01234567
20
21
22
A0
A1
A2 F2
F1
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-8
DECODERSDECODER NETWORKS
COMBINATIONAL LOGIC
•DECODERS-TRUTH TABLES-IMPLEMENTATION-DESIGNING W/DECODERS
• We can also use multiple decoders to form a larger decoder.
2-to
-4D
ecod
er
0123
20
21
A0
A1
D0D1D2D3
D4D5D6D7
E
2-to
-4D
ecod
er
0123
20
21
A2
E
3-to-8 Decoder Implementedwith two 2-to-4 Decoders
A2 used with enable inputto control which decoderwill output the 1.
A1 and A0 used to selectwhich output on specificdecoder will output 1.
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-9
ENCODERSBASIC ENCODER
COMBINATIONAL LOGIC
•DECODERS-IMPLEMENTATION-DESIGNING W/DECODERS-DECODER NETWORKS
• Standard binary encoder is an -to- -line encoder, where .
• Example: 8-to-3-line encoder
m n m 2n≤
8-to
-3E
ncod
er
01234567
20
21
22
A0
A1
A2
D0D1D2D3D4D5D6D7
8-to
-3E
ncod
er
01234567
20
21
22
0
0
1
00001000
Example:Input of 00010000E
Ac
Module Enable
Module Active
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-10
ENCODERSENCODER TRUTH TABLE
COMBINATIONAL LOGIC
•DECODERS•ENCODERS
-BASIC ENCODER
• Truth table for an 8-to-3-line encoder:
• Assumed that only one input is 1. What happens if more then one is 1?
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D2D3D4 D1 D0D5D6D7
OutputsInputs
A0A1A2
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-11
ENCODERSDESIGNING WITH ENCODERS
COMBINATIONAL LOGIC
•DECODERS•ENCODERS
-BASIC ENCODER-TRUTH TABLE
• Encoders are useful when the occurrence of one of several disjoint events
needs to be represented by an integer identifying the event.
8-to
-3E
ncod
er
01234567
20
21
22
1
0
0
NNE
E
SES
SW
W
NW
Example: Wind direction encoder
E
1
pp. 253-254 of Ercegovac, Lang and Moreno, “Introduction to Digital Systems”, 1999.
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-12
ENCODERSPRIORITY ENCODERS
COMBINATIONAL LOGIC
•ENCODERS-BASIC ENCODER-TRUTH TABLE-DESIGN W/ ENCODERS
• A priority encoder takes the input of 1 with the highest index and translates
that index to the output.
1
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
0
1
X
X
X
X
X
0
0
0
1
X
X
X
X
0
0
0
0
1
X
X
X
0
0
0
0
0
1
X
X
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D2D3D4 D1 D0D5D6D7
OutputsInputs
A0A1A2
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-13
ENCODERSDESIGN WITH P-ENCODER
COMBINATIONAL LOGIC
•ENCODERS-TRUTH TABLE-DESIGN W/ ENCODERS-PRIORITY ENCODERS
• Priority encoders are useful when inputs have a predefined priority and we
wish to select the input with the highest priority.
2-to
-4P
riorit
y
0123
20
21
Enc
oder
Device A
Device B
Device C
Device D
LowestPriority
HighestPriority
RequestLines
Processor
E
Ac
1
Example: Resolving interrupt requests
pp. 253-256 of Ercegovac, Lang and Moreno, “Introduction to Digital Systems”, 1999.
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-14
MULTIPLEXERSBASIC MULTIPLEXER (MUX)
COMBINATIONAL LOGIC
•ENCODERS-DESIGN W/ ENCODERS-PRIORITY ENCODERS-DESIGN W/ P-ENCODERS
• Selects one of many inputs to be directed to an output.
4x1
Mul
tiple
xer
S1 S0
0
1
2
3
f
X Y
A0
A1
A2
A3
0
X
1
X
X
X
X
X
X
0
X
1
X
X
X
X
0
0
0
0
0
1
0
1
A0=0
A2=0
A0=1
A2=1
A2A3Y A1 A0X
OutputInputsF
X
X
X
X
0
X
1
X
X
X
X
X
X
0
X
1
1
1
1
1
0
1
0
1
A1=0
A3=0
A1=1
A3=1
E
Module Enable
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-15
MULTIPLEXERSUSING PASS GATES
COMBINATIONAL LOGIC
•ENCODERS•MULTIPLEXERS
-BASIC MULTIPLEXER
• The 4x1 mux can be implemented with pass gates as follows.
Out (f)
A0
A1
A2
A3
Y X
Only one of An gets passed to output.Depends on the value of X and Y.
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-16
MULTIPLEXERSDESIGN WITH MULTIPLEXERS
COMBINATIONAL LOGIC
•ENCODERS•MULTIPLEXERS
-BASIC MULTIPLEXER-USING PASS GATES
• Any Boolean function can be implemented by setting the inputs
corresponding to the function and the selectors as the variables.
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F1ZYX
8x1
Mul
tiple
xer
S2 S1
0123
f
X Y
0101
E
Module Enable
S0
Z
40506071
Example:
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-17
DEMULTIPLEXERSBASIC DEMULTIPLEXER
COMBINATIONAL LOGIC
•MULTIPLEXERS-BASIC MULTIPLEXER-USING PASS GATES-DESIGN W/ MULTIPLEX.
• Takes one input and selects one of many outputs to direct the input.
1x4
Dem
ultip
lexe
r 0
1
2
3
W
D0
D1
D2
D3
W=0
0
W=1
0
0
0
0
0
0
W=0
0
W=1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
D2D3Y D1 D0X
OutputsInputsW
0
0
0
0
W=0
0
W=1
0
0
0
0
0
0
W=0
0
W=1
1
1
1
1
0
1
0
1
0
0
1
1
E
Module Enable
S1 S0
X Y
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-18
DEMULTIPLEXERSDESIGN W/ DEMULTIPLEXERS
COMBINATIONAL LOGIC
•MULTIPLEXERS•DEMULTIPLEXERS
-BASIC DEMULTIPLEXER
• A demultiplexer is useful for routing an input to a desired location.
Example:
1x4
Dem
ultip
lexe
r 0
1
2
3
E
1
S1 S0
X Y
Processing Unit 0
Processing Unit 1
Processing Unit 2
Processing Unit 3
Selects which PU to sendthe input data.
Input Data
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-22
ADDERSHALF- AND FULL-ADDERS
COMBINATIONAL LOGIC
•DEMULTIPLEXERS•SHIFTERS•ROTATORS
-BASIC ROTATOR
• Two basic building blocks for arithmetic are half- and full-adders as
depicted by the block diagrams below.
Half-adder Full-adder
HA
BA
S
COUT
Sum
Carry-outFA
BA
S
COUT
Sum
Carry-out
CIN
Carry-in
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-23
ADDERSHALF-ADDER (HA)
COMBINATIONAL LOGIC
•SHIFTERS•ROTATORS•ADDERS
-HALF- & FULL-ADDERS
• First of all, how do we add?
• 2’s complement arithmetic allows us to add numbers normally.
0
0
1
1
0
1
0
1
BA
0
0
0
1
0
1
1
0
S COUT
S AB AB+ A B⊕= =
COUT AB=
Sum Carry-outInputs
AB
S
COUT
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-24
ADDERSFULL-ADDER (FA) (1)
COMBINATIONAL LOGIC
•ROTATORS•ADDERS
-HALF- & FULL-ADDERS-HALF-ADDER (HA)
• Half-adder missed a possible carry-in. A full-adder (FA) includes this
additional carry-in.
0000
0011
BA
0001
0110
S COUT
S A B⊕( ) CIN⊕=
COUT AB CIN A B⊕( )+=
Sum Carry-outInputs
0101
CIN
Carry-in
1111
0011
0101
1001
0111
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-25
ADDERSFULL-ADDER (FA) (2)
COMBINATIONAL LOGIC
•ADDERS-HALF- & FULL-ADDERS-HALF-ADDER (HA)-FULL-ADDER (FA)
S A B⊕( ) CIN⊕=
COUT AB CIN A B⊕( )+=
S
COUT
AB
CIN
Half-adder Half-adder
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-26
ADDERSBINARY ADDITION
COMBINATIONAL LOGIC
•ADDERS-HALF- & FULL-ADDERS-HALF-ADDER (HA)-FULL-ADDER (FA)
• A 4-bit binary adder can be formed with four full-adders as follows.
FA
B0A0
S0
C1C0FA
B1A1
S1
C2FA
B2A2
S2
C3FA
B3A3
S3
C4
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-27
COMPARATORSMAGNITUDE COMPARATOR
COMBINATIONAL LOGIC
•ADDERS-HALF-ADDER (HA)-FULL-ADDER (FA)-BINARY ADDITION
• Given two n-bit magnitudes, A and B, a comparator indicates whether
• A = B, A > B, or A < B
4-BitComparator
G Greater (A > B)
E Equal (A = B)
L Less (A < B)
An
Bn
cinGGreater
cinEEqual
cinLLess
Cascaded inputvalues from other
comparators
n-bit input magnitudes
Results ofcomparisons
R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.CHAPTER VI-28
COMPARATORSMAGNITUDE COMPARATOR
COMBINATIONAL LOGIC
•ADDERS•COMPARATORS
-MAG. COMPARATOR
• The approach is to use the XNOR function (equivalence) on each of the n-
bits as follows
• The Boolean functions for a 4-bit magnitude comparator is as follows
•
•
•
Note: indicates whether , indicates whether ,
and indicates whether .
xi AiBi AiBI+ Ai Bi⊕= =
A B=( ) x3x2x1x0=
A B>( ) A3B3 x3A2B2 x3x2A1B1 x3x2x1A0B0+ + +=
A B<( ) A3B3 x3A2B2 x3x2A1B1 x3x2x1A0B0+ + +=
AiBi Ai Bi> AiBi Ai Bi<
xi Ai Bi=
Recommended