CS 61C: Great Ideas in Computer Architecture Lecture 23...

CS61C:GreatIdeasinComputerArchitecture

Lecture23:VirtualMemory

Krste Asanović &RandyH.Katz

http://inst.eecs.berkeley.edu/~cs61c/fa17

1Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• PageFaults• HierarchicalPageTables• CachingPageTableEntries(TLB)

2Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• PageFaults• HierarchicalPageTables• CachingPageTableEntries(TLB)

3Fall2017-- Lecture#2311/15/17

VirtualMachine

• 100’sofprocesses− OSmultiplexestheseoveravailablecores

• Butwhataboutmemory?− Thereisonlyone!− Wecannotjust”save”itscontentsinacontextswitch…

100+Processes,managedbyOS

4Fall2017-- Lecture#2311/15/17

Virtualvs.PhysicalAddresses

• Processesusevirtualaddresses,e.g.,0…0xffff,ffff− Manyprocesses,allusingsame(conflicting)addresses

• Memoryusesphysicaladdresses(also,e.g.,0...0xffff,ffff)• Memorymanagermapsvirtualtophysicaladdresses

Processor(&Caches)

Control

DatapathPC

Registers(ALU)

Memory(DRAM)

Bytes?

Virtua

lAdd

ress

PhysicalAdd

ress

Manyofthese(software&hardwarecores) Onemainmemory

5Fall2017-- Lecture#2311/15/17

AddressSpaces

• Addressspace=setofaddressesforallavailablememorylocations• Now,twokindsofmemoryaddresses:

−VirtualAddressSpace§ Setofaddressesthattheuserprogramknowsabout

−PhysicalAddressSpace§ Setofaddressesthatmaptoactualphysicallocationsinmemory§ Hiddenfromuserapplications

•Memorymanagermapsbetweenthesetwoaddressspaces

6Fall2017-- Lecture#2311/15/17

ConceptualMemoryManagerMemory(DRAM)

Concept:Realmemorymanagersusemorecomplexmappings.

7Fall2017-- Lecture#2311/15/17

ResponsibilitiesofMemoryManager

1) Mapvirtualtophysicaladdresses2) Protection:

− Isolatememorybetweenprocesses− Eachprocessgetsdedicate”private”memory− Errorsinoneprogramwon’tcorruptmemoryofotherprogram− PreventuserprogramsfrommessingwithOS’memory

3) Swapmemorytodisk− Giveillusionoflargermemorybystoringsomecontentondisk− DiskisusuallymuchlargerandslowerthanDRAM

§ Use“clever”cachingstrategies

8Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• HierarchicalPageTables• CachingPageTableEntries(TLB)

9Fall2017-- Lecture#2311/15/17

MemoryManager

• Severaloptions• Today“pagedmemory”dominates

−Physicalmemory(DRAM)isbrokenintopages−Typicalpagesize:4KiB+

pagenumber(e.g.,20Bits) offset(e.g.,12Bits)

Virtualaddress(e.g.,32Bits)

10Fall2017-- Lecture#2311/15/17

PagedMemoryPageN

Page2

Page1

Page0

Memory(DRAM)PageTable

PageTable

PageTable

Eachprocesshasadedicatedpagetable.Physicalmemorynon-consecutive.11Fall2017-- Lecture#2311/15/17

PagedMemoryAddressTranslation• OSkeepstrackofwhichprocessisactive

− Choosescorrectpagetable• Memorymanagerextractspagenumberfromvirtualaddress• Looksuppageaddressinpagetable• Computesphysicalmemoryaddressfromsumof− Pageaddressand− Offset(fromvirtualaddress)pagetableentry offset

Virtualaddress(e.g.32Bits)

pagenumber offset

Physicaladdress

Physicaladdressesmay(butdonothaveto)havemoreorfewerbitsthanvirtualaddresses

12Fall2017-- Lecture#2311/15/17

Protection

• AssigningdifferentpagesinDRAMtoprocessesalsokeepsthemfromaccessingeachothersmemory− Isolation− PagetableshandledbyOS(insupervisorymode)

• Sharingisalsopossible− OSmayassignsamephysicalpagetoseveralprocesses

13Fall2017-- Lecture#2311/15/17

WriteProtectionPageN

Page2

Page1

Page0

Memory(DRAM)

0

0

1

PageTable

1

0

0

1

PageTable

0

PageTable

Exceptionwhenwritingtoprotectedpage(e.g.,programcode)

Writeprotected

14Fall2017-- Lecture#2311/15/17

WhereDoPageTablesReside?

• E.g.,32-Bitvirtualaddress,4-KiBpages−Singlepagetablesize:

§ 4x220 Bytes=4-MiB§ 0.1%of4-GiBmemory§ Butmuchtoolargeforacache!

• Storepagetablesinmemory(DRAM)−Two(slow)memoryaccessesperlw/sw oncachemiss−Howcouldweminimizetheperformancepenalty?

§ Transferblocks(notwords)betweenDRAMandprocessorcacheo Exploitspatiallocality

§ Useacacheforfrequentlyusedpagetableentries…

15Fall2017-- Lecture#2311/15/17

PagedTableStorageinDRAM

Page Table

PageTable

Page

PageTable

Memory(DRAM)

lw/sw taketwomemoryreferences16Fall2017-- Lecture#2311/15/17

Blocksvs.Pages

• Incaches,wedealtwithindividualblocks− Usually~64Bonmodernsystems

• InVM,wedealwithindividualpages− Usually~4KBonmodernsystems

• Commonpointofconfusion:− Bytes,−Words,− Blocks,− Pages

§ Arealljustdifferentwaysoflookingatmemory!

17Fall2017-- Lecture#2311/15/17

Bytes,Words,Blocks,PagesE.g.: 16KiBDRAM,4KiBPages(forVM),128Bblocks(forcaches),

4Bwords(forlw/sw)

Page3

Page2

Page1

Page0

16KiB

Block0

Block31

Word0

Word31

1of1Memory

1of4PagesperMemory 1of32BlocksperPage

Canthinkofmemoryas:• 4Pages,or• 128Blocks,or• 4096Words,or• 16,384Bytes

Canthinkofapageas:• 32Blocks,or• 1024Words

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19Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• HierarchicalPageTables• CachingPageTableEntries(TLB)

20Fall2017-- Lecture#2311/15/17

MemoryHierarchy• Disk

−Slow−Buthuge−Howcouldwemakeuseofitscapacity(whenrunninglowonDRAM)?

21Fall2017-- Lecture#2311/15/17

Aside…WhyareDisksSoSlow?

• 10,000rpm(revolutionsperminute)• 6ms perrevolution• Averagerandomaccesstime:3ms

22Fall2017-- Lecture#2311/15/17

WhatAboutSSD?

•Madewithtransistors•Nothingmechanicalthatturns• Like“Ginormous”registerfile

−Doesnot”forget”whenpowerisoff• Fastaccesstoalllocations,regardlessofaddress• Stillmuchslowerthanregister,DRAM

−Read/writeblocks,notbytes−Potentialreliabilityissues

23Fall2017-- Lecture#2311/15/17

PagedMemoryPageN

Memory(DRAM)

PageTable

PageTable

Eachprocesshasadedicatedpagetable.Physicalmemorynon-consecutive.

Valid:pageallocatedDRAM/disk

Disk

24Fall2017-- Lecture#2311/15/17

MemoryAccess

• Checkpagetableentry:−Valid?

§ Yes,validà InDRAM?o Yes,inDRAM:read/writedatao No,ondisk: allocatenewpageinDRAM

• Ifoutofmemory,evictapagefromDRAM

• Storeevictedpagetodisk• Readpagefromdiskintomemory• Read/writedata

§ NotValido allocatenewpageinDRAM

• Ifoutofmemory,evictapage• Read/writedata

PagefaultOSintervention

25Fall2017-- Lecture#2311/15/17

Remember:OutofMemory

• Insufficientfreememory:malloc() returnsNULL

$ gcc OutOfMemory.c; ./a.outfailed to allocate > 131 TiBytes

What’sgoingon?26Fall2017-- Lecture#2311/15/17

Write-ThroughorWrite-Back?

• DRAMactslike“cache”fordisk− Shouldwritesgodirectlytodisk(write-through)?−Oronlywhenpageisevicted?

•Whichoptiondoyoupropose?• Implementation?

27Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• HierarchicalPageTables• CachingPageTableEntries(TLB)

28Fall2017-- Lecture#2311/15/17

SizeofPageTables

• E.g.,32-Bitvirtualaddress,4-KiBpages−Singlepagetablesize:

§ 4x220 Bytes=4-MiB§ 0.1%of4-GiBmemory

−Totalsizefor256processes(eachneedsapagetable)§ 256x4x220 Bytes=256x4-MiB=1-GiB§ 25%of4-GiBmemory!

•Whatabout64-bitaddresses?

Howcanwekeepthesizeofpagetables“reasonable”?29Fall2017-- Lecture#2311/15/17

Options

• Increasepagesize−E.g.,doublingpagesizecutsPTsizeinhalf−Attheexpenseofpotentiallywastedmemory

• Hierarchicalpagetables−Withdecreasingpagesize

•Mostprogramsuseonlyfractionofmemory−SplitPTintwo(ormore)parts

30Fall2017-- Lecture#2311/15/17

HierarchicalPageTable– ExploitsSparsityofVirtualAddressSpaceUse

Level 1 Page TablePage size 10b à1024 x 4096B Level 2

Page Tables12b à 4096B

Data Pages

page in primary memory page in secondary memory

Root of the CurrentPage Table

p1

p2

Virtual Address

(ProcessorRegister)

PTE of a nonexistent page

p1 p2 offset01112212231

10-bitL1 index

10-bit L2 index

Phys

ical

Mem

ory

31Fall2017-- Lecture#2311/15/17

32Fall2017-- Lecture#2311/15/17

Administrivia

• Homework6wasreleased—duenextWednesday,Nov22• Project3isdueMonday

− Hiveserverswillgetmoreoverloadedclosertothedeadline− It’sinyourbestinteresttofinishassoonaspossible!

• ThereislectureonTuesday(I/O:DMA,Disks,Networking)• Thereisnodiscussionorlabnextweek

− EnjoyyourThanksgiving!

• Project4:SparkwillbereleasedbyMondaynight• Homework7willbereleasednextWednesday

33Fall2017-- Lecture#2311/15/17

Agenda

• VirtualMemory• PagedPhysicalMemory• SwapSpace• HierarchicalPageTables• CachingPageTableEntries(TLB)

34Fall2017-- Lecture#2311/15/17

AddressTranslationandProtection

• Every instruction and data access needs address translation and protection checks

Good VM design should be fast (~one cycle) and space efficient

Physical Address

Virtual Address

AddressTranslation

Virtual Page No. (VPN) offset

Physical Page No. (PPN) offset

ProtectionCheck

Exception?

Kernel/User Mode

Read/WriteMiss

35Fall2017-- Lecture#2311/15/17

TranslationLookaside Buffers(TLB)Address translation is very expensive!

In a two-level page table, each reference becomes three memory accesses

Solution: Cache some translations in TLBTLB hit Þ Single-Cycle TranslationTLB miss Þ Page-Table Walk to refill

VPN offset

V D tag PPN

physical address PPN offset

virtual address

hit?

(VPN = virtual page number)

(PPN = physical page number)

36Fall2017-- Lecture#2311/15/17

TLBDesigns• Typically32-128entries,usuallyfullyassociative

− Eachentrymapsalargepage,hencelessspatiallocalityacrosspages=>morelikelythattwoentriesconflict

− SometimeslargerTLBs (256-512entries)are4-8wayset-associative− Largersystemssometimeshavemulti-level(L1andL2)TLBs

• RandomorFIFOreplacementpolicy• “TLBReach”:SizeoflargestvirtualaddressspacethatcanbesimultaneouslymappedbyTLB

Example:64TLBentries,4KBpages,onepageperentry

TLBReach=_____________________________________________?

37Fall2017-- Lecture#2311/15/17

VM-relatedEventsinPipeline

• HandlingaTLBmissneedsahardwareorsoftwaremechanismtorefillTLB−Usuallydoneinhardware

• Handlingapagefault(e.g.,pageisondisk)needsaprecise trapsosoftwarehandlercaneasilyresumeafterretrievingpage• Protectionviolationmayabortprocess

PCInst TLB

Inst. Cache D Decode E M

Data TLB

Data Cache W+

TLB miss? Page Fault?Protection violation?

TLB miss? Page Fault?Protection violation?

38Fall2017-- Lecture#2311/15/17

HierarchicalPageTableWalk:SPARCv8

31 11 Offset

Virtual Address Index 1 Index 2 Index 3 Offset31 23 17 11 0

ContextTableRegister

ContextRegister

root ptr

PTPPTP

PTE

ContextTable

L1 Table

L2 TableL3 Table

Physical Address PPN

• MMU does this table walk in hardware on a TLB miss• FSM?

PTscanbeswappedtodisk,tooWhataboutcodehandlingpagefaults?

39Fall2017-- Lecture#2311/15/17

Page-BasedVirtual-MemoryMachine(HardwarePage-TableWalk)

PCInst.TLB

Inst.Cache D Decode E M

DataCache W+

PageFault?Protectionviolation?

PageFault?Protectionviolation?

• Assumespagetablesheldinuntranslated physicalmemory

DataTLB

MainMemory(DRAM)

MemoryControllerPhysicalAddress

PhysicalAddress

PhysicalAddress

PhysicalAddress

Page-TableBaseRegister

VirtualAddress Physical

Address

VirtualAddress

HardwarePageTableWalker

Miss? Miss?

40Fall2017-- Lecture#2311/15/17

AddressTranslation:puttingitalltogetherVirtual Address

TLBLookup

Page TableWalk

Update TLBPage Fault(OS loads page)

ProtectionCheck

PhysicalAddress(to cache)

miss hit

the page is Ïmemory Îmemory denied permitted

ProtectionFault

hardwarehardware or softwaresoftware

SEGFAULTWhere?41Fall2017-- Lecture#2311/15/17

ModernVirtualMemorySystemsIllusionofalarge,private,uniformstore

Protection & PrivacySeveral users/processes, each with their private address space

Demand PagingProvides the ability to run programs larger than the primary memory

Hides differences in machine configurations

The price is address translation on each memory reference

OS

useri

PrimaryMemory

Swapping Space (Disk)

VA PAmappingTLB

42Fall2017-- Lecture#2311/15/17

It’sJustthe“OS”…

• Let’swriteexecve− Codetheloadsprogramintomemoryforexecution−What’sthebestway?

43Fall2017-- Lecture#2311/15/17

Execve1. SetupPT

− forprogramcode− andstack−markPTEsasinvalid

2. Init argv,argc3. Callmain

− pagefault!4. Whathappens?

− .textand.datasectionscopied− pagebypage,ondemand,byVMsystem

Memory(DRAM) Disk

Architecturematters!44Fall2017-- Lecture#2311/15/17

And,inConclusion…

• Virtualandphysicaladdresses− Programà virtualaddress− DRAMà physicaladdress

• PagedMemory1. Facilitatesvirtualà physicaladdresstranslation2. Providesisolation&protection3. Extendsavailablememorytoincludedisk

• Implementationissues− Hierarchicalpagetables− Cachingpagetableentries(TLB)

45Fall2017-- Lecture#2311/15/17