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August 13, 2012 CS 6461 Instruction Set Architecture 3
?Design a New High Performance System?
• ISA– What instructions should we include
• Internal Organization– How do the instructions implemented affect the
internal organization (and subsequently performance)
• How best approach this problem?– Understand what a computer and an instruction set
architecture does for us
– Look at current architectures for insight
August 13, 2012 CS 6461 Instruction Set Architecture 4
Classifying ISA’s
• Type of Internal Storage– Stack
– Accumulator
– Set of Registers
August 13, 2012 CS 6461 Instruction Set Architecture 6
Design Decisions
• Instruction Set Architecture Class (Load-Store?)– How Many Registers (more is good)
• How Many Operands in the instruction?
August 13, 2012 CS 6461 Instruction Set Architecture 7
Code Sequences for the 4 Classes
• Since 1980s almost all new designs are load store architectures.– Machines have large register files
– Registers are easier for the compiler to manage (addressed in only one way)
Stack Accumulator Register
(register-memory)
Register
(load store)
Push A Load A Load R1, A Load R1, A
Push B Add B Add R3, R1, B Load R2, B
Add Store C Store R3, C Add R3, R1, R2
Pop C Store R3,C
August 13, 2012 CS 6461 Instruction Set Architecture 8
Number of Memory Addresses
Number of memory
addresses
Maximum number of operands
allowed
Type of Architecture Examples
0 3 Load-Store Alpha, ARM, MIPS, PowerPC, SPARC, SuperH, TM32
1 2 Register-Memory IBM 360/370, Intel 80x86, Motorola 68000, TI TMS320C54x
2 2 Memory – memory VAX (also has 3 operand formats)
3 3 Memory - memory VAX (also has 2 operand formats)
August 13, 2012 CS 6461 Instruction Set Architecture 9
Tradeoffs for the ISA Classes
Type Advantages Disadvantages
Register-register
(0,3)
Simple, fixed length instruction encoding. Simple code generation model. Instructions take similar numbers of clocks to execute.
Higher instruction count than architectures with memory references in the instructions. More instructions and lower instruction density leads to larger programs
Register-memory
(1,2)
Data can be accessed without a separate load instruction first. Instruction format tends to be easy to encode and yields good density
Operands are not equivalent since a source operand is destroyed. Encoding a register number and a memory address in each instruction may restrict the number of registers. Clocks per instruction vary by operand location
Memory-memory
(2,2) or (3,3)
Most compact. Does not waste registers for temporaries.
Large variation in instruction size, especially for three-operand instructions. In addition, large variation in work per instruction. Memory accesses create memory bottleneck. (Not used today)
August 13, 2012 CS 6461 Instruction Set Architecture 10
Memory Addressing(page B9)
• Register Add R4,R3 R4<- R4 + R3• Immediate Add R4,#3 R4<- R4 + 3• Displacement Add R4,100(R1) R4<- R4 + Mem[100+R1]• Register Indirect Add R4,(R1) R4<- R4 + Mem[R1]• Indexed Add R3,(R1+R2) R3<- R3 + Mem[R1+R2]• Direct Add R1, (1001) R1<- R1 + Mem[1001]• Memory Indirect Add R1, @(R3) R1<- R1 +
Mem[Mem[R3]]• AutoIncrement Add R1, (R2)+ R1<- R1 + Mem[R2]
R2<- R2 +d• AutoDecrement Add R1, -(R2) R2<- R2 - d
R1<- R1 + Mem[R2]• Scaled Add R1, 100(R2)[R3] R1<- (R1) +
Mem[100+(R2) + (R3)*d]
August 13, 2012 CS 6461 Instruction Set Architecture 11
Summary of Use of Addressing Modes for DEC VAX Architecture
August 13, 2012 CS 6461 Instruction Set Architecture 13
About ¼ of Data Transfers and ALU Operations Have an Immediate Operand
August 13, 2012 CS 6461 Instruction Set Architecture 15
Type and Size of Operands
• 8, 16, 32, 64 bits• Alignment• Fetch capability• Encoding type
August 13, 2012 CS 6461 Instruction Set Architecture 17
Control Flow
• Addressing modes• Conditional branch operations• Frequency distributions
August 13, 2012 CS 6461 Instruction Set Architecture 20
Frequency of Different Types of Compares in Conditional Branches
August 13, 2012 CS 6461 Instruction Set Architecture 22
Fig 2.23 Three Variations In Instruction Encoding
August 13, 2012 CS 6461 Instruction Set Architecture 23
Instruction Encoding
• Balance– Desire to have as many registers and addressing modes
as possible
– The impact of the size of the register and addressing mode fields on the average instruction size and hence average program size
– A desire to have instructions encoded into lengths that will be easy to handle in a pipelined implementation
August 13, 2012 CS 6461 Instruction Set Architecture 24
The Role of Compilers
• Structure• Optimizations• Register Allocation (tied with hardware)• Impact of Compiler Technology on Architects
Decisions
August 13, 2012 CS 6461 Instruction Set Architecture 26
Fig 2.26 Change in Instruction Count From Compiler Optimization (SPEC2000)
August 13, 2012 CS 6461 Instruction Set Architecture 27
MIPS Instruction Set
• MIPS 64 has 32 general purpose registers of 64 bits in length (R0…R31)– Value of R0 is always 0
• 32 floating point registers capable of holding 32 or 64 bit floating point numbers
• Instruction formats– I type immediate
– R type register-register
– J type jump
August 13, 2012 CS 6461 Instruction Set Architecture 28
MIPS Instruction Set
• Instruction nomenclature– Opcode
– Registers rs, rd, rt
August 13, 2012 CS 6461 Instruction Set Architecture 30
Fallacies and Pitfalls
• Pitfall – Designing a “high-level” instruction set feature specifically oriented to supporting a high-level language structure.
• Fallacy – There is such a thing as a typical program
• Pitfall – Innovating at the instruction set architecture to reduce code size without accounting for the compiler.
• Fallacy – An architecture with flaws cannot be successful
• Fallacy – You can design a flawless machine
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