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CSC321
Where We’ve Been
• Binary representations
• Boolean logic
• Logic gates – combinational circuits
• Flip-flops – sequential circuits
• Complex gates – modules
• Circuit design techniques
• Assembly language programming
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What We Can Do
• Create digital systems– Interconnection of modules to accomplish a
specific task– Through an appropriate set of modules and
connections we can create a digital computer– Rather than show the circuits in all their
glorious detail we use an abstract representation
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Architectural Functional Block Diagram
ADDRESS BUS (External) 16 bit
I-RAMGeneral Registers
STACKBit-addressable
SFRs etc.
Temporaryregister
ALU8-bit
DAT
A B
US
(Ext
erna
l) 8
bitInternal data bus
Memory AddressRegister
(Uses P0 and P2)
DPT
R
P.C
.
Internal Memory
InstructionRegister
AccAccumulatorB
Temporaryregister
Instructiondecoder/
control logic
CACF0
RS1RS2OV
P
PSWflags
Con
trol L
ines
RD/ WR/ PSEN/ALE/ etc.
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So What?
• A digital computer is a fascinating thing in and of itself but somewhat useless
• It is the job of the programmer to make it do something useful
• The programmer’s job is to supply specific, detailed instructions to move and manipulate binary data patterns within the architecture to accomplish a meaningful task
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Sounds Easy
• The problem is that we [the programmers] don’t want to be burdened with the knowledge of gates, registers, flip-flops, etc.
• So, we describe the architecture in terms of various parameters useful to the programmer
• Note that “the programmer” may not be an “applications programmer” – it may be a “language compiler writer”, for example
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Descriptive Parameters
• The set of registers within the architecture– The names and functions (uses) of the registers
• The set of operations available for moving data between registers and manipulating data contained within registers– Microoperations
• The method of specifying the sequence of execution of the microoperations
• Note that this is a level lower than assembly language
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Microoperations
• To describe the operations we use a language called Register Transfer Language
• We [as programmers] assume that the logic circuits [combinational and/or sequential] are available to perform the “transfers”
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Register Transfer Language
• A register is nothing but a small, fast piece of memory
• A system for expressing in symbolic form the micro-operation sequences among the registers of a digital module
• Note [again] that this is not Assembly Language!!!
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Register Transfer Language(RTL)
• Registers are designated by capital letters– MAR – Memory Address Register
– PC – Program Counter
– IR – Instruction Register
– Rx – General purpose register
– etc.
• Bits within registers are numbered 0 to n-1 (n-bit register) starting at the LSB (rightmost bit)
• What are registers made of?
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Register Representations(Pictorial)
R1 7 6 5 4 3 2 1 0
R107
R2015 015
R2(H) R2(L)78
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Register Transfers
• Move the data from one register to another
• The bit pattern that is in register R1 is copied into register R2– Again, we are assured that the circuitry required to
perform the transfer is available– Implies a parallel load operation
R1R2
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Conditional Transfer
• Conditionally move the data from one register to another
• The bit pattern that is in register R1 is copied into register R2 if the control signal P is high (1)– This isn’t a Java “if/then” statement!– Again, we are assured that the circuitry required to
perform the transfer is available– Implies a parallel load operation
R1if (P = 1) then R2
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Control Function
• Conditionally move the data from one register to another
• Same meaning as the if/then statement
• P may be [typically is] a complex logic expression/combinational circuit
R1P: R2
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Hardware Implication
R1P: R2
Controlcircuit R2
R1
clockP Load
n
clock
load
• Rising edge of clock sets the load signal
• Next rising edge cause the transfer to occur
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Parallel Operations
• Some microoperations take multiple clock cycles (periods)
• Some microoperations can be performed simultaneously (in parallel)– During the same clock edge transition
– It’s this kind of operation that distinguishes between computers and “super computers”
R1, R3P: R2 R0
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Data Paths
• We’ve been assuming that the circuitry to perform the transfers exists
• Two choices for realizing this assumption
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Data Paths
• Lots and lots of little wires• Every register pair that can transfer data
must be wired together
3 2 1 0
C0C1C2C3
register C
3 2 1 0
B0B1B2B3
register B
3 2 1 0
A0A1A2A3
register A
3 2 1 0
D0D1D2D3
register D
• You would have to do this for all registers!
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Data Paths
• Common bus– A set of n wires (for n-bit register transfers)
shared by all registers– Registers take turns putting their bit patterns
onto the bus
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Bus Implementation
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0
4 x 1MUX
3 2 1 0
4 x 1MUX
3 2 1 0
4 x 1MUX
3 2 1 0
4 x 1MUX
A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3
A0B0C0D0A1B1C1D1A2B2C2D2A3B3C3D3
bit 0bit 1bit 2bit 3
select 0select 1
register D register C register B register A
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Bus Implementation
• Completing the transfer (we now have data bits from a register on the bus)– Simple – we just connect the bus data lines to
the inputs of the registers– The data is then available to all registers on the
bus– We activate the Load line for the actual
destination register
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Register Transfer Language
• In long-hand:
• In short-hand
• Bus activation is implied
R1, R2BUS BUS
R1R2
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Three-State Gates
• In constructing the bus we used multiplexers– Convenient but expensive in terms of size and
money
• An alternative is the three-state gate– Similar to the logic gates we’ve looked at so far
(NOT, AND, OR, NAND, NOR, XOR)– Different in that they’re not binary
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Three-State Gates
• Three-state gates have a 3rd output value that corresponds to “no output”– When in this state the gate is effectively out of
the circuit – it acts as if it isn’t even there– Technically, this is called a high-impedance
state and acts as an open circuit
• You’ll also here these called tri-state gates
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Three-State Gates
• The most common tri-state gate is the buffer• What’s a buffer?
• What’s a tri-state buffer?
input output
0 0
1 1
input control output
0 0 open
0 1 0
1 0 open
1 1 1
input output
control
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Tri-State Buffer Usage
2 x 4Decoder
0123
S0
S1
E
A0
B0
C0
D0
A3
B3
C3
D3
bit 0
bit 3
Select
Enable
from registers
from registers
bus lines
─ 1 decoder─ A bunch of buffers
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Memory Transfers
• Recall we must specify a direction (read/write), a source address, and a destination address
• Read from memory location at address in the AR register (Address Register) and place the contents into the R1 register
M[AR]Read: R1
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Memory Transfers
• Write (copy) the contents of register R1 to the memory location at address in the AR register (Address Register)
R1Write: M[AR]
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Register Transfer Language (RTL)Arithmetic Operations
R1 + R3R2R1 - R3R2
R1R2R1 + 1R2R2 + R1 + 1R2
R1 + 1R2R1 - 1R2
Addition
Subtraction
Increment
Decrement
Negate (2’s complement)
Complement (invert bits)
Subtraction
• We need circuits to do all these operations
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Binary Adder Circuit
• Recall there are two types of adder– Half adder
• Adds two bits
• Produces a sum and carry
– Full adder• Adds three bits
• Produces a sum and carry
S
C
S
C
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Creating Larger Adders
• Connect full adders together– n-bit binary adder is created from n full adders
Full Adder Full Adder Full Adder Full Adder
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
Cout S3 S2 S1 S0
4-bit binary adder
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Binary Subtractor
• Subtraction is performed by a 2’s complement operation followed by an addition
Full Adder Full Adder Full Adder Full Adder
B3 A3B2 A2
B1 A1B0 A0
C3 C2 C1
C0
Cout S3 S2 S1 S0
M
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Incrementer
• Can use a binary adder with a 1 as the 2nd input• Can be done more simply with a series of half
adders
HalfAdder
HalfAdder
HalfAdder
HalfAdder
A0A1A2A3 1
S3 S2 S1 S0C3 C2 C1 C0
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Decrementer
• Subtractor with a 1 at the 2nd input
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Arithmetic Unit
• We don’t want all these separate circuits in our system– Too much space, too much complexity, too
much money
• Can we combine all these operations in a single circuit?
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Arithmetic Unit
4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX
Full Adder Full Adder Full Adder Full Adder
0B3B2B1B0A0 A1 A2 A3Cin
Cout
S0S1
D3D2D1D0
0 1 2 3S1S00 1 2 3S1S00 1 2 3S1S00 1 2 3S1S0
Note: MSB is on the right, LSB is on the left
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Select Lines Set To 00
4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX
Full Adder Full Adder Full Adder Full Adder
0B3B2B1B0A0 A1 A2 A3Cin
Cout
S0S1
D3D2D1D0
0 1 2 3S1S00 1 2 3S1S00 1 2 3S1S00 1 2 3S1S0
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Select Lines Set To 01
4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX
Full Adder Full Adder Full Adder Full Adder
0B3B2B1B0A0 A1 A2 A3Cin
Cout
S0S1
D3D2D1D0
0 1 2 3S1S00 1 2 3S1S00 1 2 3S1S00 1 2 3S1S0
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Select Lines Set To 10
4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX
Full Adder Full Adder Full Adder Full Adder
0B3B2B1B0A0 A1 A2 A3Cin
Cout
S0S1
D3D2D1D0
0 1 2 3S1S00 1 2 3S1S00 1 2 3S1S00 1 2 3S1S0
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Select Lines Set To 11
4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX
Full Adder Full Adder Full Adder Full Adder
0B3B2B1B0A0 A1 A2 A3Cin
Cout
S0S1
D3D2D1D0
0 1 2 3S1S00 1 2 3S1S00 1 2 3S1S00 1 2 3S1S0
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Summary
Select
S0 S1 Cin 1st Operand 2nd Operand Output (D) Microoperation
0 0 0 A B A + B add
0 0 1 A B A + B + 1 add with carry
0 1 0 A B’ A + B’ subtract with borrow
0 1 1 A B’ A + B’ + 1 subtract
1 0 0 A 0 A transfer (assignment)
1 0 1 A 0 A + 1 increment
1 1 0 A 1 A - 1 decrement
1 1 1 A 1 A transfer (assignment)
Where are we?
• This takes us up to section 4-5• Homework:
– 4-1, 4-2, 4-3, 4-6, 4-7, 4-8
– Due next lecture
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