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Department of EECS University of California, Berkeley
EECS 105 Spring 2017, Module 4
Prof. Ali M. Niknejad Prof. Rikky Muller
Current Mirrors and Biasing
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
2
Announcements
l HW9 due on Friday
University of California, Berkeley
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
3
Load Impedance
Courtesy M.H. Perrott
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
4
Issue: Headroom Limitations
Courtesy M.H. Perrott
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
5
Achieving High Gain
Courtesy M.H. Perrott
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
6
Diode Connected Device
l How do we build current sources? l Let’s start with a “diode connected” device l A MOS device with gate and drain shorted operates
like a diode (but not exponential) University of California, Berkeley
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
7
Diode Connected -- SS Model
l We can derive the small-signal model by shorting out the hybrid-pi model
l Note that a Gm generator with it’s controlling terminals connected to the Gm is more simply a …?
University of California, Berkeley
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
8
The Integrated “Current Mirror” l M1 and M2 have the same
VGS l If we neglect CLM (λ=0),
then the drain currents are equal
l Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1
l We say that the current IREF is mirrored into iOUT
l Notice that the mirror works for small and large signals!
University of California, Berkeley
High Res
Low Resis
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Multiplication Ratio
University of California, Berkeley
VGS1 =VGS 2
IOUT = kW2
L2(VGS 2 −VT )
22 = IINW2 / L2W1 / L1
= NIIN
IIN = kW1L1(VGS1 −VT )
2 IOUT = kW2
L2(VGS 2 −VT )
2
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Current Mirror as Current Source
l The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET
l M2 acts like a current source to the rest of the circuit l For good current source behavior, what is the minimum vOUT?
University of California, Berkeley
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
11
Small-Signal Resistance of I-Source
University of California, Berkeley
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
12
Improved Current Sources
University of California, Berkeley
Goal: increase Ro(ut) Approach: look at amplifier output resistance results … to see topologies that boost resistance
Looks like the output impedance of a common-source amplifier with source degeneration
out oR r>>
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Effect of Source Degeneration
l Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance
l Output impedance is boosted by factor University of California, Berkeley
( )St t m gs o Rv i g v r v= − +
1eq
m
Rg
≈
Sgs Rv v≈ −
SR t Sv i R=
( )t t m S t o t Sv i g R i r i R= + +
( )1to m S o
t
vR g R ri
= ≈ +
( )1 m Sg R+
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
14
Improved Current Sources
University of California, Berkeley
How would you scale the output current?
IIN = kW1L1(VG −VS −VT )
2
VS = IIN RS
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
15
Cascode (or Stacked) Current Source
University of California, Berkeley
Insight: VGS2 = constant AND VDS2 = constant
Small-Signal Resistance Ro:
( )1o m S oR g R r≈ +
( )1o m o oR g r r≈ +
20o m oR g r r≈ >>
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
16
Drawback of Cascode I-Source
University of California, Berkeley
What is the minimum output voltage to keep all transistors in saturation?
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
17
Drawback of Cascode I-Source
University of California, Berkeley
Minimum output voltage to keep both transistors in saturation:
, 4, 2,OUT MIN DS MIN DS MINV V V= +
vOUT
iOUT
2, 2 0 2DS MIN GS T DSATV V V V> − =
4 2 4 2 4 0D DSAT GS GS GS TV V V V V V> + = + −
, 2 4 0OUT MIN GS GS TV V V V= + −
In EE140 we will learn circuit tricks to overcome this problem!
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Current Sinks and Sources
University of California, Berkeley
Sink: output current goes to ground
Source: output current comes from voltage supply
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Current Mirrors
University of California, Berkeley
Idea: we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier.
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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Example: Common-Drain Amplifier
University of California, Berkeley
21 ( )2DS ox GS T
WI C V VL
µ= −
vin
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
21
Common Drain AC Schematic
University of California, Berkeley
vin
How does a REAL current source fit in to the small-signal model?
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
22
CD Voltage Gain With Real I-Source
University of California, Berkeley
RL
Ideal I-Source voutRL || ro
= gmvgs
voutRL || ro
= gm vin − vout( )
vin
Real I-Source
EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller
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CD Voltage Gain (Cont.)
University of California, Berkeley
KCL at source node:
Voltage gain:
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