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Dataflow Modeling ofSignal Processing and
Communication Systems
Wireless Networking and Communications Group
April 21, 2023
Prof. Brian L. Evans
Guest Lecture forEE 382V Embedded System Design and Modeling
2
Outline
Introduction Signal processing system design needs Synchronous dataflow
Signal processing building blocks Filters Rate changers
Signal processing examples Communication system examples Conclusion
2
3
Needs for System-Level Design
Signal processing algorithms Multirate processing: e.g. interpolation Local feedback: e.g. IIR filters Iteration: e.g. decoding
Graphical representations Block diagram syntax natural but static Dataflow semantics for signal processing
Signal representations Bit, byte, integer, fixed-point, floating-point Complex-valued versions of above Vectors/matrices of scalar data types
Do not needrecursion
Often iterative
Bit error rate vs. Signal-to-noise ratio (Eb/No)
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4
Needs for Embedded Realization
Block-based and point-by-point processing Retarget simulation for embedded platforms
Processors (e.g. DSPs) and hardware (e.g. FPGAs) Cosimulation on desktop and embedded platforms
Static scheduling Prediction of resources (e.g. memory) at compile time DSPs have limited on-chip memory (32-512 kB) FPGAs have limited on-board memory & logic blocks
Floating-point to fixed-point conversion
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5
Dataflow Models
Match data-intensive processing Signal processing Communication systems
Definitions [Lee] A token is a data value or data structure A signal is a sequence of tokens A node maps input tokens onto output tokens Set of firing rules specify when a node can fire A firing of a node consumes input tokens and produces output
tokens A sequence of firings is a dataflow process
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Synchronous Dataflow [Lee 1987]
Untimed Arcs: one-way first-in first-out (FIFO) queues Nodes: functional blocks
Source nodes always enabledOthers enabled when enough
samples are on all inputs Node execution
Consumes same fixed number of samples on each input arcProduces same fixed number of tokens on each output arcConsumed data is dequeued from arc
Flow of data through graph does not depend on data values
A3
B2
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7
Synchronous Dataflow (SDF)
Delay of (n) samplesn samples initially in FIFO queue
Systems are determinateExecution in sequence or parallel
has same outcome (predictable) Systems can be statically analyzed
Check for “sampling rate” consistencyDetermine/optimize FIFO queue sizes at
compile time Models systems with rational rate changes
A3
B2
(6) 23
Nodes are not multirate but graph is!
Periodic schedule fires A twice & B thrice, e.g.
AABBB or ABABB
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8
Dataflow Models in Design Tools
Design Tool Dataflow Model(s) Example Applications
Agilent Advanced Design System
Synchronous and Timed Synchronous Dataflow
Mixed analog, digital, and RF communication systems
Coware Signal Proc. Worksystem
Synchronous and Dynamic Dataflow
Periodic digital systems, e.g. transceivers & MP3 decoders
National Instruments LabVIEW
Homogeneous Dynamic Dataflow (G)
Periodic and aperiodic digital systems
Synopsys CoCentric System Design Studio
Cyclostatic Dataflow Periodic digital systems, e.g. transceivers & mp3 decoders
UC Berkeley Ptolemy Classic
Synchronous and Dynamic Dataflow
Periodic and aperiodic digital systems
9
Outline
Introduction Signal processing system design needs Synchronous dataflow
Signal processing building blocks Filters Rate changers
Signal processing examples Communication system examples Conclusion
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10
Homogeneous Operations
Pointwise arithmetic operations (addition, etc.)
Delay by m samples property of SDF arc
Finite impulseresponse filter
0a1 11 1
1op
0a
1 1
1
mz
][kx
1z
][ky
0a 1Ma2Ma1a …
…1z1z
1
0
][ ][M
mm mkxaky
1
1
FIR
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Homogeneous Operations
Infiniteimpulseresponsefilter
x[k] y[k]
y[k-M]
x[k-1]
x[k-2] b2
b1
b0
UnitDelay
UnitDelay
UnitDelay
x[k-N] bN
Feed-forward
a1
a2
y[k-1]
y[k-2]
UnitDelay
UnitDelay
UnitDelay
aM
Feedback
M
mm
N
nn
mkya
nkxbky
1
0
][
][ ][
IIR
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Increasing Sampling Rate
Upsampling by L denoted as LOutputs input sample followed by L-1 zerosIncreases sampling rate by factor of L
Finite impulse response (FIR) filter g[m]Fills in zero values generated by upsamplerMultiplies by zero most of time
(L-1 out of every L times) Sometimes combined into
rate changing FIR block
m
Output of Upsampler by 4
1 2 3 4 5 6 7 80
1 2
Output of FIR Filter
3 4 5 6 7 8
m
0
1 2
Input to Upsampler by 4
n
0
g[m] 41 4 1 1
FIR1 4
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Polyphase Filter Bank Form
Filter bank (right) avoids multiplication by zeroSplit filter g[m] into L shorter polyphase filters operating at
lower rate (no loss in output precision)Saves factor of L in multiplications and prev. inputs stored and
increases parallelism by factor of L
g0[n]
g1[n]
gL-1[n]
s(Ln)
s(Ln+1)
s(Ln+(L-1))
g[m] L
Oversampling filter a.k.a. Pulse shaper a.k.a. Linear interpolator
Multiplies by zero (L-1)/L of the time
1 L
L1
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Decreasing Sampling Rate
Finite impulse response (FIR) filter g[m]Typically a lowpass filterEnforces sampling theorem
Downsampling by L denoted as LInputs L samplesOutputs first sample and discards L-1 samplesDecreases sampling rate by factor of L
Sometimes combined intorate changing FIR block
44 1
g[m]1 1
1 2
Input to Downsampler
3 4 5 6 7 8
m
0
1 2
Output of Downsampler
n
0
FIR4 1
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15
Polyphase Filter Bank Form
Filter bank (right) only computes values outputSplit filter h[m] into M shorter polyphase filters operating at
lower rate (no loss in output precision)Saves factor of M in multiplications and increases parallelism by
factor of L
h0[n]
h1[n]
hM-1[n]
h[m] M
s(Mn)
s(Mn+1)
s(Mn+(M-1))
Undersampling filter a.k.a. Matched filter + sampling a.k.a.
Linear decimator
Outputs discarded (M-1)/M of the time
1
1
M M
16
Outline
Introduction Signal processing system design needs Synchronous dataflow
Signal processing building blocks Filters Rate changers
Signal processing examples Communication system examples Conclusion
16
17
17
Spectral Shaping for Converter
Upsampling by 4Output input sample then 3 zerosIncreases sampling rate fourfold
FIR filter performs interpolation
176.4 kHz[Pohlmann]
Digital 4x Oversampling Filter
4FIR Filter
fstop< 22.05 kHz16 bits
176.4 kHz
Spectral shapingfor an audio data converter
18
Noise-Shaped Feedback Coding
Homogeneous. Computable?b(m)+
_
_
+
e(m)
x(m)
difference quantizer
compute error (noise)
shapeerror (noise)
u(m)
)(mh
Sigma-delta modulator using noise-shaped
feedback coding (spectral shaping)
Original Image
Threshold at Mid-Gray
Noise-Shaped
19
Outline
Introduction Signal processing system design needs Synchronous dataflow
Signal processing building blocks Filters Rate changers
Signal processing examples Communication system examples Conclusion
19
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Communication Systems
Message signal m[k] is information to be sentInformation may be voice, music, images, video, dataLow frequency (baseband) signal centered at DC
Transmitter signal processing includes lowpass filtering to enforce transmission band
Transmitter carrier circuits upconvert signal
SignalProcessing
CarrierCircuits
Transmission Medium
Carrier Circuits
SignalProcessing
TRANSMITTER RECEIVERs(t) r(t)
][ˆ km
CHANNEL
][km
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Communication Systems
Propagating signals experienceattenuation & spreading w/ distance
Receiver carrier circuits downconvert to an intermediate frequency and possibly baseband
Receiver signal processing extracts/enhances baseband signal
SignalProcessing
CarrierCircuits
Transmission Medium
Carrier Circuits
SignalProcessing
TRANSMITTER RECEIVERs(t) r(t)
][ˆ km
CHANNEL
][km
Model the environment
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Quadrature Amplitude Modulation
i[n] gT[m] L
+cos(0 m)
q[n] gT[m] L
sin(0 m)
Serial/parallel
converter1
BitsMap to 2-D constellationJ
L samples per symbol (upsampling)
Digital QAM Transmission
Pulse shaper
(FIR filter)
Index
SignalProcessing
CarrierCircuits
Transmission Medium
Carrier Circuits
SignalProcessing
TRANSMITTER RECEIVERs(t) r(t)
][ˆ km
CHANNEL
][km
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23
Quad. Amplitude Demodulation
iest[n]hopt[m] L
cos(0 m)
hopt[m] L
sin(0 m)
L samples per symbol (downsampling)
Matched filter
(FIR filter)
qest[n]
Parallel/serial
converterJ
Bits
DecisionDevice 1
Digital QAM Reception
Symbol
SignalProcessing
CarrierCircuits
Transmission Medium
Carrier Circuits
SignalProcessing
TRANSMITTER RECEIVERs(t) r(t)
][ˆ km
CHANNEL
][km
heq[m]
Channel equalizer (FIR filter)
24
Modeling of Points In-Between
Baseband channel model Combines transmitter carrier circuits, channel and receiver
carrier circuits One model uses cascade
of gain, FIR filter, andadditive noise(homogeneous SDF)
SignalProcessing
CarrierCircuits
Transmission Medium
Carrier Circuits
SignalProcessing
TRANSMITTER RECEIVERs(t) r(t)
][ˆ km
CHANNEL
][km
0a FIR +
noise
25
Limitations of SDF
Strengths of SDF are also its limitations Untimed Predictable flow of data through graph
Modeling of receiver front end Automatic gain control (AGC) Symbol clock recovery (digital IIR) Receive filter (analog IIR)
25
Receive Filter
A/D
SymbolClockRecovery
CarrierDetect
AGC
Analog front end for QAM reception
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Conclusion
Synchronous dataflow model does not support Composability with itself Data-dependent graphs Recursion
Advantages Models multirate systems Ability to generate static schedules at compile time (resources
required by graph known in advance) Static sequential schedules can be optimized for minimum
program memory or buffer memory SDF modeling allows efficient simulation and synthesis SDF well-matched to signal processing and communications
Synchronous dataflow is untimed and determinate
Limited expressiveness enables SDF to be
statically scheduled
2727
Thank You,Questions ?
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