Design of Disturbance Rejection Controllers for a Magnetic...

FPGA Implementation of Multiple Controllers for a Magnetic Suspension System

By: Chris OliveraAdvisors: Dr. Winfred Anakwa

& Dr. Yufeng LuBradley UniversityFebruary 27, 2014

Outline Of Presentation:

Summary

Goals

Functional Description

Block Diagram

Functional Requirements

Lab Work (Previous and New)

Project Schedule

Questions?

Summary

Purpose to implement previously designed multiple controllers

that used current and position feedback to suspend a metallic ball with an electromagnet on a FPGA board instead of a xPC Target Box or dSPACE board.

Why? to minimize costs!

xPC Target Box ~ $7,000

dSPACE ~ $12,000

FPGA Board ~Less than $1,000

Goals

To Implement Multiple Controllers for Rejection of Multiple Disturbances

Build Op-Amp Circuits to Shift Voltage Signals to FPGA Levels

Implement Controllers Using FPGA Board and Xilinx Software

Created and Tested In Simulink

FPGA Board Serving as Controller

Minimize Steady-State Error, Overshoot, and Settling Time

Functional Description

Method of Choice:

Internal Model Principle

Host PC using Simulink and Xilinx software

FPGA Board with Controllers

Magnetic Suspension System

Internal Model Principle

Developed by B.A. Francis & W.M. Wonham

Theory Controller is designed to include a model of the disturbance to be rejected while also

augmenting plant poles onto a desired transfer function. When disturbance is present in system, the model, having already accounted for it, rejects it and leaves the system output unchanged.

High-Level Functional Diagram

Magnetic Suspension System

Coil Driver BallElectromagnetic

Coil

Photo

SensorPosition Signal

Control Signal + Disturbance

Current Sensor

(1kΩ)Current Level (unused)

Control and Disturbance Drives Current

Current Induces Magnetic Field

Field Suspends Ball

Sensor Translates Location into Voltage

FPGA Board and Host PC

Using 0V~3.3V ADC and DAC in FPGA Board

Resolution = 32 bits

Download Controller, Upload Commands

Process Position Data and Passes Control

Block Diagram

Functional Requirements

Meet Specifications Tracking of Reference Waveforms

Percent Overshoot

Settling Time

Steady State Error

Input/output User selectable Sine, Square, Step Reference Waveforms

Set Point Ball Position

Software Functionality FPGA

Dunlap’s Previous Work

Using Classical Controller

7.67

1/961s +-12

Transfer Fcn1

7.67

1/961s +-12

Transfer Fcn

ste

To Workspace2

sin

To Workspace1Step3

Step1

Step

Sine Wavenum(z)

z -z2

Discrete

Transfer Fcn1

num(z)

z -z2

Discrete

Transfer Fcn

U + DER U

U + DER U

Dunlap’s Previous Work

Tested Classical Controller With Disturbance

Rejected Step Disturbance

0 0.5 1 1.5 2 2.5 30

0.05

0.1

0.15

0.2

0.25

0.3

0.35

.25 Input Reference

input w/.1sin(pi*t) disturbance

input w/ .1 unit-step disturbance

Completed Tasks

Utilize Internal Model Principle

Ramp and Step Disturbance

Automated Controller Design

Implement Controller In Simulink

Test Voltage Ranges of Previous Controllers

Lab Work

Tested Voltage Ranges of Multiple Controllers

dnlptutorialmag -3V – 3V

boline -2V – 2V

tutorialmag -3V – 3V

Desired Worst Case Range -3V – 3V

Dunlap’s Simulink Controller

Example of one Controller used

Transfer Function

Dis_Class_Num(s)

Dis_Class_Den(s)

Transfer Fcn4

Reference_Num(s)

Reference_Den(s)

Transfer Fcn3

Dis_Class_Num(s)

Dis_Class_Den(s)

Transfer Fcn2

Reference_Num(s)

Reference_Den(s)

Transfer Fcn1

7.67*.18

1/961s +-12

Transfer Fcn

Scope2

Target Scope

Id: 1

Scope (xPC)

MM-32

Diamond

Analog Output

1

MM-32 1

MM-32

Diamond

Analog Input

1

MM-32

Numd(z)

Dend(z)

Discrete

Transfer Fcn1

Numd(z)

Dend(z)

Discrete

Transfer Fcn

du/dt

Derivative4

du/dt

Derivative3

du/dt

Derivative2

du/dt

Derivative1

1

Constant3

1

Constant2

1

Constant1

1

Constant

ER

Y

D

Uc U

FPGA Implementation

FPGA Implementation

Subsystem

FPGA Implementation

Full Resolution FPGA (32 bits)

Simulink Results

Full Resolution FPGA

Converting to

FPGA Range

(slight difference)

Original

Using Xilinx

Project Schedule

2/27 – 3/13 Design, Build, and

Test Op-Amp Circuits

Generate VHDL code and Implement on FPGA Board

Demonstrate Working Magnetic Suspension System

3/14 – 3/24 Spring Break

3/25 – 5/14 Final Report

Final Presentation

Project Demo

Student Expo??

References

[1] B.A. Francis and W.M. Wonham, “The Internal Model Principle of

Control Theory,” Automatica. Vol. 12, pp 457-465, 1976.

[2] Jose A. Lopez and Winfred K.N. Anakwa, “Identification and

Control of a Magnetic Suspension System using Simulink and dSPACE

Tools”, Proceedings of the ASEE Illinois/Indiana 2003 Sectional

Conference, March 27, 2004, Peoria, Illinois, U.S.A.

[4] Jon Dunlap, “Design of Disturbance Rejection Controllers for a

Magnetic Suspension System”, Bradley University Department of

Electrical and Computer Engineering, May 8, 2006, Peoria, Illinois,

U.S.A

[4] Gary Boline and Andrew Michalets, “Magnetic Suspension System

Control Using Position and Current Feedback”, Bradley University

Department of Electrical and Computer Engineering, May 17, 2007,

Peoria, Illinois, U.S.A

Questions?