DIGITAL SYSTEMS Sequential Logic Design November 28, 2004 Rudolf Tracht and A.J. Han Vinck

DIGITAL SYSTEMS

Sequential Logic DesignNovember 28, 2004

Rudolf Tracht and A.J. Han Vinck

Types of logic: combinational

memoryless

combinationalcurrent input Output

Output depends on input only

Types of logic: sequential Mealy machine

Output depends on current input and memory content

current input Outputmemoryless

combinational

memory

For binary logic with n memory elements we have 2n states

The memory elements contain all the information about the past, necessary to account for the system‘s future behavior

Combinational

logic

memory content changes every T seconds

Not present for Moore machine

clock

Clock ( active high )

change state

timeclock

clock edge

Example: Clock frequency = periods/second = 1 MHz (Herz) clock period 1Sec

clock period T

clock frequency 1/T

T

Sequential:

– input A, B– wait for clock edge– observe C

– Input A, B– wait for another clock edge– observe C again: may be different

B

A

Clock

C

stability

• 2 examples

Propagation delay

Q

Q‘

Bistable circuit

01

10

Q 1

Q‘1

Use the freedom to fix output

R

S

Q

T

S R Q T

1 1 last Q last T

0 1 01

1 0 10

0 0 11

from SR = 00 to SR = 11 gives unpredictable next state

„state“

00 01 11 Q = 0

00 10 11 Q = 1

Key idea!

1. avoid SR = 00 as input

2. force SR = 11 if output must be fixed ( use C = 0 )

D

C

R

S

D C R S

0 1 1 0

1 1 0 1

0 0 1 1

1 0 1 1

Result is a sequential device: D-latch

• Used to „freeze“ information depending on control C

D

C

Q

Q‘

C D Q Q‘ D‘+C‘ D+C‘

1 0 0 1 1 0

1 1 1 0 0 1

0 x last Q last Q‘ 1 1

D‘+C‘

D+C‘

data input

control

Ideal Timing for a D-latch

D

C

Q

Follows D

Stores D

C D Q

1 0 0

1 1 1

0 x last Q

Latch is not clock controlled:= asynchronous

sequential device: Flip-Flop

• Flip-flop – output changes at times determined by

clock

clock controlled:= synchronous

Edge-triggered D Flip Flop

D D Qclk C

D

C‘

D CLK Q

0 0

1 1

X 0 last Q

X 1 last Q

C

C‘

QM

master slave

latch latch

Ideal timingIdeal timingQM fixed

Q=QM Q fixed

take over

Cont‘d

• The edge of the clock is used to sample the "D" input & send it to „Q“ (positive edge triggering).

– At all other times the output Q is independent of the input D

– The input must be stable for a short time before the clock edge.

C

C‘

Q output fixed

QM output fixed

No change in D

Q = QM

C‘QM QCD

master slaveC‘

Edge-triggered D Flip Flop

D D Qclk C

D

C‘

D CLK Q

0 0

1 1

X 0 last Q

X 1 last Q

D

CLK

QM

Q

QM

master slave

latch latch

Ideal timingIdeal timing

Cont‘d

• There are also

– Negative-edge triggered D flip flops

– Edge triggered J-K flip flops

J-K flip flop

J

K

D

clk

Q

clk

Edge triggered D and J-K flip flop

D CLK Q Q‘

0 0 1

1 1 0

X 0 last Q last Q‘

X 1 last Q last Q‘

J K CLK Q Q‘

0 1 0 1

1 0 1 0

X X 0 last Q last Q‘

X X 1 last Q last Q‘

0 0 last Q last Q‘

1 1 last Q‘ last Q

D J-K

Application D flip-flop: Shift registers (delay line)

• Serial in, serial out

• Serial in serial out

• Clock

• At each clock tick a new bit is shifted in. (This works only because every element has a certain delay and thus the input is taken before it changes))

• After n ticks the bit appears at the output, is thus a delay by n clock ticks

D Q D Q QD

D-flip-flop

Shift registers cont‘d

• Serial in, parallel out

• Serial in

• Clock

• At each clock tick a new bit is shifted in• Performs a serial to parallel conversion

D Q D Q QD

D-FF D-FF D-FF

Parallel in Serial out

parallel in

clock

sel sel sel sel

Serial out

FF FF FF FF

Parallel-in, parallel-out (2)

D

clkQ

clk

Load/shift

Serial-in

Q

D

Dclk

1-in

2-inFor serial operation

application

• Sampled speech: 8k samples/sec of 8 bit each– converted into serial stream of 64 kbit/s

• Computer serial output bus (e.g. RS-232)

0 1

data

Example

• unit delay: schematic representation

x(t) u(t) = x(t-1)

• exclusive OR

• parallel-to-serial convertor P/S

X(t-1)

R = ½ encoder

u1(t)

u1(t)

• For every input bit we generate 2 output bits

x(t-1) x(t-2)x(t)

clock

State transition graph (1)

1/1011

1/01 0/010/10

10 011/00

1/11 0/1100

0/00

Trellis representation (2)

00 00 00 00

00 00 00 00 0011 11 11 11

01 01 01

10 10 10 1001 01 01

11 11 1110 10

Transition tables (3)

input

0 1

Old state output new state output new state

00 00 00 11 10

01 11 00 00 10

10 10 01 01 11

11 01 01 10 11

General finite state machine

Specified by:

inputs

states

transitions between states

outputs connected to transitions

Analyzed by:

state transition graphs (Markov chains)

state transition tables

State minimization

Q: can we model with fewer states?

are there states that do the same job?

Definition:

two states are equivalent if and only if, for any input of length k, k > 0, they give rise to the same output.

Algorithm for minimizing the state table

Let S be the set of |S| states

Step 1: divide S into groups of states with the same outputs given the inputs. If |S| groups remain, STOP

Step 2:

subdivide every group into subgroups that contain all states that have their transitions to the same groups created in the

previous step

If no group is further subdivided, STOP

otherwise go to step 2.

STOP: uniquely label every remaining group (equivalence class)

exampleinput

0 1 0 1

old new

state state output

1 2 3 0 1

2 1 5 1 0

3 5 8 0 1

4 5 7 1 1

5 6 2 1 0

6 5 1 0 1

7 4 7 1 1

8 2 6 0 1

Step 1:

Group together states with same outputs

(1,3,6,8) (2,4,5,7)

Step 2: form subgroups

(1,3,6,8) (2,5) (4,7)

(1,3,6,8) (2,5) (4) (7)

(1,3,6,8) (2,5) (4) (7)

STOP:

4 Representants: 1, 2, 4, 7

General realization

Combinational circuit that realizes

Output = f(input, old state)

new state = h(input, old state)

N input

s

M outputs

D

D

D

r digits

new stater digits

old state

Sequence delay operator transform

a = a0 a1,..., ak,0,0,0,… A(X) = a0+a1X +...+ak Xk

Y(X) = A(X)*G(X)

A(X)

Application: shift register response with binary input and binary output.

G(X) = 1 + X + X2 , where X is called the delay operator

A(X)

XA(X) X2A(X)clock

G(X) *A(X)

1 a0 a1 ,..., ak

X a0 a1 ,..., ak

X2 a0 a1 ,..., ak-1 ak

1 a0 + a1 X + a2 X2 ,..., ak Xk

X a0 X + a1 X2 ,..., ak Xk+1

X2 a0 X2 + a1 X3 ,..., ak Xk+2

+

+

Periodic sequences

• For a periodic sequence:

A(X) = ( a0+a1X +...+ak-1 Xk-1 ) (1 + Xk + X2k + X3k + ... )

= ( a0+a1X +...+ak-1 Xk-1 ) / (1 – Xk )

• Note 1: (1 – Xk ) (1 + Xk + X2k + X3k + ... ) = 1

• Note 2: When we do calculations modulo-2, the – and + sign have the same effect.

Feedback shift register

• A binary linear feedback shift register 2 delay elements or flip-flops (we do not draw

the

clock anymore)

output

• Homework: – what is in general the maximum period of the output– Calculate the output sequence

XOR or modulo 2 calculations

1 0

Design

• Step 0: proper problem description• Step 1: construct

– state transition diagram– state transition table

• Step 2: choose flip-flop type for state memory• Step 3: derive logic equations from table for

• Next state• Output

Example: parity checker

• Problem: determine parity of 8-bits serially

• State diagram:

8 bits serial in Parity = 0 if even # of ones

out

Parity = 1 if odd # of ones

Parity checker

out = 0out=0 out=1

in=0 in=1 in=0

in=1

tables

in

0 1 0 1

old state new state output

Even Even Odd 0 1

Odd Odd Even 1 0

in

0 1 0 1

old state new state output

0 0 1 0 1

1 1 0 1 0Output = new

state

Next = out in

in outOld

clock

CRC-Application

Two standard polynomials called CRC-16 and CRC-CCITT are

• F(X) = 1 +X2 + X15 + X16 CRC-16• F(X) = 1 + X5 + X12 + X16 CRC-CCITT

The CRC calculates

X16A(X) modulo F(X) = subtract F(X) as often as possible from X16A(X),

where A(X) = a0 + a1 X2 + ••• + ak-1 Xk-1

( and coefficient calculations done modulo-2)

How do we implement this?

CRC-encoding

The CRC encoder calculates

{ X16A(X) }modulo F(X) = subtract F(X) as often as possible from X16A(X),

where A(X) = a0 + a1 X2 + ••• + ak-1 Xk-1

( and coefficient calculations done modulo-2)

•We transmit:

– C(X) = [{X16A(X)} modulo F(X) + X16A(X)] = : [ CRC(X) +X16 A(X) ]

Note:Note: C(X) modulo F(X) = 0!

In communication context

• We receive: C(X) E (X)

• We calculate: R(X) = {C(X) E (X)} modulo F(X)

– If R(X) = 0 no error (= assumption!)

– If R(X) 0 error detected

Note: all polynomials are binary and coefficient operations modulo-2

Theorem:

For F(X) of the form 1 + ••• + Xn-k

any error event of length ( n-k ) gives R(X) 0

CRC cont‘d

• The following „clocked“ shift register can be used to implement CRC16:

F(X) = 1 +X2 + X15 + X16

Data in

13 flip-flops

Example: X16 modulo F(X) = 1 + X2 + X15

Question: When is the result A(X) mod F(X) equal to 0?

What does this mean?

Cont‘d

• Example: calculate ( 1 +X2 +X4 +X5 ) modulo ( 1 +X + X3 )

– In binary: ( 1 0 1 0 1 1 ) modulo ( 1 1 0 1 )

The operations in binary are as follows

1 0 1 0 1 1 1 +X2 +X4 +X5

0 0 1 1 0 1 X2 ( 1 +X + X3 )1 0 0 1 1 00 1 1 0 1 0 X ( 1 +X + X3 )

1 1 1 1 0 0 1 1 0 1 0 0 ( 1 +X + X3 ) RESULT: 0 0 1 0 0 0 X2

Homework: draw the corresponding shift register

proof

for an error event length ( n-k ), E (X) has the form X*g(X),

where g(X) has degree < (n-k)

and thus E (X) cannot be a multiple of F(X). OK

Non-systemantic CRC

Encode: C(X) = A(X) F(X)

Receive: R(X) = C(X) E(X)

If R(X) modulo F(X) = 0 ( no error detected ! )

Decode: A‘(X) = R(X) / F(X)

Otherwise declare error

F(X) = 1 +X2 + X15 + X16

A(X)

13 flip-flops

A(X) F(X)

Examples of Polynomial * and /

Assume all coefficient calculations modulo-2 and no clock drawn

A(X) * G(X)

G(X) = ?

A(X)

A(X)

A(X) / F(X)

F(X) = ? Homework: check this

Homework: calculate the responses to A(X) = 1+X 2 +X 3. Can we combine G(X) and F(X) ?