Digital’Integrated’Circuits Invertercc.sjtu.edu.cn/upload/20150426201903867.pdfDigitalIC 4...

Digital ICIntroduction

Digital Integrated Circuits

InverterYuZhuo Fu

Digital IC 2

outline• CMOS at a glance• CMOS static behavior• CMOS dynamic behavior• Power, Energy, and Energy Delay• Perspective tech.

Digital IC 3

CMOS dynamic characteristic• CMOS capacitances mosaic• CMOS propagation delay• Optimizing inverter sizing

Digital IC 4

Circuit Under Design

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

This two-­inverter circuit will be manufactured in a twin-­well process.

Digital IC

CMOS Inverter: Transient Response

5

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

Digital IC6

CMOS capacitance mosaic• Wire capacitance• Junction(diffusion) capacitance• Gate capacitance

Most of them are nonlinear functions!

Digital IC 7

Computing the Capacitances

VDD VDD

Vin Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplifiedModel

Polysilicon

In OutMetal1

VDD

GND

PMOS

NMOS

1.2 mm=2l

Digital IC 8

Capacitance model

DS

G

B

CGDCGS

CSB CDBCGBDdiffDB

SdiffSB

GCBGB

GCDGDOGD

GCSGSOGS

CCCCCC

CCCCCC

=

=

=

+=

+=

Digital IC 9

The Miller Effect

Vin

M1

Cgd1Vout

DV

DV

Vin

M1

Vout DV

DV

2Cgd1

“A capacitor experiencing identical but oppositevoltage swings at both its terminals can bereplaced by a capacitor to ground, whose value istwo times the original value.”

Digital IC

Miller effect

10

Z

VAV

Z

VVI invinoutinin

−=

−=

vinvin

in

in

inin

A

Z

VAV

ZV

I

VZ

−=

−==

1

sCZ

1=

Mv

insCAsC

Z1

)1(

1=

−= )1( vM ACC −=

Vin Vout

Vin Vout

Z

Zin

Digital IC

Diffusion capacitances

Slide 11

( )mD

j

D

jj

V

C

dV

dQC

0Φ1

0

−==

0

)()(jeq

lowhigh

lowjhighj

D

jeq CK

VVVQVQ

VQ

C =−

−=

Δ

Δ=

( )

( )

( ) 0

-1

0

m0

-1

0

0

Φ1

Φ

Φ21

1

Φ2

j

m

D

m

D

DA

DAsiD

D

DA

DAsiDj

CVm

VNN

NNqA

m

VNN

NNqAQ

−−

=

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛

+−→

−⎟⎟⎠

⎞⎜⎜⎝

⎛

+=

ε

ε

m

DA

DAsiD

DA

DAsiDj

NN

NNqA

NN

NNqAC

-1

0

0

Φ2

Φ20

⎟⎟⎠

⎞⎜⎜⎝

⎛

+→

+=

ε

ε

[ ]mlowm

highlowhigh

m

eq VVmVV

K −− −Φ−−Φ−−

Φ−= 1

01

00 )()(

)1)((

Digital IC 12

Computing the Capacitances

Cox(fF/um2)

Co(fF/um)

Cj(fF/um2)

mj Φb(V)

Cjsw(fF/um)

mjsw Φbsw

(V)NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9

CDG0

CJ CJSW

W/L AD(um2) PD(um) AS(um2) PS(um)NMOS 3/2 19 15 19 15PMOS 9/2 45 19 45 19

NMOS and PMOS almost is same for unit capacitance

Digital IC

Computing the Capacitances

Slide 13

Polysilicon

InOutMetal1

VDD

GND

PMOS

NMOS

1.2 mm=2l

AD=4*4+3*1=16+3=19λ2PD=1+4+4+4+1+1=15λ

Digital IC

Computing the Capacitances• Vhigh=-­2.5V,Vlow=-­1.25V[NMOS,2.5V-­>1.25V HL]

• Bottom plate:Keqn(m=0.5,Φ0=0.9)=0.57• Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.61

• Vlow=0V,Vhigh=-­1.25V [NMOS,0V-­>1.25VLH]• Bottom plate:Keqn(m=0.5,Φ0=0.9)=0.79• Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.81

• Vhigh=-­1.25V,Vlow=0V [PMOS,2.5V-­>1.25VHL]• Bottom plate:Keqp(m=0.48,Φ0=0.9)=0.79• Sidewall:Keqwp(m=0.32,Φ0=0.9)=0.86

• Vhigh=-­2.5V,Vlow=-­1.25V [PMOS,0V-­>1.25VLH]• Bottom plate:Keqp(m=0.48,Φ0=0.9)=0.59• Sidewall:Keqwp(m=0.32,Φ0=0.9)=0.7

14

Digital IC 15

Computing the Capacitances

capacitor expression Value(fF)(H-­>L)

Value(fF)(L-­>H)

Cgd1 2CGD0n*Wn 0.23 0.23Cgd2 2CGD0p*Wp 0.61 0.61Cdb1 KeqnADnCJ+KeqwnPDnCJSW 0.66 0.90Cdb2 KeqnADnCJ+KeqwnPDnCJSW 1.5 1.15Cg3 (CGD0n+CGSOn)Wn+CoxWnLn 0.76 0.76Cg4 (CGD0p+CGSOp)Wp+CoxWpLp 2.28 2.28Cw 0.12 0.12CL 6.1 6.0

Digital ICIntroduction

Computing it more simple by estimation

Slide 16

Digital IC Slide 17

Effective Resistance• Shockley models have limited value

• Not accurate enough for modern transistors• Too complicated for much hand analysis

• Simplification: treat transistor as resistor• Replace Ids(Vds, Vgs) with effective resistance R• Ids = Vds/R

• R averaged across switching of digital gate• Too inaccurate to predict current at any given time

• But good enough to predict RC delay

Digital IC Slide 18

RC Delay Model• Use equivalent circuits for MOS transistors

• Ideal switch + capacitance and ON resistance• Unit nMOS has resistance R, capacitance C• Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width• Resistance inversely proportional to width

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k

Digital IC

Reason of 2R

Slide 19

)2

V-VV(

LW

k=I2DSAT

DSATGT'

DSAT

Digital IC Slide 20

RC Values• Capacitance

• C = Cg = Cs = Cd = 2 fF/mm of gate width• Values similar across many processes

• Resistance• R ≈ 6 KW*mm in 0.6um process• Improves with shorter channel lengths

• Unit transistors• May refer to minimum contacted device (4/2 l)• Or maybe 1 mm wide device• Doesn’t matter as long as you are consistent

Digital IC Slide 21

Inverter Delay Estimate• Estimate the delay of a fanout-­of-­1 inverter

2

1A

Y 2

1

Digital IC Slide 22

Inverter Delay Estimate• Estimate the delay of a fanout-­of-­1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

Y2

1

Digital IC Slide 23

Inverter Delay Estimate• Estimate the delay of a fanout-­of-­1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

Digital IC Slide 24

Inverter Delay Estimate• Estimate the delay of a fanout-­of-­1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

d = 6RC

Digital IC 25

CMOS dynamic characteristic• CMOS capacitances mosaic• CMOS propagation delay• Optimizing inverter sizing

Digital IC26

Propagation delay: first order analysis

• Propagation delay model of RC

2→/ 21

OHOLOLOH

VVvVVv +==

)2

()(

)9

71(

4

3≈)1(-

1

'

2

112

n

nn

n

DSATTDDDSATnnsat

DD

DSAT

DDv

v

eq

VVVVk

LWI

VI

V

VvvR

--

-IVdv

sat

=

+= ∫ λ

λ

Assuming transistor as saturation

Digital IC27

Propagation delay: first order analysis

• Propagation delay model of RC

L

DSATp

DDeqppLH C

I

VCRt )V-1(

4

3*69.0)2ln( DDλ==

L

DSATn

DDeqnpHL C

I

VCRt )V-1(

4

3*69.0)2ln( DDλ==

))/2-('**

1

)/2-('**

1(*52.0≈

*)11(**2/75.0*69.0

2*69.0

2

ppppp

pnnnn DSATGTDSATDSATGTDSAT

n

nDDL

Ldsatpdsatn

DD

LeqpeqnpLHpHL

p

VVVkLWVVVkL

WVC

CII

V

CRRtt

t

+

+=

+=

+=

Digital IC

Inverter Transient Response

-­0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

V out

(V)

t (sec) x 10-10

VDD=2.5V0.25µmW/Ln = 1.5W/Lp = 4.5Reqn= 13 kΩ (÷ 1.5)Reqp= 31 kΩ (÷ 4.5)

Digital IC

Inverter Transient Response

-­0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vin

V out

(V)

t (sec) x 10-10

VDD=2.5V0.25µmW/Ln = 1.5W/Lp = 4.5Reqn= 13 kΩ (÷ 1.5)Reqp= 31 kΩ (÷ 4.5)

tpHL = 36 psec

tpLH = 29 psec

So tp = 32.5 psec

tf trtpHL

tpLH

From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec

Digital IC

Inverter Propagation Delay, Revisited

To see how a designer can optimize the delay of agate have to expand the Req in the delay equation

11.52

2.53

3.54

4.55

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V)

t p(no

rmali

zed)

tpHL = 0.69 Reqn CL

= 0.69 (3/4 (CL VDD)/IDSATn )≈ 0.52 CL / (W/Ln k’n VDSATn )

Digital IC31

Design techniques for minimized propagation delay

• Reduce CL• Keep the drain diffusion areas as small as possible

• Increase the W/L ratio of the transistor• Increase Vdd

)1()(*52.0≈

'DDDSATnn

LpHL VVkL

WCtn

λ+

Digital IC

Design for Performance• Reduce CL

• internal diffusion capacitance of the gate itself• keep the drain diffusion as small as possible

• interconnect capacitance• fanout

• Increase VDD• can trade-­off energy for performance• increasing VDD above a certain level yields only very minimal improvements

• Increase W/L ratio of the transistor• the most powerful and effective performance optimization tool in the hands of the designer

• watch out for self-­loading! – when the intrinsic capacitance dominates the extrinsic load

Digital IC 33

Define NMOS-­to-­PMOS ratio

In order to create an inverter with a symmetrical propagate delaysAlso create symmetrical VTC β =2.4 which Rn=Rp!

nDSATnn

LneqLpHL VkL

WCRCt

')(2)2ln( ≈=

p

p

DSATpp

LeqLpLH VkL

WCRCt

')(2)2ln( ≈=

(W L)p(W L)n

=kn'VDSATn (VM −VTn −

VDSATn2

)

kp'VDSATp (VDD −VM +VTp +

VDSATp2

)

1)(

)('

'

===p

n

n

p

DSATpp

DSATnn

eq

eq

VkLW

VkLW

RR

γ

Digital IC 34

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10-11

t p(sec

)

tpLH tpHL

tp

Wp/Wn

Which point is optimal delay?

p

p

DSATpp

LeqLpLH VkL

WCRCt

')(2)2ln( ≈=

nDSATnn

LneqLpHL VkL

WCRCt

')(2)2ln( ≈=

Assume CL=C

Digital IC 35

Which point is optimal delay?

VDD VDD

Vin Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Interconnect

( ) ( )

n

p

wgdwggddL

LWLW

CCCCCCCCCnnpnpn

)()(

))(1(212211

=

+++=++++=

β

β

)1()))(1((345.0

))())(1((22ln

2

21

21

βγ

β

ββ

++++=

++++=+

=

nnn

p

nnn

eqwgd

eqeqwgd

pHLpLHp

RCCC

RRCCC

ttt

Digital IC 36

Which point is optimal delay?

This r is different from before! It is the resistor rate of the NMOS and PMOS

0=∂

∂

βpt

0)]1()))(1((345.0[

21

=∂

++++∂

ββγ

βnnn eqwgd RCCC

54.11331≈)1(

25.05.2

21

==+

+= =um

VVddgndn

w

CCC

γγβ

Digital IC 37

Summary of ratio

Beta=1.6, we have minimum delayBeta=2.4, we have equal delay tphl=tplhBeta=3.5, we have VM=Vdd/2

Digital IC 38

CMOS dynamic characteristic• CMOS capacitances mosaic• CMOS propagation delay• Optimizing inverter sizing

Digital IC

iref

extpp

irefextirefref

intextinteqextinteqp

SCCtt

SCCSCSRCCCRCCRt

00 69.069.0

)1)()((69.0

)1(69.0)(69.0

+=

+=

+=+=

39

Increasing inverter performance by sizing the NMOS and PMOS

Intrinsic delay is independent of the sizing of the gate

S>>0 will eliminate the impact of any external loadIf no load

If load

Digital IC 40

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10-11

S

t p(sec

)Device Sizing

(for fixed load)

Self-­loading effect:Intrinsic capacitancesdominate

Example 5.5

Digital IC 41

Inverter Chain

CL

If CL is given:-­ How many stages are needed to minimize the delay?-­ How to size the inverters?

In Out

Digital IC 42

Inverter Delayl Minimum length devices, L=0.25mm, Assume that for WP = 2WN =2W

l same pull-­up and pull-­down currentsl approx. equal resistances RN = RPl approx. equal rise tpLH and fall tpHL delays

l Analyze as an RC network

WNunit

Nunit

unit

PunitP RR

WWR

WWRR ==⎟⎟

⎠

⎞⎜⎜⎝

⎛≈⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−− 11

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):

2W

W

unitunit

gin CWWC 3=Load for the next stage:

Digital IC 43

Inverter with Load

Load (CL)

Delay

Assumptions: no load -­> zero delay

CL

tp = k RWCL

RW

RW

Wunit = 1k is a constant, equal to 0.69

Digital IC 44

Delay Formula

( )

( ) ( )γ/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

+=+=

+

Cint = rCginwith r ≈ 1f = CL/Cgin -­ effective fanoutR = Runit/W ;; Cint =WCunittp0 = 0.69RunitCunit

Digital IC 45

Apply to Inverter Chain

CL

In Out

1 2 Ntp = tp1 + tp2 + …+ tpN

⎟⎟⎠

⎞⎜⎜⎝

⎛+ +

jgin

jginunitunitpj C

CCRt

,

1,1~γ

LNgin

N

i jgin

jginp

N

jjpp CC

CC

ttt =⎟⎟⎠

⎞⎜⎜⎝

⎛+== +

=

+

=∑∑ 1,1 ,

1,0

1, ,1

γ

Digital IC

Optimal Tapering for Given Nl Delay equation has N -­ 1 unknowns, Cgin,2 – Cgin,N

l Minimize the delay, find N -­ 1 partial derivatives Result:

l Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-­1

l Size of each stage is the geometric mean of two

neighbors

46

1,1,, +−= jginjginjgin CCC

each stage has the same effective fanout (Cout/Cin)

each stage has the same delay

Digital IC 47

Optimum size for fixed Number of Stages

When each stage is sized by f and has same eff. fanout f:

Minimum path delay

Effective fanout of each stage:

1,/ ginLN CCFf ==

N Ff =

( )γ/10 Npp FNtt +=

Digital IC 48

Example

CL= 8 C1

In Out

C1 1 f f2

283 ==fCL/C1 has to be evenly distributed across N = 3 stages:

CL/C1 has to be evenly distributed across N = 4 stages:

?84 ==f

Digital IC 49

Optimum Number of Stages

For a given load, CL and given input capacitance Cin Find optimal sizing f

( ) ( )γγ

γ +=+= ftfFFNtt p

Npp 0

/10 ln

ln1/

0ln1lnln2

0 =−−

⋅=∂

∂

fffFt

ft pp γ

γ

fFNCfCFC in

NinL ln

ln with ==⋅=

( )fef γ+= 1

Digital IC 50

Optimum Effective Fanout f

Optimum f for given process defined by g( )fef γ+= 1

fopt = 3.6[4]for g=1

For r = 0, f = e, N = lnF

Digital IC 51

Impact of Self-­Loading on tp

1.0 3.0 5.0 7.0u

0.0

20.0

40.0

60.0

u/ln(u)

x=10

x=100

x=1000

x=10,000

No Self-­Loading, r=0 With Self-­Loading r=1

0

1

2

3

4

5

6

7

1 1.5 2 2.5 3 3.5 4 4.5 5

Digital IC 52

Normalized delay function of F

( ) Fln6.3=)6.3+1(Fln78.0=γ/F+1Nt=t N0pp

F unbuffered Two stages Inverter chain10 11 8.3 8.3100 101 22 16.61000 1001 65 24.910000 10001 202 33

Fln78.0=6.3lnFln

=flnFln

=N,F=f N

Digital IC 53

Buffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

Digital IC

More general example

Slide 54

1 2 3 CLoutin

( )γ/f+1Nt=t 0pp

3

3

3

L

2

3

1

2

3

L

2

3

1

2

1

L

3

L

2

3

1

2

164=f

f161

=CC

CC4

CC4

161

=CC

CC

CC

=CC

=F

f=CC

=CC4

=CC4

13

13

33

2

13

13L

3

C16=C16444*4

=fC4

=C

C44=C16464

=fC

=C

Digital IC

Input Signal Rise/Fall Time

• In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay.

3.6

3.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

0 2 4 6 8ts(sec)t p(

sec)

x 10-11

x 10-11

for a minimum-size inverter with a fan-out of a single gate

q tp increases linearly with increasing input slope ts, once ts > tp

q ts is due to the limited driving capability of the preceding gate

Digital IC

Design Challenge• A gate is never designed in isolation: its performance is affected by both the fan-­out and the driving strength of the gate(s) feeding its inputs.

(η ≈ 0.25)• Keep signal rise times smaller than or equal to the gate propagation delays• good for performance• good for power consumption

• Keeping rise and fall times of the signals small and of approx. equal values is one of the major challenges in high-­performance designs(slope engineering.)

1-iiistepstepptη+t=t

Digital IC

Rising-­fall time of the input signal

Slide 57

1-iiistepstepptη+t=t

Note: tp increases linearly with increasing input slope,once ts>tp(ts=0)

1 2 3 CLoutin

Digital ICSlide 58

Process Corners• Process corners describe worst case variations

• If a design works in all corners, it will probably work for any variation.

• Describe corner with four letters (T, F, S)• nMOS speed• pMOS speed• Voltage• Temperature

Digital ICSlide 59

Important Corners• Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time

Power

SubthreholdleakagePseudo-­nMOS

Digital IC15: Nonideal Transistors Slide 60

Important Corners• Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreholdleakage

F F F S

Pseudo-­nMOS S F ? ?