DUOS – Simple Dual TCAM Architecture for Routing Tables with Incremental Update

Author： Tania Mishra and Sartaj SahniPublisher： ISCC 2010Presenter： Wen-Tse LiangDate： 2010/09/29

IntroductionBackgroundDUOS schemeExperimental Results

The main drawback of using TCAMs in a router’s forwarding engine is that a TCAM consumes a high amount of power for each lookup operation since every TCAM cell in the array is activated for each lookup

Incremental update algorithms are complex because of the need to handle covering prefixes that may be replicated many times

In this paper we present our novel dual TCAM architecture, generally referred to as DOUS, along with advanced memory management schemes for performing efficient and consistent incremental updates without degrading lookup speed.

Shah and Gupta [23] describe incremental update algorithms for TCAMs using two different strategies, PLO_OPT and CAO_OPT ,to place prefixes in the TCAM.

Wang et al. [18] define a consistent rule table to be a rule table in which the rule matched (including the action associated with the rule) by a look up operation performed in the data plane is either the rule (including action) that would be matched just before or just after any ongoing update operation in the control plane.

Wang and Tzeng [16] also propose a consistent TCAM scheme. Their scheme, MIPS, use leaf pushing to transform the prefixes in the routing table into a set of independent prefixes, which are then stored in a TCAM (in any order). Their consistent update scheme, however, delays data plane lookups that match TCAM slots whose next hop information is being updated.

Each TCAM has two ports, which can be used to simultaneously access the TCAM from the control plane and the data plane.

Each TCAM entry/slot is tagged with a valid bit, that is set to 1 if the content for the entry is

valid, and to 0 otherwise. A TCAM lookup engages only those slots whose valid

bit is 1. The TCAM slots engaged in a lookup are determined

at the start of a lookup to be those slots whose valid bits are 1 at that time.

Changing a valid bit from 1 to 0 during a data plane lookup does not disengage that slot from the ongoing lookup.

Similarly, changing a valid bit from 0 to 1 during a data plane lookup does not engage that slot until the next lookup.

We assume the availability of the function waitWriteValidate() which writes to a TCAM slot and sets the valid bit to 1. In case the TCAM slot being written to is the subject of ongoing data plane lookup, the write is delayed till this lookup completes. During the write, the TCAM slot being written to is excluded from data plane lookups1.

Similarly, we assume the availability of the function invalidateWaitWrite() ,which sets the valid bit of a TCAM slot to 0 and then writes an address to the associated SRAM word in such a way that the outcome of the ongoing lookup is unaffected.

The basic idea of these algorithms is to maintain the trie node properties of prefixes stored in LTCAM and ITCAM.

That prefixes in LTCAM and ITCAM must be present in the leaf and intermediate nodes of the trie, respectively.

DUOS.Insert()

DUOS.Delete()

DUOS.Change()

ITCAM Algorithm

Move Algorithm

LTCAM Algorithm

Scheme 1 ( PLO_OPT )

Scheme 2 ( DFS_PLO ) (Distributed Free Space with Prefix Length Ordering Constraint).

Scheme 3 ( DLFS_PLO ) (Distributed and Linked Free Space with Prefix Length Ordering Constraint).

Scheme 4 ( CAO_OPT )

# of invocations of move() # of waitWrites/(#Inserts +

#Deletes)

# of waitWrites/(#Inserts + #Deletes)

# of enabled entries for every TCAM search