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Calibrating Achievable DesignCalibrating Achievable Design
Andrew B. KahngAndrew B. Kahng
GSRC Executive ReviewGSRC Executive Review
9/19/029/19/02
Theme Members: Wayne Dai, Tsu-Jae King, Wojciech Theme Members: Wayne Dai, Tsu-Jae King, Wojciech Maly, Igor Markov, Herman Schmit, Dennis SylvesterMaly, Igor Markov, Herman Schmit, Dennis Sylvester
9/19/02 2
OutlineOutline
The Problem: Design The Problem: Design TechnologyTechnology Productivity Productivity
The Value Proposition: Focus x TTM x QOR x Impact x …The Value Proposition: Focus x TTM x QOR x Impact x …
Specific Projects: Accomplishments and PlansSpecific Projects: Accomplishments and Plans
Collaboration and RoadmapCollaboration and Roadmap
9/19/02 3
Problem: Design Problem: Design TechnologyTechnology Productivity Gap Productivity Gap
ITRS-2001: “Cost of design is the greatest threat to the ITRS-2001: “Cost of design is the greatest threat to the
semiconductor roadmap”semiconductor roadmap”
interoperability, design quality and cost metrics, design process optimizationinteroperability, design quality and cost metrics, design process optimization
Design Productivity Gap = Design Design Productivity Gap = Design TechnologyTechnology Productivity Gap Productivity Gap
This Theme: improve Design Technology Productivity by providing This Theme: improve Design Technology Productivity by providing
open, shared infrastructures that change how we open, shared infrastructures that change how we specifyspecify, , developdevelop, ,
and and measuremeasure andand improveimprove Design Technology Design Technology Address both design complexity Address both design complexity and design technology complexityand design technology complexity
Synergy: {Correct R&D focus} x {Faster TTM} x {Validated QOR improvement}Synergy: {Correct R&D focus} x {Faster TTM} x {Validated QOR improvement}
Living Roadmap: Shared “red bricks” to optimize SEMI R&D investmentLiving Roadmap: Shared “red bricks” to optimize SEMI R&D investment
New cultures: open-source publication, CAD-IP reuse, METRICS benchmarkingNew cultures: open-source publication, CAD-IP reuse, METRICS benchmarking
9/19/02 4
Calibrating Achievable Design (C.A.D.) ThemeCalibrating Achievable Design (C.A.D.) Theme GTX / Living Roadmap: Where to Focus?GTX / Living Roadmap: Where to Focus?
What is the benefit of low-k?What is the benefit of low-k? Achievable global signaling quality?Achievable global signaling quality? Optimal memory integration and architecture?Optimal memory integration and architecture? http://vlsicad.ucsd.edu/GTX
CAD-IP Reuse: Faster and Better R&DCAD-IP Reuse: Faster and Better R&D Industry-compatible, open-source, back-end flowsIndustry-compatible, open-source, back-end flows
http://vlsicad.eecs.umich.edu/BK Remote execution “autograding” infrastructureRemote execution “autograding” infrastructure (VLSI design education, common data model, …)(VLSI design education, common data model, …)
METRICS: Measure & ImproveMETRICS: Measure & Improve Design metrics, design project metricsDesign metrics, design project metrics Clock speed, front-end acceptance, tool noise, … Clock speed, front-end acceptance, tool noise, … Deployed in industryDeployed in industry http://vlsicad.ucsd.edu/METRICS
9/19/02 5
The Value PropositionThe Value Proposition
Not Business As UsualNot Business As Usual
Design (Technology) Productivity Gap is Design (Technology) Productivity Gap is thethe critical challenge critical challenge
Launch FRC-scale initiatives that impact entire community, industryLaunch FRC-scale initiatives that impact entire community, industry Culture changes: publication standards and evaluation methodologies, Culture changes: publication standards and evaluation methodologies,
creation of reusable CAD-IP, open-source, self-consistent roadmapping, … creation of reusable CAD-IP, open-source, self-consistent roadmapping, … Living Roadmap and proactive involvement within ITRS community: ORTCs, Living Roadmap and proactive involvement within ITRS community: ORTCs,
System Drivers, analyses of “shared red bricks”, …System Drivers, analyses of “shared red bricks”, … Bookshelf: 30 slots, 100+ entries, 1000’s of downloads, clear impact across Bookshelf: 30 slots, 100+ entries, 1000’s of downloads, clear impact across
academic literature (DAC, ICCAD, ISPD, IWLS, …), in industry (Capo source is academic literature (DAC, ICCAD, ISPD, IWLS, …), in industry (Capo source is free and open; actively used at > 10 companies)free and open; actively used at > 10 companies)
METRICS: integrated into commercial iCadence platform, used at TI, 20+ METRICS: integrated into commercial iCadence platform, used at TI, 20+ attendees at DAC-2002 BOF meetingattendees at DAC-2002 BOF meeting
Next: Education, Cost-Driven Design, …Next: Education, Cost-Driven Design, …
9/19/02 6
Specific Projects (1)Specific Projects (1)
GSRC Technology Extrapolation (GTX)
“Living Roadmap”
9/19/02 7
Progress in Technology ExtrapolationProgress in Technology Extrapolation ““Living ITRS”Living ITRS”
ITRS-2001 (December 2001): consistency of power, die size, density, ITRS-2001 (December 2001): consistency of power, die size, density, performance parameters, spanning PIDS, A&P, Test, Design, ORTCsperformance parameters, spanning PIDS, A&P, Test, Design, ORTCs
GTX distribution on SEMATECH website (linked to ITRS-2001)GTX distribution on SEMATECH website (linked to ITRS-2001) Integrated with other models (SUSPENS, BACPAC, …)Integrated with other models (SUSPENS, BACPAC, …)Mantra: “Shared Red Bricks” (synergy among SEMI R&D programs)Mantra: “Shared Red Bricks” (synergy among SEMI R&D programs)
New understanding of key axes in achievable design envelopeNew understanding of key axes in achievable design envelopeCost-driven integration and packaging (UCSC)Cost-driven integration and packaging (UCSC) Interconnect (Michigan, UCB, UCSD, UCSC)Interconnect (Michigan, UCB, UCSD, UCSC)Variability (Michigan, UCSD)Variability (Michigan, UCSD)Power (via PED Theme, UCB, Michigan)Power (via PED Theme, UCB, Michigan)
9/19/02 8
Cost-Driven Integration and Packaging Cost-Driven Integration and Packaging (UCSC)(UCSC)
Area-IO advantagesArea-IO advantages Preserves on-chip electrical environment in Preserves on-chip electrical environment in
the SIP contextthe SIP context
Minimizes size of ESD protection device for Minimizes size of ESD protection device for intra-package IO’sintra-package IO’s
Improved signal integrity due to power and Improved signal integrity due to power and ground pad structureground pad structure
Testbed: Single-Package ComputerTestbed: Single-Package Computer Integrated CPU, North Bridge, graphics chip, Integrated CPU, North Bridge, graphics chip,
DDR SDRAMDDR SDRAM
Balance: core logic, memory access speedsBalance: core logic, memory access speeds
Other issues: rerouting wirelength, IO Other issues: rerouting wirelength, IO performance, thermal performance, performance, thermal performance, costcost, …, …
Conventional IO
Area-IO
Logic&Buffer
PAD
PAD
ESDProtection
Circuit
Logic&Buffer
9/19/02 9
Chip-Laminate-Chip Memory Integration Chip-Laminate-Chip Memory Integration
Attractive CLC electrical characteristicsAttractive CLC electrical characteristics Maximum off-chip delay << IO buffer delay (3.5ns)Maximum off-chip delay << IO buffer delay (3.5ns) Signal round trip time < rise time (500ps)Signal round trip time < rise time (500ps) Inter-chip skew < board skew (500ps)Inter-chip skew < board skew (500ps) No terminating resistors requiredNo terminating resistors required Smaller IO buffer size and minimized ESD protectionSmaller IO buffer size and minimized ESD protection
LaminateLogic
Area-IO DRAM
Decoupling C
Chip-Laminate-Chip (CLC) architecture
Source: SyChip Inc.
BGA ball
( 3.34M Tr., 570 Area-IO )6.80 mm
3.8
5 m
m
Achievable envelope = ?Achievable envelope = ? Routability of IO redistribution?Routability of IO redistribution? Optimal power-ground structure on Optimal power-ground structure on
laminate?laminate? Optimal clock structure on laminate?Optimal clock structure on laminate? Model of junction temperature in SIP?Model of junction temperature in SIP? Cost?Cost?
Design calibrationDesign calibration Configurable Area-IO SRAMConfigurable Area-IO SRAM
9/19/02 10
Multi-GHz On-Chip Interconnects (UCB)Multi-GHz On-Chip Interconnects (UCB) Loop-based model for fully-shielded global clock structure*Loop-based model for fully-shielded global clock structure*
Highly efficient extraction of loop RLC valuesHighly efficient extraction of loop RLC values
Models verified with full-wave simulation and measurement data Models verified with full-wave simulation and measurement data
Available in GTXAvailable in GTX
Closed-form interconnect performance model**Closed-form interconnect performance model** Driver delay and rise timeDriver delay and rise time
Interconnect delay, rise time and overshootInterconnect delay, rise time and overshoot
Available in GTXAvailable in GTX
Design Optimization***Design Optimization*** Design guidelines for best interconnect structure for optimal delay and power Design guidelines for best interconnect structure for optimal delay and power
UCB, 2002
* Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, and Tsu-Jae King, "Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design", Custom Integrated Circuits Conference (CICC), pp. 19-22, 2002
** Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu-Jae King, and Chenming Hu, "Analytical Performance Models for RLC Interconnects and Application to Clock Optimization", to be presented at International ASIC-SoC conference, September 2002, Rochester, USA.
*** submitted to JSSC
9/19/02 11
Active Shields (Michigan)Active Shields (Michigan)
Repeater, shielding paradigms Repeater, shielding paradigms entrenched in high-perf flowentrenched in high-perf flow Seek complementary “drop-in” Seek complementary “drop-in”
techniques that improve delay, slope, techniques that improve delay, slope, power, noise immunitypower, noise immunity
ActivelyActively use use shields to minimize shields to minimize capacitance or inductancecapacitance or inductance Switch shields to improve signal Switch shields to improve signal
propagation and/or noise immunitypropagation and/or noise immunity For RC lines, switch shields in phase For RC lines, switch shields in phase
with signal net to reduce effective with signal net to reduce effective coupling cap, delaycoupling cap, delay
For inductive lines, switch shields in For inductive lines, switch shields in opposite phase with signal net to opposite phase with signal net to produce better return path, reduce produce better return path, reduce loop inductanceloop inductance
9/19/02 12
RC RC Wire ResultsWire Results
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
Del
ay /
Slo
pe
(norm
aliz
ed to fat
wire)
Wire Thickness (t) (m)
Delay (Active shields) Delay (Passive shields) Fat wire (Delay and slope) Slope (Active shields) Slope (Passive shields)
Active shields resulted in reduced transition times (~25% reduction over fat wire) and reduced delays
Active shields result in increased power compared to passive shields
Noise immunity degraded slightly with active shields due to driver resistance
Optimal delay/slope vs. wire thickness for copper wire of length 7.5mm
9/19/02 13
Interconnect Architecture Metrics, Optimization (UCSD)Interconnect Architecture Metrics, Optimization (UCSD) Example motivation: “Is low k worth it?”Example motivation: “Is low k worth it?”
New New interconnect architecture metricinterconnect architecture metric allows quantified comparison of allows quantified comparison of
design, process, and materials technology improvementsdesign, process, and materials technology improvements Sensitive to entire interconnect stack, repeater area budget, design wirelength Sensitive to entire interconnect stack, repeater area budget, design wirelength
distribution, clock frequency, per-connection delay targets, …distribution, clock frequency, per-connection delay targets, …
TSMC 90nm node: Improving Miller coupling factor by 38% (better design, shielding) equivalent to 40% improvement in k
9/19/02 14
Specific Projects (2)Specific Projects (2)
CAD-IP Reuse via The GSRC Bookshelf
Pervasive Automation via bookshelf.exe
9/19/02 15
Previous Mindset: CAD-IP ReusePrevious Mindset: CAD-IP Reuse
CAD-IP Reuse: One of three original initiatives in CAD ThemeCAD-IP Reuse: One of three original initiatives in CAD Theme ““Trivial idea” Trivial idea” GSRC Bookshelf GSRC Bookshelf
Reuse helps, but is not a panaceaReuse helps, but is not a panacea Consider: Moore’s Law + Design Productivity Crisis Consider: Moore’s Law + Design Productivity Crisis
required asymptotics of computational and design effortrequired asymptotics of computational and design effort Near-linear memory: design hierarchy, coarse viewsNear-linear memory: design hierarchy, coarse views Near-linear runtime: fast global optimization heuristicsNear-linear runtime: fast global optimization heuristics Near-linear design effortNear-linear design effort: auto-installation, all-pairs benchmarking, : auto-installation, all-pairs benchmarking,
design flow health monitoringdesign flow health monitoring Near-linear learning curveNear-linear learning curve: “autograders”, open-source: “autograders”, open-source
CAD-IP Reuse is one asymptotic requirementCAD-IP Reuse is one asymptotic requirement
9/19/02 16
The VLSI CAD BookshelfThe VLSI CAD Bookshelf
GSRC-provided service that supports near-linear scaling of complexity in GSRC-provided service that supports near-linear scaling of complexity in EDA (= a repository)EDA (= a repository)
Growing popularity is seen from downloads and contributionsGrowing popularity is seen from downloads and contributions Algorithm descriptions and analyses; open-source CAD toolsAlgorithm descriptions and analyses; open-source CAD tools Open design benchmarks and algorithm comparisonsOpen design benchmarks and algorithm comparisons Currently 30 slots, 100+ entries: Currently 30 slots, 100+ entries: Verilog ToolsVerilog Tools through through Clock Skew SchedulingClock Skew Scheduling
Described in IEEE Design and TestDescribed in IEEE Design and Test, May/June 2002, May/June 2002 Growing adoption within academic literature, review processGrowing adoption within academic literature, review process
ISPD 2002 papers from UCLA, UCSD, Michigan ISPD 2002 papers from UCLA, UCSD, Michigan DAC 2002 papers from Michigan and UICDAC 2002 papers from Michigan and UIC ICCAD 2002 papers from IBM, UCSB and MichiganICCAD 2002 papers from IBM, UCSB and Michigan Ongoing work at CMU, UCSD, Minnesota, etc.Ongoing work at CMU, UCSD, Minnesota, etc.
Many fresh Ph.D.s in CAD are now familiar with the BookshelfMany fresh Ph.D.s in CAD are now familiar with the Bookshelf
9/19/02 17
Industry Usage of the GSRC BookshelfIndustry Usage of the GSRC Bookshelf Common denominator in discussions with academiaCommon denominator in discussions with academia IntelIntel (Santa Clara) and (Santa Clara) and IBMIBM (Austin and T.J. Watson) (Austin and T.J. Watson)
Downloaded and compiled several tools from the BookshelfDownloaded and compiled several tools from the Bookshelf Wrote parsers/converters (~2 weeks of time), distributed internallyWrote parsers/converters (~2 weeks of time), distributed internally Compared to internal tools on internal benchmarks Compared to internal tools on internal benchmarks
“results on par or better” “results on par or better” Tools in use for comparisons and algorithm design experimentsTools in use for comparisons and algorithm design experiments
Cadence Design SystemsCadence Design Systems (San Jose and NJ) (San Jose and NJ) Downloaded and compiled several tools from the Bookshelf Downloaded and compiled several tools from the Bookshelf In some cases (where LEF/DEF was not available) wrote convertersIn some cases (where LEF/DEF was not available) wrote converters Used for prototyping and evaluation of new commercial toolsUsed for prototyping and evaluation of new commercial tools
Other companiesOther companies Prototyping design flows before full-blown tools are readyPrototyping design flows before full-blown tools are ready
Many repeated downloads, but little technical feedbackMany repeated downloads, but little technical feedback (no feedback or (no feedback or fee required by our license)fee required by our license)
9/19/02 18
Academic Usage of the GSRC BookshelfAcademic Usage of the GSRC Bookshelf
New floorplanning methodology for pipelined array designs New floorplanning methodology for pipelined array designs developed at developed at CMUCMU, based on “wire path length” metric, based on “wire path length” metric
Bookshelf usageBookshelf usage ““Classic” = Bookshelf Block FloorplannerClassic” = Bookshelf Block Floorplanner ““Classic+LSP” and “New” methods built on same Bookshelf codeClassic+LSP” and “New” methods built on same Bookshelf code
Discovery: new floorplanning methodology yields faster and Discovery: new floorplanning methodology yields faster and smaller pipelined designssmaller pipelined designsLess area wasted on hold time fixing than in unfloorplanned designsLess area wasted on hold time fixing than in unfloorplanned designs
Many substantial contributions back into the BookshelfMany substantial contributions back into the BookshelfSoftware: New modifications to existing Bookshelf componentSoftware: New modifications to existing Bookshelf componentApplications (LEF/DEF): 1-D DCT, 2-D DCT, 1-Round IDEA encryptionApplications (LEF/DEF): 1-D DCT, 2-D DCT, 1-Round IDEA encryptionLikely future additions: AES, FFT, Low-Density Parity Check, …Likely future additions: AES, FFT, Low-Density Parity Check, …
9/19/02 19
One-Round IDEA Encryption BenchmarkOne-Round IDEA Encryption Benchmark
Floorplan
Dead Space
WPL Speed Initial P&R Util.
Final P&R Util.
No Floor X X 2.02 82.3% 98.1%
Classic 3.34% 7.82 2.13 61.8% 68.7%
Classic + LSP 4.00% 7.51 2.08 65.4% 72.9%
New 2.56% 4.27 2.02 89.4% 97.8%
Hold area used to fix hold-time violations: 9.5% (No Floor) vs. 1.8% (New)Hold area used to fix hold-time violations: 9.5% (No Floor) vs. 1.8% (New)
9/19/02 20
New Mindset: On-Demand, Pervasive AutomationNew Mindset: On-Demand, Pervasive Automation
Another “trivial” idea: Automate Another “trivial” idea: Automate allall design activities design activities that cost time/$$$that cost time/$$$
Bottom-up: “intelligent” solversBottom-up: “intelligent” solversTop-down: goal-driven, platform-based methodologiesTop-down: goal-driven, platform-based methodologiesSideways: “intelligent” VLSI design environmentSideways: “intelligent” VLSI design environment
““We automate what you do” (if we can understand it We automate what you do” (if we can understand it ))Fundamental techniques for automation (e.g., OO-based design Fundamental techniques for automation (e.g., OO-based design
patterns for EDA)patterns for EDA)Generic, reusable, high-performance SW and HW components Generic, reusable, high-performance SW and HW components
(e.g., Capo, PipeRench)(e.g., Capo, PipeRench)Common practices and methodologies for automationCommon practices and methodologies for automation
9/19/02 21
““We Automate What You Do”We Automate What You Do”
Goal: Reconfigurable and robust Goal: Reconfigurable and robust design flows design flows modular implementation platformsmodular implementation platforms language support for rapid flow prototypinglanguage support for rapid flow prototyping Web-based script composers for design flowsWeb-based script composers for design flows file-system support for distributed flowsfile-system support for distributed flows design flow health monitoringdesign flow health monitoring automatic extraction of statistically significant resultsautomatic extraction of statistically significant results
Additional motivationsAdditional motivations Related research: Related research: PUNCHPUNCH from Purdue, from Purdue, SatExSatEx from CNRS/U. Paris-Sud (France), from CNRS/U. Paris-Sud (France),
NEOSNEOS from Argonne National Lab, from Argonne National Lab, PBSPBS from NASA, from NASA, OmniFlowOmniFlow from NCSU/CBL from NCSU/CBL Benchmarking and regression testingBenchmarking and regression testing Experience in education: Experience in education: auto-graders auto-graders (large-scale infrastructure for evaluation)(large-scale infrastructure for evaluation) Experience with infrastructure for collaborative research (based on the Bookshelf )Experience with infrastructure for collaborative research (based on the Bookshelf )
9/19/02 22
bookshelf.exebookshelf.exe Best existing featuresBest existing features
Reporting style of SatExReporting style of SatEx Versatility of PUNCHVersatility of PUNCH Scalability of NEOSScalability of NEOS Control as in OmniFlowControl as in OmniFlow
New featuresNew features MIME-like data typesMIME-like data types Flow scriptingFlow scripting Automatic submission of binaries and source codeAutomatic submission of binaries and source code
Scalable: distributed computation, automated maintenanceScalable: distributed computation, automated maintenance ““Adapts to users”Adapts to users”
Multiple levels of expertise, commitment Multiple levels of expertise, commitment Sharing of public data, protection of proprietary dataSharing of public data, protection of proprietary data ““Screen-saver” grid computation mode, cf. SETI@Home, Entropia, etc.Screen-saver” grid computation mode, cf. SETI@Home, Entropia, etc.
9/19/02 23
Usage and Data ModelsUsage and Data Models
Consistent data models needed for serious flows, experimental researchConsistent data models needed for serious flows, experimental research E.g., integrated RTL-to-layout implementation, industry interoperabilityE.g., integrated RTL-to-layout implementation, industry interoperability
Plan to use Plan to use OpenAccess 2.0OpenAccess 2.0 (spec available 2Q02, source expected 1Q03) (spec available 2Q02, source expected 1Q03)
Adjustments expected within Bookshelf for open-source / industry SP&R flowsAdjustments expected within Bookshelf for open-source / industry SP&R flows
Infrastructure proposal (IBM/Cadence, Infrastructure proposal (IBM/Cadence, IWLS02): Study netlist changes IWLS02): Study netlist changes for improved routing congestionfor improved routing congestionIWLS benchmark APIIWLS benchmark API
Interface to Bookshelf formatsInterface to Bookshelf formats
Layout generation (in Bookshelf)Layout generation (in Bookshelf)
Placement (several in Bookshelf)Placement (several in Bookshelf)
Congestion maps (in Bookshelf)Congestion maps (in Bookshelf)
9/19/02 25
METRICS ArchitectureMETRICS Architecture
WebServer
DataminingInterface
Servlet
SQLTables
SQL results
Tables
requestresults
DB
Metrics Data Warehouse
DataMining
Reporting
Tables
Inter/Intra-net
JavaApplets
Flow Wrapper Transmitter
wrapper
T1 Tool Tool
TransmitterAPI
XML
T2 T3
9/19/02 26
Recent ProgressRecent Progress
DAC-2002 Birds-of-a-Feather MeetingDAC-2002 Birds-of-a-Feather Meeting20 attendees (18 from industry, including HP, IBM, Intel, Motorola)20 attendees (18 from industry, including HP, IBM, Intel, Motorola)
Industry adoption:Industry adoption:Cadence Design SystemsCadence Design Systems
METRICS integrated into Block-Based Design Methodology for Front-End METRICS integrated into Block-Based Design Methodology for Front-End Acceptance, Clock Planning and flow quality tracking Acceptance, Clock Planning and flow quality tracking
Used within iCadence (web-based design flow)Used within iCadence (web-based design flow)
Texas InstrumentsTexas Instruments METRICS used for flow/design quality trackingMETRICS used for flow/design quality tracking
9/19/02 27
Front End AcceptanceFront End Acceptance
Chip AssemblyChip Assembly
Block DesignBlock Design
Chip Design Planning
Ver
ifica
tion
Customer Data ValidationCustomer Data Validation
Design Feasibility AssessmentDesign Feasibility Assessment
Project Planning and Design BudgetingProject Planning and Design Budgeting
Floor plan & Estimation
Bus TimingTest AMS PowerClock
Design Input
Block Design
Block-Based Design is a patented technology by Cadence Design Systems, Inc.
Block-Based Design (BBD) MethodologyBlock-Based Design (BBD) Methodology
9/19/02 28
1. Create IP clock reference library– store historical information on previous IP
2. Define basic clock speed– find master clock frequency that satisfies
constraints for all blocks
3. Generate clock budgets– determine target gate count and target freq.
to drive synthesis:
– define insertion delays and skews from DB
4. Determine clock structures, variants– balanced buffered, grid, unbuffered H
5. Verify clock structures– timing correctness– adjust clock frequency, padding, PLL taps, …
Buffered Tree
Grid
H-tree
Loading
Del
ay
Clock Planning MethodologyClock Planning Methodology
Ref: K. Venkatramani, S. Mantik and R. Adhikary, “A Predictive and Analytical Clock Planning Methodology for Hierarchical Block Based Design”, DATE-2002
Block Block
No.No.
Size Size
(mm)(mm)
Clock Clock
LoadsLoads
Delay Delay
(ns)(ns)
Skew Skew
(ns)(ns)
# Pipeline # Pipeline
StagesStages
# Regs# Regs
11 1.51.5 99 0.30.3 0.030.03 22 3030
22 33 2727 1.21.2 0.120.12 33 200200
33 66 243243 9.69.6 0.970.97 55 14001400
Blk Blk
NoNo
Min Min
HzHz
Max Max
HzHz
Ideal Ideal
HzHz
Aux Aux
HzHz
nn New New
MasterMaster
New New
AuxAux
Master Master
MarginMargin
11 55 100100 5757 114114 22 66.6766.67 133133 117%117%
22 55 7575 4343 8686 22 66.6766.67 133133 155%155%
33 1010 6868 3939 7878 22 66.6766.67 133133 171%171%
44 2020 140140 8585 44 133.3133.3 157%157%
55 6060 150150 103103 44 133.3133.3 129%129%
66 6060 200200 143143 66 200200 140%140%
freqfreq
freqfreqgatecntgatecnt
gatecntgatecnt
minmax
mintarget minmax
mintarget
Blk Blk
No.No.
TypeType Clock Clock
LoadsLoads
Size Size
(mm)(mm)
Delay Delay
(ns)(ns)
DiffDiff DecisionDecision
11 SoftSoft 2222 1.31.3 0.2510.251 -0.67-0.67 PadPad
22 SoftSoft 9797 3.33.3 0.910.91 -0.01-0.01 GoodGood
33 SoftSoft 243243 4.34.3 1.4251.425 0.5030.503 FasterFaster
44 HardHard N/AN/A N/AN/A 1.21.2 0.2770.277 Early TapEarly Tap
55 HardHard N/AN/A N/AN/A 0.750.75 -0.17-0.17 PadPad
66 HardHard N/AN/A N/AN/A 11 0.0770.077 Early TapEarly Tap
9/19/02 29
Front End Acceptance (FEA) FlowFront End Acceptance (FEA) Flow• FEA preparation
– data gathering, classification and certification
• Customer data validation– project checklist (docs, specs,
testbenches, models, etc.)– data completeness (readability,
execution readiness, etc.)– simulations (block interconnect, chip-
level functional model)– primary block selection– project directory structure
• Design feasibility assessment– analysis of proposed design to
determine acceptance risks– assess key project parameters (cost,
area, performance, power)• Project planning and design budgeting
– Project schedule, human/machine resources, cost/expense, etc.
Customer Data & Specifications
Customer Data Validation
Design Feasibility Assessment
MeetRequirements?
Renegotiate Specification or
Terminate Project
Project Planning and Design Budgeting
Design and Project Data
To Chip Planning and Block Design
No
Yes
FEA Preparation
Ref: K. Venkatramani and S. Mantik, “Managing Risk in Block Based Designs: A Front End Acceptance Methodology”, EDP-2002
9/19/02 30
METRICS Impact at CadenceMETRICS Impact at Cadence
Clock Planning and Front-End AcceptanceClock Planning and Front-End Acceptance METRICS used as design data (IP) repositoryMETRICS used as design data (IP) repository
Clock planning applied to a wireless modem design consisting of Clock planning applied to a wireless modem design consisting of 8 main IP blocks (total of 1M cells) achieves 54MHz speed on 8 main IP blocks (total of 1M cells) achieves 54MHz speed on ARM architectureARM architecture
FEA achieves more accurate coarse-grain assessment, reducing FEA achieves more accurate coarse-grain assessment, reducing design risk without sacrificing design timedesign risk without sacrificing design time
Flow quality trackingFlow quality tracking METRICS keeps track of design quality and timing in a web-METRICS keeps track of design quality and timing in a web-
based SP&R flow for timing convergencebased SP&R flow for timing convergence
9/19/02 31
C.A.D. Theme DeliverablesC.A.D. Theme Deliverables
Most C.A.D. Theme research is available as Most C.A.D. Theme research is available as open sourceopen source Integrated as GTX modelsIntegrated as GTX models
Research at UCSC, UCB, CMU, Michigan all captured and interoperableResearch at UCSC, UCB, CMU, Michigan all captured and interoperable GTX is also available with the ITRS-2001 release (SEMATECH website)GTX is also available with the ITRS-2001 release (SEMATECH website)
Released in the GSRC BookshelfReleased in the GSRC Bookshelf Many point optimization codes; CMU libraries and reference designsMany point optimization codes; CMU libraries and reference designs
Released in the METRICS systemReleased in the METRICS system
Our open source is Our open source is really openreally open source source MIT license; can be used for ANY purpose (many positive MIT license; can be used for ANY purpose (many positive
comments from major companies such as Intel, IBM)comments from major companies such as Intel, IBM)
60+ publications also posted on GSRC website60+ publications also posted on GSRC website
9/19/02 32
Identified challenges
and issues inUDSM design
Exploredpotential
methodologysolutions
DevelopedConcept ofPlatform-
Based Design(PBD)
Select Design Drivers:•Ambient intelligence
•In-home networks•Radar-on-a-chip
Formulatedvalidation
problem forPBD
Developed andpublished
taxonomy for PBD
Explored and developedunderlying tools and
methodologies
Develop and integrateassociated tools and
methodologies (capture,synthesis, optimization,
verification, test)
Develop prototypeplatforms (architecture,
implementation) thatmeet design driver
needs
Identify missingcomponents /
emerging challenges(mixed signal,
reliability)
Refine and transfermethodology
Joint project betweenthemes to develop
prototypeimplementation
Develop solutionsfor emerging
problems
Jan 1999 Today Jan 2003 Jan 2004 Jan 2005
SRC (?)&
Sponsors
Collaborate with C2S2 FCRP
Roadmap and CollaborationRoadmap and Collaboration
GTX + Living ITRS: What is the design problem?
GTX + Living ITRS: What is the design problem?
Bookshelf, METRICS and bookshelf.exe (design process opt)
Bookshelf, METRICS and bookshelf.exe
Bookshelf, METRICS
bookshelf.exe (auto-flow opt)
Interfaces to other FRCs: GTX + Living ITRS, Cost modeling Other interfaces to SRC and Sponsors:
Education, Living ITRS “Shared Red Bricks”
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