DVClub Sept 14 Updated Presentation v2 - T&VS · Performance Verification Nick Heaton, Cadence...

Performance Verification

Nick Heaton, Cadence Design SystemsDVClub Sept 8th 2014November 14 2014

• Challenges of performance verification– ARMv8 Mobile CPU Subsystem Example

• UVM Testbench Requirements

Agenda

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• Performance Characterization

ARM® ARMv8-A Mobile Example CPU Subsystem

Cortex®-A57 Cortex®-A53

MailTM-T760GPU

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ARM® ARMv8-A Mobile Example CPU Subsystem Performance Challenges

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What is the latency of the processor clusters

to memory paths including all async

bridges ?

ARM® ARMv8-A Mobile Example CPU Subsystem Performance Challenges

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What is the latency of the processor clusters to memory

paths including all async bridges ?

What is the bandwidth of the paths from IP with high bandwidth

demands to memory ?

ARM® ARMv8-A Mobile Example CPU Subsystem Performance Challenges

What is the bandwidth and latency of the paths from real-time IP to

memory ?

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ARM® ARMv8-A Mobile Example CPU Subsystem Performance Challenges

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How do I ensure adequate performance when ALL critical IPs

are active ?

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Characterization TestsRouting Model

UVMTestbench

UVM TestbenchPerformance Characterization

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• Systematic Approach– Take each path (from Master IP to Memory) in turn and do analysis for

– maxBandwidth– Fully saturating traffic – Read, Write and Read/Write transactions– Different burst lengths 1,2,4,8,16 beats (based on full bus width)

– minLatency

ARM® ARMv8-A Mobile Example SoCPerformance Characterization Requirements

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– minLatency– Single outstanding transaction– Read, Write transactions– Different burst lengths 1,2,4,8,16 beats (based on full bus width)

– Outstanding Transaction Sweep– Constant traffic– Read and Write transactions– Sweep outstanding transaction levels from 1 to maxOT for each interface

ARM® ARMv8-A Mobile Example SoCPerformance Characterization Analysis - maxBandwidth

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ARM® ARMv8-A Mobile Example SoCPerformance Characterization Analysis – minLatency

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Interconnect WorkbenchAssembly

UVM Testbench

IP-specificTraffic Profiles

CoreLink 400 System IP

RTL & IP-XACT

Interconnect WorkbenchAnalysis &

Debug

PerformanceAnalyzer

PerformanceCharacterization

Tests

Automate Simulate Analyze

Cadence VIP Cadence VIP Library for AMBA®

UserMeta-Data

SoC PerformanceTestbench

Cadence Interconnect Workbench

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PerformanceMeasurements

PerformanceAnalysis

VerificationClosure

For Interconnect IP Integration•Performance of use case traffic loads•Verify configuration functionalityFor SoC Integration•Validate performance in context of IPs

Benefits� Shorten performance tuning and analysis iteration loop from

days to hours� Reduce testbench development time from weeks to hours

Tune Architecture

Generated Testbench Flow

SoC VerificationTestbench

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Synthesized Traffic WorkloadsRouting Model

UVMTestbench

UVM TestbenchWorkload Analysis – for QoS refinement

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DUT

• Significant challenges in predicting and optimizing SoC performance– Multiplicity of IP configuration options particularly in Interconnect and DDR space– Need a systematic approach which has the potential to be automated

• Performance verification accomplished in three steps– Characterization – fully automated and can be checked as a standard regressions step

Summary

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– Characterization – fully automated and can be checked as a standard regressions step– Architectural – Establish QoS functions as expected– Use-case – hunt for corner case issues

• Cadence Interconnect Workbench supports all stages of the process– Automation of testbench, supports ARM Corelink System IP– Automation of the characterization test suite– Comprehensive analysis and checking capabilities– Traffic Synthesizers for architectural and use-case analysis