View
219
Download
0
Category
Preview:
Citation preview
1
ECE 425
Timer
2
Timer Functions
• Two main modes:– Input capture• Used for timing external events
– Match (Output compare)• Allows use as a simple function generator
• Runs off PCLK or a scaled down version.– PCLK is CCLK * 1, ½ or ¼ – 32-bit prescale register allows long periods
3
Timing Terminology
4
Timer Overview
• Two independent timers• 32 bit counters– 4 channels per counter
• Can generate interrupts on timeout/match• Programmable for edge sensitivity– Rising edge, falling edge, any edge
5
Timer in a Nutshell
• Set up time base.– Derivative of system clock
• Input capture: See how many timer cycles elapse between events or just count the number of events.
• Match (output compare): every N cycles toggle, set or clear an output.– Can change N every time to make eccentric
waveforms of arbitrary complexity.
6
Timer Registers
• 17 per timer– Control registers: enables, set frequency, set mode– Check & clear interrupts– Capture values for timing measurements– Counters: prescale & time base
• Lots of choices, lots of complexity
7
Timer Control Register
• Only two bits used.• Bit 0: time base and prescale counters enable. Set
to 1 to enable. Off (Logic 0) is default.– Both are enabled/disabled with this bit. No individual
control.• Bit 1: reset. Set to 1 to synchronously clear both
counters.• Addresses: – Timer 0: 0xE000_4004– Timer 1: 0xE000_8004
8
Count Control Register
• Selects Timer or Counter mode– Timer mode: increment time base counter every PCLK
or scaled PCLK rising edge.– Counter mode: timer counter is incremented on the
specified edge of a Capture input pin.• When in counter mode, selects which input pin
will trigger the action.• Addresses:– Timer 0: 0xE000_4070– Timer 1: 0xE000_8070
9
Counter Control RegisterBits 1:0 Description
00 Timer Mode. Increment on clock rising edge
01 Counter mode, increment on input rising edge
10 Counter mode, increment on input falling edge
11 Counter mode, increment on any input edge
Input edge? That’s next.
10
Counter Control Registers
Bits 3:2
Description
00 Input source is CAP0
01 Input source is CAP1
10 Input source is CAP2
11 Input source is CAP3
CCR bits 7:4 are reserved and currently unused. Should always be left at 0.
11
CAP Triggers and Their Pins
• CAP0.0 (3 pins) : P0.2, P0.22 and P0.30• CAP0.1 (1 pin) : P0.4• CAP0.2 (3 pin) : P0.6, P0.16 and P0.28• CAP0.3 (1 pin) : P0.29• CAP1.0 (1 pin) : P0.10• CAP1.1 (1 pin) : P0.11• CAP1.2 (2 pins) : P0.17 and P0.19• CAP1.3 (2 pins) : P0.18 and P0.21
12
CAP0-3
• Each Timer has four possible input sources, CAP0-3.• Each of the sources is associated with one or more pins.
– Pins have multiple duties. Being able to select one of several pins for Capture triggers will simplify board/system design.
– Selection is done via Pin Connect Block.• When more than one pin is selected for a Capture input
on a single channel, the pin with the lowest Port number wins.– Example: if pins 30 (P0.6) and 46 (P0.16) are selected for
CAP0.2, only pin 30 will be used by TIMER0 to perform CAP0.2 function.
13
Timer Counter
• The heart of the timer system: a 32-bit counter.
• Incremented according to the value set in the prescale register. Increments every (Prescale + 1) PCLK cycles.– It that is zero, increments every PCLK rising edge
• Rolls over at terminal count (0xFFFF_FFFF).– Roll over does not generate an interrupt or have
any particular significance.
14
Timer Counter
• Suppose you want to know how many times the counter has rolled over?– Necessary for measuring events with long periods
• Just set one of the match registers to generate an interrupt every time it does go to 0.
• Timer Counter Addresses:– Timer 0: 0xE000_4008– Timer 1: 0xE000_8008
15
Prescale Register
• Set the maximum value for the Prescale Counter.– 32-bit register, range is 0 – 0xFFFF_FFFF
• When set to 0, Timer will run off PCLK with no scaling.– Anything else, timer will be scaled.
• Addresses:– Timer 0: 0xE000_400C– Timer 1: 0xE000_800C
16
Prescale Counter
• 32-bit counter.• Runs off PCLK.• Increments every PCLK cycle up to the point
where it matches what was set in the Prescale Register.– When it hits, it returns to 0 on the next cycle
• Addresses:– Timer 0: 0xE000_4010– Timer 1: 0xE000_8010
17
Comparators
Bit-by-bit XOR followed by NOR reduction. Output is 1 iff all bits are equal.
A0B0
A1B1
A2B2
A3B3
18
Match Registers
• 4 32-bit match registers per timer. • When one matches counter value, something
can be triggered.• Options are– Generate an interrupt– Reset the timer– Stop the timer– Some combination of the above
19
Match Register Addresses
Timer 0• MR0: 0xE000_4018• MR1: 0xE000_401C• MR2: 0xE000_4020• MR3: 0xE000_4024
Timer 1• MR0: 0xE000_8018• MR1: 0xE000_801C• MR2: 0xE000_8020• MR3: 0xE000_8024
Procedure: Write a value to one of the registers. Enable one or more of the match functions via the match control registers. When the timer matches a match register, the enabled function will trigger.
20
Match Control Registers
• Three bits per Match register• Enable/disable– Interrupt on match– Stop on match– Return to zero on match
• Addresses:– Timer 0: 0xE000_4014– Timer 1: 0xE000_8014
21
Match Control BitsBit Function Bit Function
0 Interrupt 0 Enable 6 Interrupt 2 Enable1 Reset 0 Enable 7 Reset 2 Enable2 Stop 0 Enable 8 Stop 2 Enable3 Interrupt 1 Enable 9 Interrupt 3 Enable4 Reset 1 Enable 10 Reset 3 Enable5 Stop 1 Enable 11 Stop 3 Enable
For all functions, Logic 1 is enabled, Logic 0 is disabled.Only bits 11:0 are defined. All the rest are reserved and should always be left at 0.
22
Capture Registers
• Captures timer value when the specified event occurs.
• Event is programmed into Capture Control Registers– Events are edges on specified pins.
• Elapsed time is calculated in program by subtracting 1st from 2nd.– Implied: must store first somewhere else.
• Must check for rollover to get valid difference.
23
Capture Register Addresses
Timer 0• CAP0: 0xE000_402C• CAP1: 0xE000_4030• CAP2: 0xE000_4034• CAP3: 0xE000_4038
Timer 1• CAP0: 0xE000_802C• CAP1: 0xE000_8030• CAP2: 0xE000_8034• CAP3: 0xE000_8038
Procedure: set one or more control registers to trigger on a specified edge. When the event occurs, store the timer value in a CAP register. Save the captured value in memory or another register. Wait for the next event. When that happens, subtract (adjusting for rollover, if it occurred) the second from the first, yielding the elapsed time in PCLK cycles.
24
Capture Control Registers
• Three bits per Capture Register• Options are:– Capture on rising edge– Capture on falling edge– Enable interrupt– Any combination of the above
• Addresses:– Timer 0: 0xE000_4028– Timer 1: 0xE000_8028
25
Capture Control BitsBit Function Bit Function
0 Capture R0 on rising edge 6 Capture R2 on rising edge1 Capture R0 on falling edge 7 Capture R2 on falling edge2 Enable interrupt on R0
event8 Enable interrupt on R2
event3 Capture R1 on rising edge 9 Capture R3 on rising edge4 Capture R1 on falling edge 10 Capture R3 on falling edge5 Enable interrupt on R1
event11 Enable interrupt on R3
event
For all bits, logic 1 means enabled and logic 0, disabled. Only bits 11:0 are defined. All the rest are reserved and should always be left at 0.
26
External Match
• We’ve already seen how match works.• But that is internal to the silicon.• To use it as a signal generator, need to get
those transitions to the outside world.• That’s done through External Match.• Four per timer, some can be connected to
more than one pin.
27
External Match Functions
• Each match (4 per timer) can cause an associated output pin to:– Do nothing– Go to logic 0 (no effect if already 0)– Go to logic 1 (no effect if already 1)– Toggle– Pins must previously have been set to output (all
default to input) and associated with match via Pin Control Block.
28
External Match Functions
Value Function00 Do Nothing01 Clear10 Set11 Toggle
29
External Match Register
• Four bits per timer reflecting match output as set in control bits. Will show pin output whether or not pins have been associated with the match.– It’s a R/W register but these four bits should be
considered read only• Eight bits setting action– Two bits per channel– Ignore, set, clear, toggle– These eight bits are for you to set.
30
External Match Register
Bit Function Bits Function0 Match 0 output 5:4 Match 0 control1 Match 1 output 7:6 Match 1 control2 Match 2 output 9:8 Match 2 control3 Match 3 output 11:10 Match 3 control
Only 12 bits are defined. The rest should always be left at zeros.
Addresses: Timer 0: 0xE000_4014, Timer 1: 0xE000_8014
31
Interrupt Register
• Four bits for match interrupts• Four bits for capture interrupts• After one is set, it can be cleared by writing a
one to the same bit.– Toggle logic– Writing zeros has no effect
• Addresses:– Timer 0: 0xE000_4000– Timer 1: 0xE000_8000
32
Interrupt RegisterBit Function0 Match channel 01 Match channel 12 Match channel 23 Match channel 34 Capture channel 05 Capture channel 16 Capture channel 27 Capture channel 3
33
Timer Interrupt
• VIC only has one interrupt per timer.– Timer 0: bit 4 of VICSoftInt register, 0xFFFF_F018– Timer 1: bit 5 of same register
• If more than one timer interrupt is possible, the timer ISR must read the timer interrupt register to determine which one fired.
• Clear interrupt in VIC (toggle logic again) as well as timer interrupt register.– ISR must do both to re-enable interrupt.
34
That’s All
• 17 x 2 registers.• Need to initialize them to use timer
subsystem.• Defaults are all off.
35
Timer Operation: Interrupt & Reset
36
Timer Operation: Interrupt & Stop
37
Timer System (1st Half)
38
Timer System (2nd Half)
39
Timer Applications
• What’s the timer good for?• Timing things.• Like a race.• How about a marathon?
40
Marathon Timer Requirements
• Accuracy: say 1/100 of a second.• Time: track checkpoints every ¼ mile.• Make it long enough for the 400 lb. Sumo
wrestler.– 10 hours or so without aliasing.
41
Where Do We Start?
• It will be an ARM core, same peripheral units as we’ve been discussing.
• What functions will we need?• Is it a Match function?• How about input capture?• What registers need initialization?
42
Processor Clock
• Could choose anything, but let’s stick with the lab machines: 60 MHz internal clock.
• How many clock ticks does 1/100 of a second take?– 600,000, which is 927C0h
• And 10 hours?– 36,000 seconds, 6x107 cycles per second
2.16x1012
43
Clock Choice
• Only need to measure to 1/100 of a second. 600,000 cycles per measurement seems excessive.
• 2x1012 is a pretty big number even for a 32 bit machine.– FFFF_FFFF is about 4.3 x 10 9, so there would be lots of
roll overs.– Nothing wrong with that, we can handle it, but it’s an
unnecessary complication.• Maybe we can do something to make the timer
better match the task.
44
Clock Scaling
• We can scale the PCLK by up to 4, then scale the timer clock by up to 232.
• What would be a good number?– Only need two clock ticks per 1/100 of a second.– Get max. power savings by dividing CCLK by 4.
• As it happens, that’s the default: 00 to VPBDIV register
– Then divide 15 MHz PCLK by something to count at around 200 Hz.• 75,000: something like that can be stored in the timer’s
Prescale Register.
45
Timer Setup
• Counter Control Register Mode (bits 1:0)– Default is timer mode, no need to do anything
• Counter Control Register source (bits 3:2)– May as well use the default here too, if we are
only going to time one runner.• How about the Match registers? What do we
need to do with them?– Nothing. They are used for setting outputs and
have nothing to do when timing external events.
46
More Things To Set Up
• Capture control registers: need to set something there. All are off by default.– Assume we’ll just use one channel.– They’re all the same. Pick one arbitrarily.– Pick an edge. Rising or falling, matters not, but
usually rising is used.• Both would be a bad idea.
– Enable interrupt. Could theoretically make it work by polling, but this is what interrupts are for.
47
Timer Register Write Summary
• Assumption: using Timer 0, Channel 0• 00 VPBDIV (0xE01F_C100)• 75,000 Timer Prescale Register
(0xE000_400C)• 0000 Timer Controller Register (0xE000_4070)– Timer mode, channel 0, increment on rising edges
• 4 Capture Control Register (0xE000_4028)– Enable channel 0 interrupt
48
Timer ISR
• After enabling the timer, all the action will be in the ISR.
• What does it need to do?– Homework X: write a task list and then organize it
into a flow chart for the marathon timer ISR. Include any necessary initialization, which may need to be done before the interrupt is enabled.
Output Compare Application
• Two tone siren.• Set fast (1200 Hz) wave on an output pin.• Wait half a second.• Set slow (300 Hz) wave on the pin.• Wait half a second.• Repeat.
49
Values for 1200 Hz
• Want a 1200 Hz signal square wave for the siren.• Suppose PCLK is 15 MHz.• 15,000,000/1200/2= 6250, easily fits into a 32 bit
register. No need to scale PCLK.• Read Timer Counter, add 6250 & store, wait for match.
– Alternate program: reset counter, only compare to 6250. • Advantage: no repeated adds in ISR• Disadvantage: no freerunning counter, can’t be used for other
functions simultaneously
• Upon match, toggle output and repeat.
50
A Few More Pieces
• Would need a half-second timer to determine when to switch frequencies.– Maybe RTC: Interrupt when half a second has
elapsed. Repeat forever.– Every half second, need to switch counts, from
1200 to 300 Hz.• 300 Hz count: 1.5x107 / 300 / 2 = 25000• Same algorithm as before, whichever was chosen.
51
52
Register Initialization
• Use timer 1, channel 2 (arbitrary choice).• 00 VPBDIV (0xE01F_C100)– 15 MHz PCLK
• 00 Timer Control Register (0xE000 8004)– Enabled and not cleared, which is the default
• Count Control Register (0xE000 8070)– Timer mode, increments on PCLK rising edge
• 00 Prescale Register (0xE000 800C)– Don’t use prescale for now
53
More Register Initialization
• 20h Match Control register (0xE000_8014)– Trigger interrupt on match
• 10h VICSoftInt (0xFFFF_F018)– Enable interrupt
• 300h External Match Register (0xE000_803C)– Toggle on match
54
RTC
• Real Time Clock may be used, but…– It has no provision for interrupting at less than 1
second intervals.• Is this a fatal flaw?– Not really.• Run it twice as fast, so what it thinks is one second is
really only half a second.• Change the spec. Switch frequencies once per second
instead of twice.• Use another match channel instead of RTC.
55
½ Second Switch
• Can we easily use a second interrupt for the switch?• 15 MHz PCLK: need to switch every 7.5 million
cycles.• 7.5x106 = 7270E0h
– Having a 32 bit machine can be advantageous. This would have been much more complicated with an HC12.
• So we can easily load another channel with 7.5 million and have two tasks running concurrently.
56
More Homework
• Initialize registers to do the ½ second switch without interfering with the siren frequencies.
• Outline the ISRs for both.– Does not need to be done in assembly language.
Match Siren Circuit
57
LPC214x3.3uFPin
If the speaker is low enough power it could work. An amplifier likely would be needed. Capacitor is sized to work with input impedance of speaker (typically eight Ohms), passing frequencies of interest (300 to 1200 Hz) while blocking DC.
Recommended