ECE 4773 - Team 3A Senior Capstone Lab Fall 2006 SUBSEA BLOW-OUT PREVENTER (BOP) CONTROL MODULE

ECE 4773 - ECE 4773 - Team 3ATeam 3A

Senior Capstone LabSenior Capstone Lab Fall 2006 Fall 2006

SUBSEA BLOW-OUT SUBSEA BLOW-OUT PREVENTER (BOP) PREVENTER (BOP) CONTROL MODULECONTROL MODULE

Team 3aName: Rob Warren

Position: Project Manager

Team 3aName: Mark Shook

Position: Configuration Manager

Team 3aName: Robert Fenton

Position: Correspondent Officer

Team 3aName: Duy Nguyen

Position: Financial Officer

HYDRIL PRESSURE HYDRIL PRESSURE CONTROLCONTROL

SurfaceSurface Foreman ControlForeman Control Central ProcessingCentral Processing

Sub-SeaSub-Sea Annular BOPsAnnular BOPs Ram BOPsRam BOPs Control SystemsControl Systems

RequirementsRequirements

List of Critical Product List of Critical Product RequirementsRequirements Operate in pressures up to 6700 psi.Operate in pressures up to 6700 psi. Operate two solenoidsOperate two solenoids Monitor ram position (LVDT 0-10V)Monitor ram position (LVDT 0-10V) Calculate flow count (5- 100 GPM) via flow Calculate flow count (5- 100 GPM) via flow

metermeter Communication to external host Communication to external host Capable of testing internal componentsCapable of testing internal components ModularModular

OBJECTIVEOBJECTIVE

RELIABLERELIABLE

SUBMERSIBLESUBMERSIBLE

SCALABLESCALABLE

DESIGN PARADIGMDESIGN PARADIGM

Communications (TCP/IP)Communications (TCP/IP) Host to Sub-Sea UnitHost to Sub-Sea Unit

Fiber OpticsFiber Optics Sub-Sea IntranetSub-Sea Intranet

Ethernet (802.3)Ethernet (802.3)

DESIGN PARADIGMDESIGN PARADIGM

LogicLogic Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)

RedundantRedundant ReliableReliable ProgrammableProgrammable

DESIGN PARADIGMDESIGN PARADIGM

Sensor InterfaceSensor Interface Flow MeterFlow Meter Ram Position SensorRam Position Sensor

Solenoid InterfaceSolenoid Interface Modified H-bridgeModified H-bridge

Dual DirectionDual Direction Solenoid TestSolenoid Test H-bridge TestH-bridge Test

Host

Power Interface(Solenoid)

Main Logic(FPGA)

Self Test

A/D converterFlow Meter

Solenoids

LVDT

HARDWARE SYSTEMHARDWARE SYSTEM

SOFTWARE SYSTEMSOFTWARE SYSTEM

COMMUNICATIONS

LOGIC CORE

LOGIC CORE

LOGIC CORE

BUFFER BUFFER BUFFER

MAJORITYVOTER

SOLENOID

NET IFACENET IFACE

SOLENOID

SOFTWARE SYSTEMSOFTWARE SYSTEM

COMMUNICATIONS

LOGIC CORE

LOGIC CORE

LOGIC CORE

BUFFER BUFFER BUFFER

NET IFACENET IFACE

FLOWMETER

ADC ADC ADC

SOFTWARE SYSTEMSOFTWARE SYSTEM

COMMUNICATIONS

LOGIC CORE

LOGIC CORE

LOGIC CORE

BUFFER BUFFER BUFFER

NET IFACENET IFACE

LVDT

ADC ADC ADC

Cond-itioning

EthernetController

Microblaze Processor

Solenoid Control

Solenoid Control

Clocks

ATD

PowerSolenoid- 60VLVDT -10VH-Bridge- 60VFPGA- 3.2VMini module- 2.5VA/D converter 3.3V

MechanicalExternal pressure (6700 psi)Size

InputsLVDTFlowmeter

Network/(802.3)

OutputsSolenoid (1)

(2 leads)

Solenoid (2)(2 leads)

Network/(802.3)

Power to sensors

Functional Block DiagramFunctional Block Diagram

Solenoid ControllerSolenoid Controller

Solenoid 1

CPU Isolation

Solenoid 2

High-VoltageController

IsolatedSensor

IsolatedSensor

TIMELINETIMELINE

Critical PointsCritical Points Critical Design Review (CDR)Critical Design Review (CDR) Initial AssemblyInitial Assembly Test Requirement Document (TRD)Test Requirement Document (TRD) Final AssemblyFinal Assembly TestingTesting Project Completion DateProject Completion Date

Critical Design Review Oct. 16

Parts Arrive- Initial Assembly Oct. 23

TRD Nov. 3

Final Assembly Nov. 10

Testing Nov. 13

Project Completion Dec. 01

WORK BREAKDOWN WORK BREAKDOWN STRUCTURESTRUCTUREJob List |MemberJob List |Member Rob WRob W Mark SMark S Robert FRobert F Duy NDuy N

Communication Protocol Communication Protocol DevelopmentDevelopment

XX XX

Research Power Research Power RequirementsRequirements

XX

Determine I/O SpecificationsDetermine I/O Specifications XX

Locate Suitable ComponentsLocate Suitable Components XX XX XX

Develop Redundant SystemsDevelop Redundant Systems XX XX XX

Hardware DiagrammingHardware Diagramming XX XX

Software DiagrammingSoftware Diagramming XX XX

Schematics Schematics XX XX

Prototyping Prototyping XX XX

Hardware Troubleshooting Hardware Troubleshooting XX XX

Final Assembly Final Assembly XX XX

Programming Programming XX XX XX

Software Debugging Software Debugging XX XX XX

Test Procedure Development Test Procedure Development XX XX

Product Testing/QAProduct Testing/QA XX XX

COST OF MATERIALS COST OF MATERIALS ORDEREDORDERED

Item Part Number (Mfg. Part #) Supplier Website Qty PPU Total

FPGA Board DS-KIT-3S400MM1 em.avnet.com 1 $195.00 $195.00

FPGA Board w/Base DS-KIT-3S400MM1-BASE em.avnet.com 1 $375.00 $375.00

A2D Converter AD7705BNZ digikey.com 3 $8.33 $24.99

Dual H-Bridge NJM2670D2 digikey.com 5 $4.83 $24.15

2mm 2x32 Headers TMM-132-01-S-D digikey.com 6 $7.52 $45.12

Opto-Isolators HCPL-2530 digikey.com 6 $2.10 $12.60

Copper Plate Board PC53-ND digikey.com 2 $15.11 $30.22

Total $707.08

Labor Hours AnalysisLabor Hours Analysis

Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Cum

Bud 0 18 31 11 6 18 21 27 25 23 21 20 20 0 0 0 241 Estimate at Complete

Act 0 13 20 10.5 9.5 13 19 23 22 20 17 17 24 57 93 0 358 Actual to date

Delta 0 5 11 0.5 -3.5 5 2 4 3 3 4 3 -4 -57 -93 0 149% Percent Expended

Weeks 1- 12 were slightly over allocated Weeks 1- 12 were slightly over allocated Weeks 13-15 were under allocatedWeeks 13-15 were under allocated Overall Estimate at completion was Overall Estimate at completion was

under budgetedunder budgeted

Key features/Performance Key features/Performance highlightshighlights

Web user interfaceWeb user interface Ability to fire both solenoidsAbility to fire both solenoids Ease of interconnectivity/scalabilityEase of interconnectivity/scalability Able to test the H-Bridge and Able to test the H-Bridge and

solenoid coil with a trickle current.solenoid coil with a trickle current.

Tests Via TRDTests Via TRD Feature TestingFeature Testing

Send each software command from the host to Send each software command from the host to the module and verify appropriate action / the module and verify appropriate action / responseresponse

Redundancy Testing Redundancy Testing Disconnect both solenoids, instigate solenoid Disconnect both solenoids, instigate solenoid

testing, and verify system failure reporttesting, and verify system failure report Individually disconnect each A/D converter, Individually disconnect each A/D converter,

instigate a position measurement and verify instigate a position measurement and verify individual system failure report (non-compliant individual system failure report (non-compliant subsystem)subsystem)

Power off 60V power supply, instigate solenoid Power off 60V power supply, instigate solenoid controller test, and verify system failure reportcontroller test, and verify system failure report

Control ModuleControl Module

FPGA Board & BaseFPGA Board & Base

Solenoid Control/Test Solenoid Control/Test ModuleModule

RecommendationsRecommendations

Communication ImprovementsCommunication Improvements The Field Programmable Gate Array (FPGA) is using a Microblaze processor core which is running a sample webserver software package for Ethernet communication. This is a very limited server application and should be improved to allow for greater reliability and versatility. Currently the only means for accessing status information through the control module is by using any standard web browser. This can be very useful, though we recommend when improving the server software concurrently creating a host communication program. This program which would run on any PC or even server class machine could communicate with the control unit on a separate port than the web browser. This would allow for faster more data oriented communications, facilitating improved testing and allowing easier and more frequent collection of sub-sea data such as equipment operability status

RecommendationsRecommendations

Redundancy Redundancy The proposed design called for a highly redundant control unit, using three independent logic cores. These were designed, but not implemented due to time constraints. It is recommended to add these logic cores to the FPGA internal hardware. This Tri-Core technology will create greater redundancy and reliability by using the Microblaze processor solely as the communications driver. The design for this architecture can be located in Appendix 2.

RecommendationsRecommendations

Additional PeripheralsAdditional Peripherals This design is highly scalable with over 100 unused I/O pins. These can be used to easily add the LVDT sensors through external A/D converters including redundant circuitry as well as the flow meter’s pulse train input. In addition, one control module could be configured to operate multiple pairs of solenoids by using an additional optocoupler / H-Bridge circuit for each added pair of solenoids. Multiple sensors could also be added to the control module through unused I/O pins.

SUMMARYSUMMARY

Current SystemCurrent SystemLimited EnvironmentLimited EnvironmentStaticStatic

Proposed SystemProposed SystemReliableReliableSubmersibleSubmersibleScalableScalable

SUMMARYSUMMARY

Straightforward SolutionStraightforward Solution

High Level ProgrammingHigh Level Programming

Completed by December 1Completed by December 1stst

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