ECE 550D Fundamentals of Computer Systems and Engineering...

ECE 550D Fundamentals of Computer Systems and Engineering

Fall 2017

Storage and Clocking

Prof. John Board

Duke University

Slides are derived from work by Profs. Tyler Bletsch and Andrew Hilton (Duke)

VHDL: Behavioral vs Structural

• A few words about VHDL

• Structural:

• Spell out at (roughly) gate level

• Abstract piece into entities for abstraction/re-use

• Very easy to understand what synthesis does to it

• Behavioral:

• Spell out at higher level

• Sequential statements, for loops, process blocks

• Can be difficult to understand how it synthesizes

• Difficult to resolve performance issues

Last time…

• Who can remind us what we did last time?

• Add

• Subtract

• Bit shift

• Floating point

So far…

• We can make logic to compute “math”

• Add, subtract,… (we’ll see multiply/divide later)

• Bitwise: AND, OR, NOT,…

• Shifts

• Selection (MUX)

• …pretty much anything

• But processors need state, i.e. memory (hold value)

• Registers

• Main Memory

• Storage (disks)

Memory Elements

• All the circuits we looked at so far are combinational circuits: the output is (only) a Boolean function of the present inputs (a specific combination of inputs always results in exactly the same output)

• We need circuits that can remember values (registers, memory)

• For sequential circuits, the output of the circuit is a function of both the present inputs and the history (sequence of events) of how we got here, represented by a value which we call the state

• Circuits with storage are called sequential circuits

• Key to storage: feedback

Ideal Storage – Where We’re Headed

• Ultimately, we want something that can hold 1 bit and we want to control when it is re-written

• However, instead of just giving it to you as a magic black box, we’re going to first dig a bit into the box

“flip flop” =

device that

holds one

bit (0 or 1)

bit to be written bit currently being held

bit to control

when we write

FF Step #1: NOR-based Set-Reset (SR) Latch

If I am crazy enough to wire up

2 nor gates this way – fire??

No – two stable configurations

as shown here. But how to move

between them?

Let’s start with the left side, which

we consider to be the “reset” state

Set-Reset Latch (Continued)

We activate SET

for a brief time,

then lower it

Set Signal Goes High

Output Signal Goes High

(2 gate delays later)

Set Signal Goes Low

Output Signal Stays High

Until Reset Signal

Goes High

Then Output Signal Goes Low

(again 2 gate delays later)

FF Step #1: NOR-based Set-Reset (SR) Latch

1 1 - Don’t set both S & R to 1.

Seriously, don’t do it.

R,S both low, remember the

previous command

S set the latch to 1 (even if it is

already 1)

R reset the latch to 0 (even if it

is already 0)

R,S together causes oscillation,

random value - bad

SR Latch

• Upside: IT HAS MEMORY! If we never invented something better/fancier, we could build computers with these!!!

• Upside: it’s cheap – just 2 nor gates

• Downside: S and R at once = chaos

• Downside: Bad interface, bad timing behavior

• So let’s build on it to do better

Building up to the D Flip-Flop and beyond

SR Latch

D Latch

E !Q !Q

D Flip-Flop

32 bit reg

Register

(too awkward) (bad timing) (okay but only one bit) (nice!)

FF Step #2: Data Latch (“D Latch”)

Starting with SR Latch

Data Latch (D Latch)

Starting with SR Latch

Change interface to

Data + Enable (D + E)

If E=0, then R=S=0.

If E=1, then S=D and R=!D

Enable

E goes high

D “latched”

Stays as output

Enable

Does not

affect Output

E goes low

Output unchanged

By changes to D

Enable

E goes high

D “latched”

Becomes new output

Enable

Slight Delay

(Logic gates take

- Here about 4

gate delays

Logic Takes Time

• The D latch is a good next step but still has messy timing for using in a computer

• Logic takes time:

• Gate delays: delay to switch each gate

• Wire delays: delay for signal to travel down wire

• Other factors (not going into them here)

• Need to make sure that signal timing is right

• Don’t want to have races or unpredictable or unexpected conditions..

Clocks

• Processors have a clock:

• Alternates 0 1 0 1

• Like the processor’s internal metronome

• Latch logic latch in one clock cycle

• 3.4 GHz processor = 3.4 Billion clock cycles/sec

One clock cycle

FF Step #3: Using Level-Triggered D Latches

• First thoughts: Level Triggered

• Latch enabled when clock is high

• Hold value when clock is low

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

Strawman: Level Triggered

• How we’d like this to work

• Clock is low, all values stable

010 111 100 001

• Clock goes high, latches capture and xmit new val

010 010 100 100

• Signals work their way through logic w/ high clk

010 010 100 100

• Clock goes low after all logic but just before signals reach next latch

010 010 100 100

• Clock goes low before signals reach next latch

111 010 000 100

• Everything stable before clk goes high a second time

111 010 000 100

• Clk goes high again, repeat

111 111 000 000

• Problem: Really hard to time this! What if signal reaches latch too early while clk is still high the first time?

111 111 101 000

• Problem: What if signal reaches latch too early?

• Signal goes right through latch, into next stage..

111 111 101 101

That would be bad…

• Getting into a stage too early is bad

• Something else is going on there corrupted

• Also may be a loop with one latch

• And this assumed all signals take the same amount of time to get through the logic cloud – in reality some faster than others

• Consider incrementing counter (or PC)

• Too fast: increment twice? Eeek…

3 bit adder with one side wired

permanently to 001

SR Latch

D Latch

E !Q !Q

D Flip-Flop

32 bit reg

Register

FF Step #4: Edge Triggered

• Instead of level triggered latch

• Latch a new value at a clock level (high or low)

• We use edge triggered flip flop

• Latch a value (only) at a clock edge (rising or falling)

Falling Edges

Rising Edges

Our Ultimate Goal: D Flip-Flop

• Rising edge triggered D Flip-flop

• Two D Latches w/ opposite clocking of enables

D Flip-Flop

• Two D Latches w/ opposite clocking of enables

• On Low Clock, first latch enabled (propagates value)

• Second not enabled, maintains value

D Flip-Flop

• Two D Latches w/ opposite clking of enables

• On Low Clock, first latch enabled (propagates value)

• Second not enabled, maintains value

• On High Clock, second latch enabled

• First latch not enabled, maintains value

• Value from first latch flips into second latch at instant of rising clock edge, stays constant until next rising edge

D Flip-Flop

• No possibility of “races” anymore

• Even if I put 2 DFFs back-to-back…

• By the time signal gets through 2nd latch of 1st DFF

1st latch of 2nd DFF is disabled

• Still must ensure signals reach DFF before clk rises

• Important concern in logic design “making timing”

• Having signals ready in time for next clock edge (need to be stable a few moments before the edge in fact)

Making Timing

• Making timing is important in a design • If you don’t make timing, your logic won’t compute right

• Synthesis tool (Quartus) tells you what maximum frequency your design will run safely

• If you run above this, your logic doesn’t “finish” in time

D Flip-flops (continued…)

• Could also do falling edge triggered

• Switch which latch has NOT on clock

• D Flip-flop is ubiquitous

• Must properly differentiate between latches (level sensitive) and flip-flops (edge sensitive)

• Which edge: doesn’t matter

• As long as consistent in entire design

• We’ll use rising edge

• And often both – rising for writing, falling for reading, to allow data transfer in a single clock cycle, but more on that later!

D flip flops

• Generally don’t draw clk input

• Have one global clk, assume it goes there

• Should always see “>” to indicate edge triggered device

• Maybe have explicit enable

• Might not want to write every cycle

• If no enable signal shown, implies always enabled

• Get output and NOT(output) for “free”

DFFs in VHDL

x: dffe port map (

clk => clk, --the clock

d => someInput, --the input is d

q => theOutput, --the output is q

ena => en, --the enable

clrn => '1', --clear

prn => '1'); --set (PReset)

Also, comes in “dff” with no enable

A word of advice

signal x_q : std_logic;

signal x_d: std_logic;

x : dffe port map (…, d=> x_d, q=>x_q,…);

• Use naming convention: x_d, x_q

• Write x_d, read x_q

• Remember new value shows up next cycle

x x_d x_q

A few words about timing

• Homework 2: VGA Controller

• Requires certain clock frequency

• Else won’t control monitor properly

• Quartus will tell you what maximum timing your current circuit makes

• Fmax : how fast can this be clocked

• Tells you your worst timing paths

• From which dff to which dff

• Can see in schematic viewer (usually)

• Homework 2

• Should be plenty of slack

• But if not…

Fixing timing misses

• Typical approach: reduce logic (gate delays)

• Better adder?

• Rethink approach?

• Change “don’t care” behavior?

• Fix high fanout

• Duplicate high Fan Out/simple logic

• Also, feel free to ask for help from me/TAs

• Quartus’s tools to help you fix them aren’t the best

SR Latch

D Latch

E !Q !Q

D Flip-Flop

32 bit reg

Register

Stick a bunch of DFFs together to make a register

32 bit reg

enable

Next evolution: multiple registers

32 bit reg

Register

(nice!)

32 bit reg

WrData

Register File (Tremendous!)

> “Tristate”

buffers –

ECE 550D Fundamentals of Computer Systems and Engineering...

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