EE 122: Router Design - University of California, …ee122/fa02/notes/lecture...laik@cs.berkeley.edu...

EE 122: Router DesignKevin Lai

September 25, 2002

laik@cs.berkeley.edu 2

Routers

.

.. ...

A router consists- A set of input interfaces at which packets arrive- A set of output interfaces from which packets depart- Some form of interconnect connecting inputs to outputs

Router implements two main functions- Forward packet to corresponding output interface- Manage bandwidth and buffer space resources

laik@cs.berkeley.edu 3

What a Router Looks Like

6ft

19”

2ft

Capacity: 160Gb/sPower: 4.2kW

3ft

2.5ft

Cisco GSR 12416 Juniper M16019”

Capacity: 80Gb/sPower: 2.6kW

Slide by Nick McKeown

laik@cs.berkeley.edu 4

Why Understand Router Design

Many companies make switches and routers- e.g., Cisco, Juniper, Nortel

Many other devices have a similar structure- e.g., PC’s internal interconnect, multi-processor

interconnectSwitch design dictates what can be done at higher layers

- e.g., per flow state is expensive,the need to minimize per packet processing time

laik@cs.berkeley.edu 5

Why Do We Need Faster Routers?

1. To prevent routers becoming the bottleneck in the Internet.

2. To increase POP capacity, and to reduce cost, size and power.

laik@cs.berkeley.edu 6

Why we Need Faster Routers 1: To prevent routers from being the bottleneck

0,1

1

10

100

1000

10000

1985 1990 1995 2000

Spec

95In

t CPU

resu

lts

0,1

1

10

100

1000

10000

1985 1990 1995 2000

Fibe

r Cap

acity

(Gbi

t/s)

TDM DWDM

Packet processing Power

2x / 18 months 2x / 7 months

Link Speed

Source: SPEC95Int & David Miller, Stanford.

Slide by Nick McKeown

laik@cs.berkeley.edu 7

Why we Need Faster Routers 2: To reduce cost, power & complexity of POPs

POP with large routers POP with smaller routers

Ports: Price >$100k, Power > 400W. It is common for 50-60% of ports to be for interconnection.

Slide by Nick McKeown

laik@cs.berkeley.edu 8

Requirements

Power- generates heat, costs money- < 5kW

Size- space costs money- < 2m3

BandwidthPorts

- number of external linksPriceSome customers want

- Multicast- Quality of Service

laik@cs.berkeley.edu 9

Generic Router Architecture

Input and output interfaces are connected through an interconnectA interconnect can be implemented by

- Shared memory • low capacity routers (e.g.,

PC-based routers)- Shared bus

• Medium capacity routers- Point-to-point (switched) bus

• High capacity routers

input interface output interface

Inter-connect

laik@cs.berkeley.edu 10

First Generation Routers

RouteTableCPU Buffer

Memory

LineInterface

MAC

LineInterface

MAC

LineInterface

MAC

Typically <0.5Gb/s aggregate capacity

Shared Backplane

Line Interface

CPU

Memory

Slide by Nick McKeown

laik@cs.berkeley.edu 11

Second Generation Routers

RouteTableCPU Buffer

Memory

LineCard

BufferMemory

LineCard

MAC

BufferMemory

LineCard

MAC

BufferMemory

FwdingCache

FwdingCache

FwdingCache

MAC

Typically <5Gb/s aggregate capacitySlide by Nick McKeown

laik@cs.berkeley.edu 12

Third Generation Routers

LineCard

MAC

LocalBuffer

Memory

CPUCard

LineCard

MAC

LocalBuffer

Memory

FwdingTable

RoutingTable

FwdingTable

Switched Backplane

Line Interface

CPUMemory

Typically <50Gb/s aggregate capacity

Slide by Nick McKeown

laik@cs.berkeley.edu 13

Speedup

C – input/output link capacityRI – maximum rate at which an input interface can send data into interconnectRO – maximum rate at which an output can read data from interconnectB – maximum aggregate interconnect transfer rateInterconnect speedup: B/CInput speedup: RI/COutput speedup: RO/C

input interface output interface

Inter-connect

RI ROBC C

laik@cs.berkeley.edu 14

Typical Functions Performed by Input Interface on Data Path

Packet forwarding: decide to which output interface to forward each packet based on the information in packet header

- examine packet header- lookup in forwarding table- update packet header

laik@cs.berkeley.edu 15

Typical Functions Performed by Output Interface

Buffer management: decide when and which packet to dropScheduler: decide when and which packet to transmit

1

2

SchedulerBuffer

laik@cs.berkeley.edu 16

Typical Functions Performed by Output Interface (cont’d)

1

2

Scheduler

flow 1

flow 2

flow n

Classifier

Buffer management

Packet classification: map each packet to a predefined flow/connection (for datagram forwarding)

- use to implement more sophisticated services (e.g., QoS)

Flow: a subset of packets between any two endpoints in the network

laik@cs.berkeley.edu 17

Interconnect

Point-to-point switch allows to simultaneouslytransfer a packet between any two disjoint pairs of input-output interfacesGoal: come-up with a schedule that

- Provide Quality of Service- Maximize router throughput

Challenges:- Address head-of-line blocking at inputs- Resolve input/output speedups contention- Avoid packet dropping at output if possible

Note: packets are fragmented in fix sized cells at inputs and reassembled at outputs

laik@cs.berkeley.edu 18

Output Queued (OQ) Routers

input interface output interface

Backplane

RO

Only output interfaces store packetsAdvantages

- Easy to design algorithms: only one congestion point

Disadvantages- Requires an output speedup

of N, where N is the number of interfaces not feasible C

laik@cs.berkeley.edu 19

Input Queueing (IQ) RoutersOnly input interfaces store packetsAdvantages

- Easy to built • Store packets at inputs if

contention at outputs - Relatively easy to design algorithms

• Only one congestion point, but not output…

• need to implement backpressureDisadvantages

- Hard to achieve utilization 1 (due to output contention, head-of-line blocking)

• However, theoretical and simulation results show that for realistic traffic an input/output speedup of 2 is enough to achieve utilizations close to 1

input interface output interface

Backplane

RO C

laik@cs.berkeley.edu 20

Head-of-line Blocking

The cell at the head of an input queue cannot be transferred, thus blocking the following cells

Cannot betransferred because output buffer overflow

Cannot be transferred because is blocked by red cell

Input 1 Output 1

Input 2 Output 2

Input 3 Output 3

laik@cs.berkeley.edu 210% 20% 40% 60% 80% 100%Load

Dela

yA Router with Input Queues

Head of Line Blocking

The best that any queueing system can

achieve.

2 2 58%− ≈Slide by Nick McKeown

laik@cs.berkeley.edu 22

Solution to Avoid Head-of-line Blocking

Maintain at each input N virtual queues, i.e., one per output

Input 1Output 1

Output 2Input 2

Output 3

Input 3

laik@cs.berkeley.edu 23

Combined Input-Output Queueing (CIOQ) Routers

Both input and output interfaces store packetsAdvantages

- Easy to built • Utilization 1 can be achieved

with limited input/output speedup (<= 2)

Disadvantages- Harder to design algorithms

• Two congestion points• Need to design flow control

input interface output interface

Backplane

RO C