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EE3A1 Computer Hardware and EE3A1 Computer Hardware and Digital DesignDigital Design
Lecture 2
Introduction to VHDL
IntroductionIntroduction
We’ll look at some simple design in VHDL These will be the examples used in lab 1
A simple exampleA simple example
NAND gate
1st thing to do: Say what it looks like to the rest of the system List of inputs and outputs Port map
Port map: inputs and outputsPort map: inputs and outputs
Uppercase is a VHDL keyword Lower case is name I have chosen
Mode can be IN or OUT
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END;
Port map: inputs and outputsPort map: inputs and outputs
Type STD_LOGIC can be ‘0’, ‘1’, ‘X’ or ‘U’. ‘X’ means unknown ‘U’ means uninitialized
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END;
ArchitectureArchitecture
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END;
Now we know how many inputs and outputs Next we say how outputs derive values from inputs: Architecture
ArchitectureArchitectureENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;
Simulate itSimulate it
Check our design by giving it inputs Simulator says what the output would do
Output is 0 when both inputs are 1: It works
Multiple architecturesMultiple architectures
We can give more than 1 architecture Distinguish them by different names
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;
ARCHITECTURE complicated OF nandgate IS
BEGIN
c <= NOT ( a AND b );
END;
BEGIN and END statementsBEGIN and END statements
C: Block defined by { and }
for (i=1; i<=n; i++)
{
a[i]=i;
b[i]=a[i]*a[i];
}
A block is a group of statements that should be treated as one
BEGIN and END statementsBEGIN and END statements
VHDL: Block defined by BEGIN and END
FOR i IN ( 1 TO N ) LOOPBEGIN a(i) = i; b(i) = a(i) * a(i);END LOOP;
A block is a group of statements that should be treated as one
SemicolonsSemicolons
C:
for (i=1; i<=n; i++); /* WRONG semicolon */
{; /* ALSO WRONG semicolon */
a[i]=i;
b[i]=a[i]*a[i];
}
; indicates end of statement. Statements that "open up" a block don't take semicolons:
SemicolonsSemicolons
VHDL:
FOR i IN ( 1 TO N ) LOOP; --WRONG semicolon
BEGIN; --ALSO WRONG semicolon
a(i) = i;
b(i) = a(i) * a(i);
END LOOP;
; indicates end of statement. Statements that "open up" a block don't take semicolons:
ENTITY doesn’t need a BEGINENTITY doesn’t need a BEGIN
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC );
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;
Style issuesStyle issues
VHDL is not case sensitive. In (black and white) books, VHDL keywords
are normally in one particular case In editors, VHDL keywords are normally in
one particular colour
Style issuesStyle issues These are the same:
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
entity NANDGATE is
port ( A, B: in std_logic; C: out std_logic);
end;
entity nandgate is
port ( a, b: in std_logic; c: out std_logic);
end;
Spaces, indents and line breaksSpaces, indents and line breaks Have no effect on code meaning Used to enhance clarity These are the same:
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END;
Annotating END statementsAnnotating END statements
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END;
It’s good style to say what you are ENDing
Annotating END statementsAnnotating END statements
Often helps avoid bugs or confusion Usually optional
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC);
END;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END ARCHITECTURE simple;
It’s good style to say what you are ENDing
CommentsComments
Comments are introduced by two dashes
-- This is a comment
LibrariesLibraries
void main ()
{
printf(“My first C program”);
}
ERROR: printf not found
LibrariesLibraries
#include <stdio.h>
void main ()
{
printf(“My first C program”);
}
Works OK
The IEEE libraryThe IEEE library
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END ENTITY nandgate;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END ARCHITECTURE simple;
Error message “Cannot recognise type STD_LOGIC”.
Opening librariesOpening libraries
Definition of STD_LOGIC is held in library Must open library in order to get at definitions Main library is called IEEE
LIBRARY IEEE;
USE IEEE.XXXX.YYYY
XXXX is sub-library (package) YYYY is feature that you want to use.
Opening librariesOpening libraries
Definition of STD_LOGIC is held in library Must open library in order to get at definitions Main library is called IEEE
LIBRARY IEEE;
USE IEEE.XXXX.ALL
If you want to open all features of the package
Using STD_LOGICUsing STD_LOGICLIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nandgate IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END ENTITY nandgate;
ARCHITECTURE simple OF nandgate IS
BEGIN
c <= a NAND b;
END ARCHITECTURE simple;
QuestionsQuestions
What is the block diagram for this entity declaration?ENTITY question1 IS
PORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC; c: IN STD_LOGIC; d: OUT
STD_LOGIC );
END ENTITY question1;
What is wrong with this architecture (2 problems)?ARCHITECTURE simple OF question1 IS
BEGIN
b <= a NAND c;
END ARCHITECTURE complicated;
What is the block diagram for this entity declaration?
ENTITY question1 ISPORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC;
c: IN STD_LOGIC; d: OUT STD_LOGIC );
END ENTITY question1;
QuestionsQuestions
What is wrong with this architecture?
ARCHITECTURE simple OF question1 IS
BEGIN
b <= a NAND c;
END ARCHITECTURE complicated;
Output d is never assigned a value
Mismatch in architecture names
Example 2Example 2
Arithmetic Logic Unit Heart of a microprocessor 1st part of the assignment To build ALU we need
Conditionals Signals that are many bits wide Arithmetic on signals
ConditionalsConditionals
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ConditionalsConditionals
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY equals ISPORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);END ENTITY equals;
ConditionalsConditionals
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY equals ISPORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);END ENTITY equals;
ARCHITECTURE number1 OF equals ISBEGIN
c <= '1' WHEN a=b ELSE '0';END ARCHITECTURE number1;
Signals that are more than 1 bitSignals that are more than 1 bit
STD_LOGIC_VECTOR(0 TO 3) Four members a(0), a(1), a(2) and a(3). Each is of type STD_LOGIC.
a
b c
4
4
4
a
b
0
0
a
b
1
1
a
b
2
2
a
b
3
3
c 0
c 1
c 2
c 3
Example of 4-bit deviceExample of 4-bit device
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY orgate ISPORT
( a, b: IN STD_LOGIC_VECTOR(0 TO 3); c: OUT STD_LOGIC_VECTOR(0 TO 3));END ENTITY orgate;
a
b
0
0
a
b
1
1
a
b
2
2
a
b
3
3
c 0
c 1
c 2
c 3
Example of 4-bit deviceExample of 4-bit device
ARCHITECTURE number1 OF orgate IS
BEGIN
C(0) <= a(0) OR b(0);
C(1) <= a(1) OR b(1);
C(2) <= a(2) OR b(2);
C(3) <= a(3) OR b(3);
END ARCHITECTURE number1;
a
b
0
0
a
b
1
1
a
b
2
2
a
b
3
3
c 0
c 1
c 2
c 3
Example of 4-bit deviceExample of 4-bit device
ARCHITECTURE number2 OF orgate IS
BEGIN
c <= a OR b;
END ARCHITECTURE number2;
a
b
0
0
a
b
1
1
a
b
2
2
a
b
3
3
c 0
c 1
c 2
c 3
The compiler can figure out that a,b,c are 4 bits wide
Example of 4-bit deviceExample of 4-bit device
ARCHITECTURE number3 OF orgate IS
BEGIN
C(0 TO 3) <= a(0 TO 3) OR b(0 TO 3);
END ARCHITECTURE number3;
a
b
0
0
a
b
1
1
a
b
2
2
a
b
3
3
c 0
c 1
c 2
c 3
Making the loop explicit
STD_LOGIC_VECTOR STD_LOGIC_VECTOR valuesvalues
Single bit STD_LOGIC assignment: a <= ‘1’; --single quotes
4-bit STD_LOGIC_VECTOR assignment: a <= “1110”; -- double quotes.
Direction of numberingDirection of numbering
Can number upwards or downwards
a: STD_LOGIC_VECTOR(0 TO 3); a <= “1110”;
Element 0
Element 3
Element 2 Element 1
a: STD_LOGIC_VECTOR(3 DOWNTO 0); a <= “1110”;
Element 3
Element 0
Element 1 Element 2
Both represent the same decimal number 14 if it’s signed; -2 if it’s unsigned
Direction of numberingDirection of numbering
In digital logic design bit 0 is usually lsb So in VHDL index usually counts downwards
a: STD_LOGIC_VECTOR(3 DOWNTO 0); a <= “1110”;
Element 3
Element 0
Element 1 Element 2
a: STD_LOGIC_VECTOR(0 TO 3); a <= “1110”;
Element 0
Element 3
Element 2 Element 1
Arithmetic onArithmetic on STD_LOGIC_VECTORSTD_LOGIC_VECTORss
Comparator
g <= ‘1’ WHEN a>b ELSE ‘0’; Signed or unsigned?
1111 is +15 or –1? 1110 is +14 or –2?
a
b g
4
4
Arithmetic onArithmetic on STD_LOGIC_VECTORSTD_LOGIC_VECTORss
VHDL has two different versions of +,-,>,< etc. STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED
Import one or the other
Arithmetic onArithmetic on STD_LOGIC_VECTORSTD_LOGIC_VECTORss
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_signed.ALL; ENTITY comp IS
PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); g: OUT STD_LOGIC);END ENTITY comp; ARCHITECTURE simple OF comp ISBEGIN
g <= ‘1’ WHEN a>b ELSE ‘0’;END ARCHITECTURE simple;
1111 will be interpreted as -1
Arithmetic onArithmetic on STD_LOGIC_VECTORSTD_LOGIC_VECTORss
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL; ENTITY comp IS
PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); g: OUT STD_LOGIC);END ENTITY comp; ARCHITECTURE simple OF comp ISBEGIN
g <= ‘1’ WHEN a>b ELSE ‘0’;END ARCHITECTURE simple;
1111 will be interpreted as 15
ALU exampleALU example
a
b c
16
16
16 alu
opcode 2
Opcode Operation
00 a + b
01 a – b
10 a and b
11 a or b
16 bit ALU Operation is selected by opcode
ALU exampleALU example
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_signed.ALL; ENTITY alu IS
PORT ( a, b: IN STD_LOGIC_VECTOR(15 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR(1 DOWNTO 0); c: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );END ENTITY alu;
ALU exampleALU example
ARCHITECTURE simple OF alu IS
BEGIN
c <= a + b WHEN opcode=”00”
ELSE a - b WHEN opcode=”01”
ELSE a OR b WHEN opcode=”10”
ELSE a AND b WHEN opcode=”11”;
END ARCHITECTURE simple;
Simulate the ALUSimulate the ALU
a = “0000000001110111”, 0077H. b = “0000000000000001”, 0001H. As opcode changes “00”,”01”,”10”,”11”, (0,1,2,3) output gets a+b, then a-b, then a OR b then a AND c.
Synthesise the exampleSynthesise the example
It works as expected Synthesise to gate level description Much quicker and easier than doing it the old
fashioned way More flexible too
SummarySummary
Intro to VHDL Basic examples for use in lab 1
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