View
35
Download
1
Category
Tags:
Preview:
DESCRIPTION
EECS 170C Lecture Week 1. Lowpass Filter Example. ideal op-amp. From standard circuit analysis:. Specifications:. ideal op-amp. Lowpass Filter Design. 2 equations with 3 unknowns not a unique solution!. Additional constraint #1:. Capacitors should be no larger than 1 pF:. - PowerPoint PPT Presentation
Citation preview
1
EECS 170C LectureWeek 1
Spring 2014 EECS 170C
Prof. M. Green / U.C. Irvine
Lowpass Filter Example
idealop-amp
From standard circuit analysis:
Spring 2014 EECS 170C
2Prof. M. Green / U.C. Irvine
idealop-amp
Lowpass Filter Design
Specifications:
2 equations with 3 unknowns not a unique solution!
Spring 2014 EECS 170C
3Prof. M. Green / U.C. Irvine
Capacitors should be no larger than 1 pF:
Set C2 = 1 pF
R2 = 318 R1 = 159
Additional constraint #2:
For f > f3dB, magnitude should exhibit -40 dB/decade rolloff:
ff3dB
-20 dB/decade
The given circuit topology cannot satisfy this constraint.
Additional constraint #1:
Spring 2014 EECS 170C
4Prof. M. Green / U.C. Irvine
Additional constraint #3:
Under the condition that R’s and C’s vary randomly within ±10%,f3B should vary no more than ±5%
This constraint is impossible to meet for any RC filter!
2nd-order filter topology (2 capacitors) needed:
Spring 2014 EECS 170C
5Prof. M. Green / U.C. Irvine
Replace resistors with triode-biasedMOSFETs with gates controlled bydc voltage VG, realizing electrically controllable resistors.
Critical frequencies can be controlled by VG.
VinVout
VG
Possible solution #2:
Replace resistors with configuration consisting of capacitor and switches, with switches controlled by clock signal with period Tc. Critical frequencies are determined by Tc and capacitor ratios.
Critical frequencies can be controlled by Tc.
VinVout
Possible solution #1:
Spring 2014 EECS 170C
6Prof. M. Green / U.C. Irvine
Aspects of Design (Synthesis)
• Desired behavior & specifications are given; component values & circuit topology are not.
• Solution is usually found iteratively: An initial circuit is proposed and analyzed. If specifications are not met, the circuit is modified and re-analyzed.
• There is usually not a unique solution that satisfies the specifications. However, each solution exhibits its own set of tradeoffs (e.g., size, cost, robustness) that must be considered.
• It may not be possible to meet all of the specifications simultaneously using a given technique or technology.
Spring 2014 EECS 170C
7Prof. M. Green / U.C. Irvine
Analog vs. Digital Signal Representation
Analog representation:
Precision in specifying and measuring voltage signal is determined by random noise generated by circuit components.
Dynamic Range is determined by ratio of maximum amplitude (usually determined by supply voltage) and noise level.
Digital representation:
Dynamic Range in specifying and measuring digital signal is determined by number of bits used in representing the signal.
Spring 2014 EECS 170C
8
16 possible digits Dynamic Range = 16
Prof. M. Green / U.C. Irvine
Continuous vs. Discrete Methods of Timing
Continuous-time signaling:
Voltage signal is defined at any arbitrary instant of time. There is no limit on the highest frequency that can be generated or measured.
Discrete-time signaling:
Voltage signal is defined only at discrete values of time kT, where k is an integer. The highest frequency that can be observed is 1/2T – the Nyquist frequency.
Spring 2014 EECS 170C
9Prof. M. Green / U.C. Irvine
Passive Components
Power dissipation in a resistor:
Components that always dissipate power are said to be passive.
Power supplied by VS:
Power dissipated in RL:
Power gain:
Power amplification is impossible if only passive components are present.
Spring 2014 EECS 170C
10Prof. M. Green / U.C. Irvine
Active Components
A component that is not passive is said to be active.
(assuming rin >> RS , rout << RL)
Power amplification is possible with active devices -- that’s why we need transistors.
Spring 2014 EECS 170C
11Prof. M. Green / U.C. Irvine
Discrete Circuit Realized on a Printed Circuit Board (PCB)
Spring 2014 EECS 170C
12Prof. M. Green / U.C. Irvine
Integrated Circuit on a Monolithic Substrate
Spring 2014 EECS 170C
13Prof. M. Green / U.C. Irvine
Circuit Realization:Discrete vs. Monolithic
• Each component takes roughly the same area on the board independent of its value.
• Passive components can be chosen to a desired accuracy, subject to cost.
• Most circuit nodes can be observed for testing and verification.
• Dimensions on order of cm.
• The area of a component is directly related to its value.
• Individual component values exhibit large variances; however, like components with identical geometries in close proximity exhibit very close matching (<1%).
• Access to the circuit is only through pre-determined nodes that are connected to pads which then bonded out to the package.
• Dimensions on order of mm, encapsulated in a package.
Spring 2014 EECS 170C
14Prof. M. Green / U.C. Irvine
Example of Matching
Design an amplifier with an accurate gain of +10:
Assume Av can take values between 10,000 and 50,000.
Very small depends onlyon resistor ratio
Let R1 = 9k , R2 = 1k:
Av = 10,000 Vout /Vin = 9.990
Av = 50,000 Vout /Vin = 9.998independent of individual resistor values
Spring 2014 EECS 170C
15Prof. M. Green / U.C. Irvine
X
X
X
1. Die Size
Manufacturability of ICs
Spring 2014 EECS 170C
16Prof. M. Green / U.C. Irvine
2. Power Dissipation
Power dissipated in the IC is converted to heat, raising the temperature of the die & package.
Elevated die temperature can degrade circuit performance or even permanently damage the silicon.
To accelerate heat removal, a heat sink may need to be used, requiring more space.
Passive heat sinks Active air-cooling heat sink
Spring 2014 EECS 170C
17Prof. M. Green / U.C. Irvine
3. Robust Design
IC must operate properly in the presence of variations in:• Processing in fabrication technology
• Individual component values can vary ±15% or more• Voltage supply
• Supply voltages can vary ±10%• Temperature
• Circuit should operate to spec at 0--70° C ambient temperature
“PVT”
Spring 2014 EECS 170C
18Prof. M. Green / U.C. Irvine
Prof. M. GreenUniv. of California, Irvine
19
KCL at Vout:
KCL at VX:
Use of Approximation
19Spring 2014 EECS 170C
Prof. M. Green / U.C. Irvine
20
My Research
The operation of “real” high-speed clock dividers is more complex …
Spring 2014 EECS 170C
1. High-speed frequency divider:
Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C
21
Clock divider based on CML D flip-flop:
Divider sensitivity curve:
Vmin = minimum input clock amplitude required for correct operation. (function of input frequency)
fso = self-oscillation frequency
Vmax = maximum dc differential voltage that can be applied to the input clock for which the circuit self-oscillates.
Vmax
Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C 22
Divider chip photograph
Measured sensitivity curves:a) Conventional (DFF) dividerb) Modified regenerative dividerc) Ring oscillator divider
Designed at Broadcomusing 0.13 µm CMOS process;shunt-peaking was used.
Divider test chip measurements
Prof. M. Green / U.C. Irvine
• Normally the equalizer and CDR are designed and implemented as separate blocks.• Common elements in each of the two blocks can be identified and combined...
Spring 2014 EECS 170C
23
2. Equalization of broadband receivers:
Prof. M. Green / U.C. Irvine
Circuit Details• Shunt-peaking CML summer.• 2-stage shunt-peaking CML slicer.• Differentially-tuned LC VCO.• Retimer generates low-ISI retimed
data.
Spring 2014 EECS 170C
24Prof. M. Green / U.C. Irvine
Measurement Setup
Die photo. Implemented in Jazz Semiconductor 0.18µm BiCMOS Process (only CMOS transistors used).
Test board
Test setup
Spring 2014 EECS 170C
25Prof. M. Green / U.C. Irvine
Equalizer + CDR Operation (2)
Recovered clock RJ = 2.15 ps rms
Recovered clock RJ = 1.83 ps rms
Retimer output eye diagramJitter = 4.14 ps rms
Retimer output eye diagramJitter = 4.96 ps rms
2.4 mcable
3.6 mcable
Cable output eye diagram.
Cable output eye diagram.
Spring 2014 EECS 170C
26Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C
27
Din1
Din2
DoutD-FF
D QLatch
D Q
10 GHz
D-FF
D Q
D-FF
D QLatch
D Q
D-FF
D Q
Select
AB
D-FF
D Q
D-FF
D QLatch
D Q
Select
AB
Din3
Din0
Select
AB
10 GHz
10 GHz
20 GHz
20 GHz
retimer
40 GHz
40 GHz÷2 PLL÷2
20 GHz
10 GHz
4:1 Multiplexer Tree Structure:
2. Equalization of broadband receivers:
Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C
28
40GHz Differential Push-Push VCO
Resonates at 20 GHz
Virtual ground node
Resonates at 40 GHz
Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C
29
Chip Board and Die Micrograph
20 Gb/s inputs
40 Gb/s output20 GHz clock
625 MHz Reference
clock
40Gb/s Distributed
buffer
40Gb/s MUX and retimer
Push-pushdifferential
VCO
PLLClock buffers
20Gb/s inputs
40 Gb/s output
20 GHz clock output
Prof. M. Green / U.C. Irvine
Spring 2014 EECS 170C
30
Measured 40 Gb/s Output
40Gb/s MUX output (Differential) with 450 mV differential peak-to-peak vertical eye opening and 1.14 ps rms jitter
Prof. M. Green / U.C. Irvine
Recommended