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3-bit Counter has 14 transitions in 8 cycles 14/8 = 1.75 transitions per cycle
N-bit Counter has 2(2N-1) transitions Transitions per cycle → 2 as N→ ∞
4-bit 1.875 transitions/clock
5-bit 1.93756-bit 1.968757-bit 1.9843758-bit 1.99218759-bit 1.99609375
000 --001 1010 2011 1100 3101 1110 2111 1000 3
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3-bit counter has 8 transitions in 8 cycles 8/8 = 1 transition per cycle
N-bit counter has 2N transitions Transitions per cycle is 1
for any size counter
For large counters, ratio of transitions for Decimal to Gray → 2
000 --
001 1011 1010 1110 1111 1101 1100 1000 1
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Gray Encoding can be accomplished by Binary to Gray conversion Directly Synthesizing Gray Counter
Binary to Gray conversion is accomplished with 2 XOR gates
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Power analysis conducted with powersim
.18 μm, 1.8V supply8
Decimal Encoding
Decimal to Gray
% Reduction Gray Encoding
% Reduction
# of Gates 8 9 -12.5% 12 -50%
# of Glitches 3122 3496 -11.97% 1618 48.17%
Glitch Power (μW) 1.852307 1.583410 14.52% 0.934297 49.56%
Dynamic Power (μW)
1.855127 1.587364 14.43% 0.940320 49.31%
Leakage Power (μW)
.914450 .986150 -7.84% .889597 2.72%
Logic Power (μW) .002820 .003955 -40.25% .006024 -113.62%
Total Power (μW) 2.769578 2.573515 7.08% 1.829918 34.18%
Much of dynamic power consumption comes from glitches Can be reduced by path balancing
Directly implementing gray counter in logic removes ~1/2 of the glitches, however consumes more leakage and logic power due to increase in number of logic gates
Overall, gray counters are more power efficient
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Hakenes, R.; Manoli Y. “A Segmented Gray Code for Low-Power Microcontroller Address Buses”. EUROMICRO Conference, 1999. Proceedings. 25th, Pages 240 – 243, Vol. 1
Doran, R. W. “The Gray Code”. Centre for Discrete Mathematics and Theoretical Computer Science, March, 2007.
Mehta, Huzefa et al. “Some Issues in Gray Code Addressing”. Proceedings of the 6th Great Lakes Symposium on VLSI, 1996. Pages 178 – 181.
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