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7/28/2019 EM of Copper Damascene Interconnects Integrated Wtih Low-K
1/1
Electromigration Characteristics of
Copper Damascene Interconnects Integrated
with Low k- (FSG/USG) Dielectrics
Du Nguyen & Hazara Rathore
IBM Microelectronics
2070 Route 52 East Fishkill Facility
Hopewell Jct., NY 12533
Phone: (914) 892-3162
Fax: (914) 892-6850
Abstract:
The VLSI chip performance is improved
by the reduction of the RC constant. To reduce the
resistance, copper has been used as the conductor
for the VLSI interconnects. To reduce the
capacitance, fluorine silicon glass (FSG) is chosen
to be embedded with undoped silicon dioxide
(USG) to integrate with damascene copper
interconnects for enhancing the chip performance.
In this paper, we will attempt to illustrate that the
electromigration life time of single and dual
damascene lines which are insulated by a FSG
layer embedded with USG layer as the interlevel
dielectric (ILD) are excellent without any
degradation in life times due to the presence of
FSG. In addition to the electromigration data, we
will show interlevel voltage ramp data and limited
life stress data using copper electrodes.Experiment
The copper used for this experiment was an
electroplated (EP) copper. The EP copper was
deposited after the depositions of diffusion barrier
/ adhesion layer and copper seed layer. The EP
copper lines integrated with FSG / USG were
evaluated by using test structures with single
damascene and dual damascene line structures.
The test structure of a single damascene is built
from local interconnect level made of tungsten to
interconnect with metal stripe at level M1 by
interlevel contact via, CA. The M1 stripe wasformed by using a single damascene process which
was manufactured by using a FSG layer as an
interlevel dielectric (ILD). M1 trenches were
formed by using lithography processes and a RIE
etch step to etch into the ILD. After the M1
trenches were formed, a blanket deposition of
diffusion barrier / adhesion layers, copper seed
layer and then followed by an electroplated copper.
A chemical mechanical polishing (CMP) process is
used to remove the excess copper and liners in
forming single damascene copper stripes. A
blanket deposition of silicon nitride is deposited toencapsulated the copper lines as a capped layer to
protect any chemicals attack metal lines from the
top down. Following the single damascene stripe is
a dual damascene process which is used to form
both interlevel V1 vias and M2 stripes. A thick
layer of undoped silicon dioxide (USG) is
deposited with the thickness is the same as the
height of the V1 via, then follows by a FSG layer.
The thickness of the FSG is determined by the M2
thickness. In this experiment, a dual damascene
metal sequence is using a lithography process to
determine metal stripe trenches and a RIE process
to etch into ILD to form metal stripe trenches.
Using a lithography process again to determine via
opening and using RIE process to etch via holes.
After the trenches were formed for via and metal
stripes, diffusion barriers and copper seed layer
were deposited then follows by an electroplated
process to fill in to form a dual damascene
interconnect. A silicon nitride layer also used as an
encapsulated later. The process was repeated in the
same to form dual damascene metal stripe at M3
and M4, then the test structure is covered by thick
oxide and nitride layer for the final interlevel vias
to be ready for wire bonding. The test structure is
400 um long, .315um wide and 0.4 um deep. The
structure is a four point probe structure by having 2
pads for each end. One pad from each end is for
applying current source and the other pad is for
sensing the voltage. The test was conducted at 295
degree centigrade at 25.0 mA/um2. The failure
mechanism of dual damascene line when the
electrons flow from M1 go up to M2 is caused by
via depletion which shows voids formed in V1 or
on top of V1. When the electrons flow from M3
down to M2, the failure mechanism is line
depletion which shown by voids underneath of V2
via.
Because of CA made of tungsten, there is no
electromigration failure mode in single damascene
line but line depletion is the main failure mode in
both directions for M1.
Conclusions:
FSG is a good insulator to be integrated with
copper interconnects because it does not show any
degradation of electromigration life time and it
help to improve the chip performance.
References:
1) J.C. Maisonobe, G. Passemard, C. Lacour, P.
Motte, P. Noel, J. Torres, SILK Compatibility
with IMD Process Using Copper Metallization,Microelectronics Engineering 50 (2000) 25-32
2) E. Hartmannsgruber, G. Zwicker, K.
Beekmann, Selective CMP Process for Staked
low k- CVD oxide films, Microelectronics,
Engineering 50 (2000) pp. 53-58
3) Chanming Jin et al. Thermal Conductivity
Measurements of Low Dielectrics Constant Films,
DUMIC Proceedings, Feb. 20-21 1996
4) R. J. Gutmann et al, Integration of copper
multilevel interconnects with oxide and polymer
interlevel dielectrics, Thin Solid Films 270 (1995)
pp. 472-4795) M.J. Loboda, New Solutions for Inter metal
Dielectrics Using Trimethyl silane based PECVD
process, Microelectronics Engineering 50 (2000)
pp. 15-23
6) H. Rathore, D. Nguyen, L. Ashley, G. Biery, B.
Agarwala, T. Kane and P. Plaitz, Proceedings 16th
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Conference p. 89 (1999)
7) H. Rathore, D. Nguyen, MRS 2000, Spring
Meetings, p. 84 (2000)
8) H. Rathore, D. Nguyen, B. Agarwala, and L.
Ashley SemiconWest B-1 (1999)
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