Enabling System Level Design Optimization...© Zuken Zuken Corporate Profile Summary 3 1976...

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Hierarchical 3D-IC Design Enabling System Level Design Optimization

James Church

Solutions Architect

January 21, 2015

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Agenda

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• Corporate Introduction

• Design Trends

• System-level Co-design

• Case Studies

• Pathfinding

• Summary and Roadmap

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Zuken Corporate ProfileSummary

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1976

$202,920,030

Yokohama, Japan

Munich, Germany

Westford, Massachusetts

Tokyo Stock Exchange Level-1

1,171

Profitable, no debt

Founded

Revenue Year Ended March 2014

Corporate Headquarters

European Headquarters

North American Headquarters

Stock Listing

Employees

Operational Excellence

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Global OrganizationMore Than 30 Offices Worldwide

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Zuken USA Inc.North AmericanHeadquarters

Zuken Inc.WorldwideHeadquarters

Zuken GmbHEuropean Headquarters

Zuken GmbHEuropean HeadquartersMunich, Germany

Zuken Inc.Worldwide HeadquartersYokohama, Japan

Zuken USA Inc.North American HeadquartersWestford, Massachusetts

SOZO Center

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Zuken Corporate ProfileWhat We Do

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PCB Systems IC Packaging

Wiring and Control Systems

We partner with our customers to develop and

deliver software and services to improve our

customers’ business success

• Software development, sales, and support

• Implementation and integration services

• Process automation and optimization

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Design Trends

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Trends in Technology

Applications vs. IC Packaging

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2014 - 2019

Advancement

in cloud

computing

and “Big Data”

Growth in

wearable

devices

Ongoing

integration of

smart devices

Increased

implementation

of gestural

computing

Expansion of “smart”

application in

automotive, healthcare,

and other industries

(Source: STATSChipPAC)

Continuous innovation in

technology will require

advancement in IC packaging

technologies.

This includes substrate/silicon

interposer design and 3D

IC/TSV, and careful

implementation of high-speed

interfaces!

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Historic System-level Design Challenges

• Single design tool view prevents system level optimizations and

leads to over-margining

• Discrete design and planning databases create gaps in

constraints, data fidelity/coherency and IP reuse

• Lack of ECAD and MCAD integration under-constrains design

before prototyping

• Neutral file interchange formats have scant ECO support and are

easily out of synch with current design status

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System-level Co-design

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System-level Co-design Challenges

System

Co-Design

ICs

Interposers

Package

SiP

PoP

PCB

FPCB

Rigi-flex

Mechanical Enclosure

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2.5/3D design,

optimization, and

visualization

Net assignment,

routability and

performance

Simulation and

Analysis:

Thermal, EM, RF

Electrical

Mechanical

DRC, MRC rules and

electrical and physical

constraints

Support for any

combination of co-

design is key!

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Feasibility and Design

Chip/Package Co-designRDL/IO/bump Optimization

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4 PKG Layer

(1-2-1)

6 PKG Layer (2-

2-2 )

8 PKG Layer (3-

2-3)

Package Routing

Feasibility Studies

RDL Route (LSI side) Escape Route (PKG side)

• Constraint Driven Route

Pathfinding

• Fan Out/In

• RDL

• Die Escape

• Bump ‘Tile’ Macros

• Supports System Level

Hardmac P&R

• Known RDL+Escape

Solutions

• Constraints Driven Pin

Optimization

• Dsgn/Mfr. Rules

• Interface Constraints

• Routing Layer

Availability

• Partial Routes

• OpenAccess IC Format

• LEF/DEF & GDS

Import/Export

• “In situ” Feasibility

• Route Feasibility &

Design in One Tool

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Interposer Co-designManaging complex designs with TSVs

• Floorplanning of stacked/adjacent chips with TSV and Si-Interposer

– Routing to fixed TSV on interposers from 1 or 2 sides

– Solve the routing of chip RDL and fixed layer count interposer

– Generate power/ground mesh in Si-Interposer

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Front Side

Package

Silicon Substrate

Back Side

Front Side

Silicon Substrate

RDL

RDL

Micro Bump

FC Bump

Die 1

Die 2 TSV

Si-Interposer

chip chip

TSV

Package

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Advanced Package Co-designPoP/SiP/WLP design

• System-level co-design enables intelligent PoP and SiP design

– Seamless connection of independent databases

– Focused design rule checks for PoP/SiP with real-time 3D view

– Support for complicated bond wire placement of stacked die

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3D DRC for

bond wires

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Package/PCB co-designMulti-PCB/Flex

• Conduct real-time pins swaps

between package and board

– Improve routability with automatic or

interactive untangling of nets

– Improve signal performance and

power delivery

– Eliminate exchange of CSV or other

neutral files to communicate change

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PCB Design PKG Design

Net SwapReflect

Hierarchical structure of package and board

CSV

AF1 AF2 AF3 AF4

AE1 AE2 AE3AE4

NET220

AD1 AD2 AD3AD4NET219

AC1 AC2AC3NET2

Pin NumberNet Name

BGA Package Component

CSV File

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• Supports state-of-the-art chip design with unique package

technologies with multi-board integrated design

– Optimize I/Os across the system in real-time

– Conduct design trade-offs for various form factor or application

– Consider board-level issues concurrently with the mixture of above

technologies and SiP

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3D-IC

System-level Co-designSoC/SiP/PCB

Multi-database Embedded Devices

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Electromechanical Co-Design

• 3D environment enables design

to true mechanical constraints

• Identify critical placement issues

early in the design process

• Conduct measurements and

collision checks for optimal

floorplanning

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System Co-design Case Study:

Portables

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μS D

U S B

H D M IBattery

CP

U

DRA

M

eMM

C

SSD

LCD

H e a d

W

i

F

i

Module areaNew communication

function

Almost all domains are modules

Case Study: System-level Co-design

• Challenges in form

factor-driven design:

– RF module

placement

– Physical

specifications

– Thermal dissipation

– Form and fit

– Product cost

– Package technology

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Case Study: System-level Co-design

Profile of chip is too thick to be

embedded within module

package

Existing RF module has to be

redesigned to meet new form

factor requirements

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Shrink module size 6mmX8mm⇒ 4.5mmX6mm

It is difficult to place all components on surface

Module height 1.7mm⇒1.0mm

Custom LSI won’t go into the module

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Case Study: System-level Co-designOptimizing Signals in the System

• Chip RDL routing optimized in context to the module and PCB

without die redesign

• 3D rule and technology update enabled embedding and physical

verification to new form factor specification

RDL

Package on

PCBModule + RDL

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System Co-design Case Studies:

2.5D/3D Systems

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Case Study: eWLB Wide IO Memory Design

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3D-IC System level Design • eWLB• 2 Embedded openAccess

IC databases• PoP Memory• Memory

System Level Constraints and Netlist

3D Editing of Native Database

Hierarchical System Architecture

IC Hardmacro

and Routing

IC2

IC1

PoP

Embedded

Substrate

3D-IC

IC2

IC1

PoP

Embedded

Substrate

3D-IC

(Image: STATSChipPAC)

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System Level Co-Design Functionality Execution in Multi-board Database

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System Level

Net Swap

without .CSV

3D Design in System

Level Visual Context

IC HardMacro

WLP Routing

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Stacked 3D Pathfinding:System “Best Pin” Pathfinding in Native Design Tool

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IC Hardmacro

IC Hardmacro

IC2

IC1

PoP

Embedded

Substrate

IC2

IC1

PoP

Embedded

Substrate

IC2

IC1

PoP

Embedded

Substrate

IC2

IC1

PoP

Embedded

Substrate

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Stacked 3D Pathfinding:Verification and ECO Management

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LPB Format

Netlist

Verification

ECO

Management

IC2

IC1

PoP

Embedded

Subtrate

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Pathfinding:

Logical, Physical & Cost Planning

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Pathfinding: Logical, Physical & Cost Planning

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Pathfinding:

Logical, Physical & Cost Planning

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Cost, Weight, Power

Analysis vs. Specification

Component Cost

Information

Component Weight &

Power Floorplan

Driven

Functional

Partition

Driven

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Pathfinding: Logical, Physical & Cost Planning

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System A System B

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Pathfinding: Planning to Realization….Planning vs. Final

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• IP Reuse

• Planning vs.

Design

Coherency

• Properly

Constrained

Planning

• Planning

Constraints

Transferred to

Design Stage

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Roadmap and Summary

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Roadmap

• System-level, Constraint-driven Design

– System level physical and electrical constraints

– Reduce program cost due to system over-constraining

– System & Component PDK

• System-level analysis

– Integrated cross module physics simulation, meshing and modeling

– Removal of artificial modeling discontinuities at component

boundaries

• Expanded system path-finding with IP reuse

– System planning and path finding with direct translation to

constraints and design jumpstart

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Summary: Co-Design EDA Requirements

• 3D platform with dedicated DRCs to ensure system level physical

verification and provide system level product insight

• Use of independent, but connected databases to provide opportunities

for system optimization throughout the design process

• Pin assignment and routing automation to enable realizable path finding

and quick turn ECO changes

• System level electrical and mechanical collaboration and checking to

ensure realizable design

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