FIR Filter Model

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-- FIR Filter Model

--

-- +-----------------------------+

-- | Copyright 1996 DOULOS |

-- | Library: DSP |

-- | designer : Tim Pagden |

-- | opened: 30 Sep 1995 |

-- +-----------------------------+

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.types.all;

library maths;

use maths.maths_class.all;

library matrix;

use matrix.matrix_class.all;

entity FIR_32tap_8_8 is

port (

a : in std_logic_vector(7 downto 0);

b : in logic_8_vector(31 downto 0);

clock : in std_logic;

reset : in std_logic;

y : out std_logic_vector(20 downto 0)

);

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end FIR_32tap_8_8;

architecture behavioural of FIR_32tap_8_8 is

constant number_of_taps: integer := 32;

signal data_table: single_vector(number_of_taps-1 downto 0);

signal coefficient_table: single_vector(number_of_taps-1 downto 0);

begin

-- y

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begin

if rising_edge(clock) then

-- data_table_var := data_table(number_of_taps-1) &

data_table(number_of_taps-2 downto 0);

-- putting the coeff table in a loop like this allows dynamic coeff updating

for i in 0 to number_of_taps-1 loop

coefficient_table_var(i) := single(to_integer(unsigned(b(i))))/127.0;

end loop;

-- tmp := reverse_order(data_table_var);

-- tmp2 := 0.15; + to_integer(a);

data_table_var := data_table;

tmp2 := single(to_integer(signed(a)));

data_table_var := shift_fifo (data_table_var, tmp2); -- fifo => data_in =>

data_table 0,

upper_limit => number_of_taps-1,

a_in => reverse_order(data_table_var),

b_in => coefficient_table_var

);

y_result := to_signed(integer(fir_result), y_result'length);

y

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end if;

end process;

end behavioural;

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VHDL code for a 4 tap FIR filterFinite Impulse Response(FIR) filters are one of the two main type of filters available for

signal processing. As the name suggests the output of a FIR filter is finite and it settles downto zero after some time. For a basic FAQ on FIR filters see thispost by dspguru.

A FIR filter output, 'y' can be defined by the following equation:

Here, 'y' is the filter output, 'x' in the input signal and 'b' is the filter coefficients. 'N' is the filterorder. The higher the value of N is, the more complex the filter will be.

For writing the code in VHDL I have referred to the paper,VHDL generation of optimized FIRfilters, available online. You can say I have coded the exact block diagram available in thepaper, "Figure 2".

This is a 4 tap filter. That means the order of the filter is 4 and so it has 4 coefficients. I havedefined the input as signed type of 8 bits wide. The output is also of signed type with 16 bitswidth. The design contains two files. One is the main file with all multiplications and addersdefined in it, and another for defining the D flip flop operation.

The main file is given below:

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.NUMERIC_STD.ALL;

entity fir_4tap isport( Clk :instd_logic;--clock signal

Xin :insigned(7downto0);--input signalYout :outsigned(15downto0) --filter output);

end fir_4tap;

architecture Behavioral of fir_4tap is

componentDFFisport(

Q :outsigned(15downto0); --output connected

to the adderClk :instd_logic; -- Clock inputD :in signed(15downto0) -- Data input from the

MCM block.);

endcomponent;

signal H0,H1,H2,H3 :signed(7downto0):=(others=> '0');signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 :signed(15downto0):=(others=> '0');signal Q1,Q2,Q3 :signed(15downto0):=(others=> '0');

begin

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--filter coefficient initializations.--H = [-2 -1 3 4].H0

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architecture Behavioral ofDFFis

signal qt :signed(15downto0):=(others=> '0');

begin

Q '0');constant Clk_period :time:=10ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)uut:entitywork.fir_4tap PORTMAP(

Clk => Clk,Xin => Xin,Yout => Yout

);

-- Clock process definitionsClk_process :processbegin

Clk

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Clk