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FPGA 2011 Pre-Conference Workshop:
The Role of FPGAs in a Converged Future with
Heterogeneous Programmable Processors
Organizers: Jonathan Rose, University of Toronto
Guy Lemieux, University of British Columbia
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Motivation for this Topic
The battle of fixed function systems vs. programmable devices has been won
By The Programmables; Not Just FPGAs, though: Programmable Instruction
Processors – CPUs, GPUs, processor arrays …
Next Question
What kinds of programmability to place on next generation systems/devices? – Different hardware and software programmability succeeds (CPU,
GPU, FPGA) for different apps
Future systems may need all three types – and perhaps interesting mixtures and variants of these – particularly true when optimizing cost, speed & energy
Anticipate converged device that contains all three What role can the FPGA play?
How should it evolve?
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We’d Like To Create a Good Discussion
Experiment with new methods of workshop interaction:
1. We’ll ask reflective questions
2. Solicit one slide responses from audience – If you have some thoughts, feel free to create a slide on
computer at side
3. Audience Interaction through wandering around with microphones
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Goals & Origin of Workshop
This workshop arose from last August’s Cascadia workshop at UBC in Vancouver, which was a big discussion with these people:
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Name Organization
Adam Donlin Xilinx (San Jose)
Alessandro Forin Microsoft Research
Andre DeHon U Penn
Andrew Putnam Microsoft Research
Andy Ye Ryerson
Greg Steffan U. Toronto
Guy Lemieux UBC
Jan Gray Gray Research
Jason Anderson U. Toronto
Jonathan Greene Actel
Jonathan Rose U. Toronto
Name Organization
Joseph Skudlarek Cypress
Ken Eguro Microsoft Research
Kenneth Kent UNB
Lesley Shannon SFU
Mike Butts NVIDIA
Paul Chow U. Toronto
Paul Leventis Altera
Satwant Singh Lattice
Sinan Kaptanoglu Actel
Steve Wilton UBC
Tomasz Czajkowski Altera
Wayne Luk Imperial
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Driving Applications
Middleware/Overlay Architectures
Intermediate Format
Computation Hardware CPU, GPU, FPGA, Other mixtures
API / Platform Abstraction Layer
Compilers
Languages
Specification Exploration
Programming Models; Compute Models
Run time / OS adaptation
The Ecosystem Stack
Ada
ptin
g to
Pro
cess
Te
chno
logy
Para
lleliz
atio
n an
d Sc
alab
ility
Easy C
omm
unication of Intent Li
brar
ies
Computational Stack of the Future?
Verification
Workshop Sessions
Session 1: Future-Looking Applications
Session 2: Architectures and Systems
Session 3: Languages, Compilers and Synthesis
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Full Schedule Time Title Who 1:30pm Introduction & Format Rose, Lemieux
Session 1: Future Applications 1:40pm Billions of Packets per Second Mendel
2:05pm FPGA enters the enterprise: Exemplars and outlook for reconfigurable computing in mainstream IT infrastructure Blainey
Session 2: Architecture & Systems 2:30pm
Configurable Platforms in the Low Power Embedded Division at Intel Willis
2:55pm 'Project Denver' Processor to Usher in a New Era of Computing Butts
3:20pm 25 minute break
Session 3: Compilers and Synthesis 3:45pm
Improving FPGA designer productivity using OpenCL, Deshanand Singh, Altera. Singh
4:10pm Programming Systems Consisting of Processors and FPGA Technology Vissers
4:35pm Programming Models for the AMD Processor/GPU Hybrid Fusion Gaster
5:00pm Summary & Conclusions All (8)
Session 1: Applications
1. Billions of Packets per Second – David Mendel, Altera Corporation
2. FPGA enters the enterprise: Exemplars and outlook for reconfigurable computing in mainstream IT infrastructure – Bob Blainey, IBM.
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Session 2: Architectures & Systems
1. Configurable Platforms in the Low Power Embedded Division at Intel – Thomas Willis, Intel.
2. 'Project Denver' Processor to Usher in a New Era of Computing – Mike Butts, Nvidia
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Session 3: Compilers/Synthesis
4:10pm Start Time
1. Improving FPGA designer productivity using OpenCL – Deshanand Singh, Altera
2. Programming Systems Consisting of Processors and FPGA Technology – Kees Visser, Xilinx
3. Programming models for next generation of GP GPU architectures – Benedict Gaster, AMD
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Complete Schedule Time Title Who 1:30pm Introduction & Format Rose, Lemieux
Session 1: Future Applications 1:40pm Billions of Packets per Second Mendel
2:05pm FPGA enters the enterprise: Exemplars and outlook for reconfigurable computing in mainstream IT infrastructure Blainey
Session 2: Architecture & Systems 2:30pm
Configurable Platforms in the Low Power Embedded Division at Intel Willis
2:55pm 'Project Denver' Processor to Usher in a New Era of Computing Butts
3:20pm 25 minute break
Session 3: Compilers and Synthesis 3:45pm
Improving FPGA designer productivity using OpenCL, Deshanand Singh, Altera. Singh
4:10pm Programming Systems Consisting of Processors and FPGA Technology Vissers
4:35pm Programming Models for the AMD Processor/GPU Hybrid Fusion Gaster
5:00pm Summary & Conclusions All (12)
Session 1 Reflective Questions
1. What are the key driving applications for general heterogenous computation?
2. What characteristics of applications make them suitable for GPGPU? FPGA? DSP?
3. What are the “killer apps” for an FPGA that gives it an entry into the converged device?
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Session 2 Reflective Questions
1. Where do massively parallel arrays of processors fit in? – Many lighter-weight processors vs. fewer heavy-weight
2. Can FPGAs evolve to be better at instruction set processing?
3. Where do coarse-grained FPGAs fit into the hybrid CPU, GPU, MPPA space?
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Session 3 Reflective Questions
1. What are the standard platforms for benchmarking CPU vs. GPU vs. FPGA – e.g. good C-to-gates?
2. Good hardware designers craft perfect flow of data. Can compilers come anywhere near this?
3. How can FPGA compile times be brought down to the same realm as instruction-set compile times.
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Questions
1. What future applications (or parts of applications) can be driven by FPGAs?
2. Where do FPGAs fit into the architecture realm of CPUs, general purpose GPUs, and DSPs?
3. How should the designer/programmer express their intent in the most effective way possible?
4. What are the requirements for a compilation and synthesis environment that allow FPGAs to intermix within a heterogeneous system?
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Outcomes
Collaborative effort(s) to build/glue a useful computational stack? – How to proceed – What are the next steps?
– Must be incremental and achievable steps.
– Needs a champion
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Goals of this Workshop
1. Hear invited industry speakers on these topics
2. Use this to launch a discussion within our community, – of the future role and nature of FPGAs
3. Influence research directions
4. Create new, larger collaborations
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