View
241
Download
1
Category
Preview:
Citation preview
Fundamentals ofFundamentals of EMI
Chris HerrickAnsoftAnsoft
Applications Engineer
Three Basic Elements of EMCThree Basic Elements of EMC
EMI sourceEMI sourceEmission
Space & FieldConductionCoupling process
Capacitive Inductive RadiativeConductive
Low & Middle Frequency High FrequencyLow, Middle & High Low & Middle FrequencyLC Resonance
High Frequency, gFrequency
Immunity
EMSEMS
Immunity
Controlling EMIControlling EMIEMI sourceEMI source Emission
Space & FieldConduction
Coupling processShieldsShieldsEMI FiltersEMI Filters
Capacitive Inductive RadiativeConductive
Space & FieldConduction
Low & Middle FrequencyLC Resonance
High FrequencyLow, Middle & HighFrequency
ShieldsShields ShieldsShields ShieldsShieldsEMI FiltersEMI FiltersLC ResonanceFrequency
EMS
ImmunityImmunity
PCB Noise Sources
Intentional SignalsIntentional SignalsEmissions from intentional signals include loop-mode and common-mode sources.
Unintentional Signals ( more than 90% of EMI )E i i f i t ti l i l i l d dEmissions from unintentional signals include common-mode, crosstalk coupling to I/O traces (both PCB and IC level), power planes, and above board structures.
*Reference from “PCB Design for Real-World EMI C t l ” BEMI Control,” Bruce Archambeault
Intentional SignalsIntentional SignalsFocus on Clock and High Speed Signals
Stripline not necessarily better than MicrostripExamine Clock Harmonics
Common Mode ConversionSCD11=0.5*(S11-S13+S31-S33)SCD21=0.5*(S21-S23+S41-S43)
Unintentional SignalsUnintentional Signals
Crosstalk is a big concernCrosstalk is a big concernBeware the low speed nets; use post-layout analysis to scan for unintended couplinganalysis to scan for unintended couplingCoupling may be direct, through intermediate metal or even from plane cavitiesmetal or even from plane cavities
Common mode will always existDon’t neglect the overall plane impedanceDon t neglect the overall plane impedance
Loop Mode & Common Mode NoiseA PC Board & Cables
Loop modet
A victim device
current
A Driver & Receiver by AC Analysis of Q3D ExtractorQ3D Extractor
Differential mode current flows --- LoopCommon mode current flows --- Open
We can see Common mode current is more serious than Normal mode.
Common modecurrent
Antenna theoryAntenna theory-A Differential mode current flow Loop antenna theory-A Common mode current flow Dipole antenna theory
rθAI)(f.E
- sin106131 216×=
rlIfE θπ sin)(104 7−×
=
r : distance rA : area of the loop
θ θ
Length :l
p
IIIllustration of a loop antenna Illustration of a dipole antenna
FCC B level Mag. E limit :40dBuV/m @ 3mMag E( Loop antenna) : 20mAMag. E( Loop antenna) : 20mAMag. E( Dipole antenna) : 8uA
EMC Design FlowEMC Design FlowImpedance Analysis
Ensure a low impedance as seen by active parts
Ch t k l t t d
Resonance Analysis
Change stackup, plane cutouts and decoupling as necessarySignal Extraction
Emissions Analysis
Enclosure Simulation
Decoupling CapacitorDecoupling Capacitor on Package
ChipVia
On-chip Pwr/GndVRM
V a
Ball Bonding
Power/Ground
Wire Bonding Ball Bonding VRM
PCB P/G Network
Package P/G Network
Chip Decoupling Capacitor on Chip
Decoupling Capacitor on Package
Decoupling Capacitor on PCB
Bulk Capacitor Near VRM
Decoupling Impedance of PDN
Bare PCB0.01uF
0.1uF
1uF1uF
10uFTotal PDN
Plasma Screen ExampleChanged Return Path
•Widened section of GND plane•Added decoupling CapacitorsAdded decoupling Capacitors
GND
GND
New modelOld model
Impedance test port near C3,4,5
Impedance Plotp
Impedance : Old model
Impedance New model
EMI Test Results : Old model
CISPR spec.
EMI Test Results : New model
EMC Design FlowEMC Design FlowImpedance Analysis Ensure power planes do not resonant in
critical locations
Resonance Analysis Change stackup, plane cutouts and decoupling as necessary
Signal Extraction
Emissions Analysis
Enclosure Simulation
Managing ResonancesManaging ResonancesEven though resonances ALWAYS exist, you don’t need to excite them:
Keep them away from Clock harmonics
y
p yExamine Via TransitionsAvoid routing near splitsAvoid routing near splitsMove discrete parts
VCC12VCC12
544 MHzZ11
544 MHz
18
EMC Design FlowEMC Design FlowImpedance Analysis
Resonance Analysis
Ensure signals meet required
Signal Extraction
Ensure signals meet required bandwidth
Change routing as necessary
Emissions Analysis
Enclosure Simulation
Image Plane Violations
Always Consider Return Current Path Capacitor bridging
the moat to transfer RF currents between partitions
RF current return pathp
Signal Trace Moat or slot in gground plane
EMI Reduction using Ferrites
Insert High Q FerriteInsert Low Q Ferrite
Without Ferrite
Internal Clock Line
EMI Test Results
B f F itBefore Ferrite
After FerriteAfter Ferrite
Clock Distortion
Clock Distortion
Clock Distortion
Clock Distortion
Clock Distortion
Clock Distortion
EMC Design FlowEMC Design FlowImpedance Analysis
Resonance Analysis
Signal Extraction
Ensure EMI is at acceptable level
Optimize previous three simulations
Emissions Analysis
Optimize previous three simulationsEnclosure Simulation
Full Channel Analysis
DCSupply
0
A A
A
DC Supply00
A A
U1_8VCC_1GNDU1_pair1_negU1_pair1_pos
U2_1VCC_1GNDU2_pair1_negU2_pair1_pos
VC
C_m
ain
100
R545
100
R546
inn
inp
outn
outpdiffout_probe
Vcc
Vss
100
R558
R5590.5/
data
rate
C56
0
0.1
R563
R564
inn
inp
outn
outpdiffout_probe
Vcc
Vss
SI M d l
Load
0
V475 V541
1000.1 SIwave Model
Differential PRBS
0
Real Drivers as Noise Source
MaxE Radiated from PCB
PCB Data-Line Source spectrumSource spectrum
Near-Fields
VV
High |Z| at 137 MHzHigh |Z| at 137 MHz
Low |Z| at 50 MHz
EMC Design FlowEMC Design FlowImpedance Analysis
Resonance Analysis
Signal Extraction
Test performance of different
Emissions Analysis
Test performance of different enclosures
Iterate design as necessary
Enclosure Simulation
Linking EMI Source with ShieldLinking EMI Source with ShieldA noise analysis by SIwave
A excitation source
SIwave to HFSSHFSS to HFSS
A ECU analysis by HFSS
A EM analysis by HFSS
A noise source and a cableA noise source and a cable
310 MHz ImpedanceImpedance Peak on PCB
A cable
ConclusionsConclusions
It’s easiest to control EMI at it’s sourceIt s easiest to control EMI at it s sourcePrevents Emission and Self Interference
EMC is comprised of good PI and SIEMC is comprised of good PI and SISimulating throughout the design cycle can help you avoid trouble in the chamber
Recommended